TW410444B - Substrate having gate slots and molding device and molding method thereof - Google Patents

Substrate having gate slots and molding device and molding method thereof Download PDF

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Publication number
TW410444B
TW410444B TW086116765A TW86116765A TW410444B TW 410444 B TW410444 B TW 410444B TW 086116765 A TW086116765 A TW 086116765A TW 86116765 A TW86116765 A TW 86116765A TW 410444 B TW410444 B TW 410444B
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Taiwan
Prior art keywords
gate
substrate
resin
mold
groove
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TW086116765A
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English (en)
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Hong-Woo Lim
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Trimecs Co Ltd
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Publication of TW410444B publication Critical patent/TW410444B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)

Description

經濟部中央標隼局負工消費合作社印製 A7 B7 五、發明説明（1 ) 發明領域 本發明是關於一種半導體封裝（package)用之基板， 尤指一種具有成型樹脂流動用之閘槽的基板，以及該基板 所使用之相關模製裝置及模製方法》 發明背景 製造半導體晶片封裝之一般步驟包括使半導體晶片附 著於一基板上的晶片附著蟲成型樹脂使半導體晶片 成型以保護半導體晶之間之電性連接的成型步 驟，以及將成型的半片切割爲個別晶片的切割步 驟β在球格陣列型態半導體中，基板是由複數被壓成薄板 之具有電路圖案的薄樹脂片所形成。 圖一表示習知之基板而圖二表示習知的樹脂形成鑄 模。在基变1 0 0的表面上具有複數用以附考ϋ體墨片1 〇 3 的晶片接:點2 0，在個別的晶片接點2 0的另一邊具有供成型 樹脂流動之樹脂路徑102。於半導體晶片103於基板100上 被結合（bonded)時，基板100被放置於上鑄模70與下鑄模 72之間，然後成型樹脂82藉由活塞84被注入鑄模70,72之 中空部份，因而形成半導體晶片封裝。 然而，當樹脂沿樹脂路徑1 0 2流動時，在樹脂固化後 一些殘留的樹脂附著於樹脂路徑1 0 2上。因爲些殘留的樹 本纸張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再嗔寫本頁)
經濟部中央標準局員工消費合作社印製 ^10444 ΑΊ ____Β7 五、發明説明（2 ) 脂可能造成半導體晶片的缺陷，所以需要移除殘留樹脂的 步驟（degating process)。當殘留的樹脂從基板1 0 0上的樹脂路徑 102去除時/可能產生中間層的脫落。爲解決此問題，在 基體100的樹脂路徑102上提供金或其它金屬使殘留的樹脂 的移除變得容易。 然而，對於以金表面化的基板而言，需要平坦化設備 及人力，這產生較高成本的半導體晶片封裝。 發明綜合說明 本發明之一目的在藉由提供具有閘槽的基板而解決上 述問題，可以降低半導體模製過程中之成本及改進生產 率〇 本發明之另一目的在提供可使用上述閘槽基板之模製 裝置及模製方法。 依據本發明，提〇，具有多數用以附著半導 體晶片之晶片接點2 徵在於複數閘槽30形成於沿基 板10上對應鑄模70之樹脂路徑102之處，且該閘槽30從該 基板10之邊緣伸展至該成型封裝101之旁》 依據本發明另一形式，該閘槽30係矩形，細圓形或橢 圓形。 本發明亦提供一種半導體封裝模製裝置用以成型具有 閘槽30之基板10之上的半導體晶片103，其特徵在於該鑄 本紙張尺度適用中國國家標率（CNS > Λ4規格（210Χ 297公釐） * · ------------^費------ΪΤ丨 ----β (請先閲讀背面之注^^>項再填寫本頁) A7 B7 ^10444 五、發明説明（3 ) 模之閘被分爲位於樹脂埠78或滑道80側邊的第一閘50及位 於鑄模之中空部74之側邊的第二閘60，且於第一閘5〇與第 二閘60之間具有面對基板1〇之該閘槽之閘關閉部76。 本發明也提供一種半導體封裝模製方法，包括下列步 驟：半導體晶片1 0 3被附著於具有閘槽3 0之基體1 0之晶 片接點20的結合（bonding)步騾，半導體晶片103與 10被電性連接之打線（wire bonding)步驟’將基板1%^ 置於鑄模70與72之間的鑄模夾持步驟，其中該等鑄模包括 對樹脂埠78或滑道80打開的第一閘50及向鑄模之中空部 7 4打開的第二閘7 4以及位於第一閘5 0與第二閘6 0之間的 閘關閉部76，使樹脂從樹脂埠78經由第一閘5 0及閘槽30 流入中空部7 4的樹脂注入步驟，焊接球4 0被結合於基板1 〇 底部的焊接球結合步驟，以及省略淸除（degating)步驟使 基板1 0被切割爲獨立半導體晶片的切割步驟。 圖式簡要說明 圖一係習知基板之平面圖， 圖二係習知半導體封裝鑄模的截面圖， 圖三係本發明一實施例之基板的平面圖， 圖四係本發明半導體封裝鑄模之截面圖， 圖五係本發明上鑄模之底視圖， 圖六係本發明充滿樹脂之鑄模之部份視圖， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公瀣） 11= - -HI 1 - - - I —- —I ^^1 I (請先閲讀背面之_事項再填窝本瓦) 訂 Φ 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消费合作社印裝 410444 a? __B7 五、發明説明（4 ) 圖七及八係本發明個別的半導體封裝，及 圖9a，9b係不同型態之閘槽的部份視圖。 發明詳細說明 本發明之一較佳實施例將參照圖式而說明。 如圖三所示，在藉由黏著多層薄樹脂片至預定厚度所 形成之基板10之上具有晶片接點20，因此多數的半導體晶 片可以附著於其上，在個別晶片接點2 0的另一側，閘槽3 0 沿樹脂路徑1 0 2開孔且位於沿基板1 0邊緣相同的間隔之 處。閘槽3 0的內端沿伸至成型封裝1 〇 1的旁邊，但不伸入 成型封裝101之內。因此，如果基板10北夾持於上鑄模70 與下鑄模72之間，溶解的樹脂可以從形成於鑄模外部之第 一閘5 0經由形成於基板1 0之上的閘槽3 0流動至形成於鑄模 內部之第二閘6 0。 閘槽30可以是矩形，細圓形，橢圓形弓形，或弧槽， 或任何可以構成樹脂路徑之主要形狀。圖九舉細圓形閘槽 30a及弓形閘槽30b爲例。 參照圖四及五，本發明之鑄模之閘被分爲第一閘50及 第二閘6 0。第一閘5 0係位於樹脂埠7 8或滑道8 0之側邊， 而第二閘6 0係位於鑄模之中空處7 4之側邊。在第一閘5 0與 第二閘60之間具有關閉部76延伸至上部鑄模70之底表面。 閘關閉部7 6面對位於下部鑄模7 2上之基板1 0的閘槽3 0。 本紙張尺度適用中國國家標準（CNS ) A4規格（2Ϊ0Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) . r \ |:' -----I I --- ^^1 ί- . i m - :r_ - - I— -- I - m - ,一'?T - ΙΊ -^--^I _ Ϊ —hi I - -Ϊ n A7 B7 410444 五、發明説明（5 ) 依據上述鑄模的結構，經過第一閘50的溶解樹脂的流動應 該被閘關閉部7 6阻擋，然後跳過閘槽30而經過第二閘60而 最後將進入中空部份7 4。 圖六表示中空部74及閘部50,30,60被充滿樹脂。圖 七及八表示個別的半導體封裝，其中在使用閘槽基板及本 發明鑄模及焊接球40被結合在基板10之下表面之後，基板 10的週邊框將被切除。 尤其是，殘留在第一閘50之內及閘槽30之主要部份內 的樹脂應該在切割個別晶片的步驟後被移除，而第二閘6 0 內的殘餘樹脂將不被移除。但殘留的樹脂極小因此不會造 成實質製程上或使用上的麻煩。因此，從基板10移除殘餘 樹脂的部驟將可以省略，如此可以省略製程步驟並降低成 本。 如上所述，依據本發明，僅藉由在基板上提供閘槽及 簡單地改變鑄模的結構就可以不需要及省略半導體封裝成 型製程中在半導體基板上的樹脂路徑之金平坦化或其它處 理，因此產生半導體封裝的製程可以7顯著地改進因而提高 產能。 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消费合作社印製 本纸張尺度適用中國國家標準（CNS ) A4現格（210X297公麓}

Claims (1)

  1. A8 B8 C8 D8 410444 六、申請專利範圍
    1. 具有多數用以附著半導體晶片之晶片接點 20，其特徵在於複數閘槽30形成於沿基板10上對應鑄模 70之樹脂路徑102之處，且該閘槽30從該基板10之邊緣伸 展至該成型封裝10 1之旁。 2·如申請專利範圍第〖項之基板，其中該閘槽30係矩彤， 細圓形或橢圓形。 3. —種半導體封裝楔製裝置，用以成型具有閫槽30之基板 10之上的半導體晶片103，其特徵在於該鑄模之閘被分爲 位於樹脂埠7 8或滑道8 0側邊的第一閘5 0及位於鑄模之中空 部7 4之側邊的第二閘6 0，且於第一閘5 0與第二閘6 0之間 具有面對基板10之該閘槽之閘關閉部76。 經濟部中夬標準局員工消費合作社印製 -----------! (請先閱磺背面之逄意事項再填寫本買j "· 4. 一種半導體封裝模製方法，包括下列步驟：半導體晶片 1 0 3被附著於具有閘槽3 0之基體1 0之晶片接點2 0的結合 (bonding)步驟，半導體晶片103與基體10被電性連接之 打線（wire bonding)步驟，將基板10放置於鑄模70與72 之間的鑄模夾持步驟，其中該等鑄模包括對樹脂埠7 8或滑 道8 0打開的第一閘5 0及向鑄模之中空部7 4打開的第二閘 7 4以及位於第一閘5 0與第二閘6 0之間的閘關閉部7 6，使 樹脂從樹脂埠7 8經由第一閘5 0及閘槽3 0流入中空部7 4的 樹脂注入步驟，焊接球40被結合於基板10底部的焊接球結 合步驟，以及省略淸除（degating)步驟使基板10被切割爲 獨立半導體晶片的切割步驟。 本紙張尺度適用+國國家標準（CNS ) A4規格（2丨0 X 297公釐）
TW086116765A 1997-06-27 1997-11-10 Substrate having gate slots and molding device and molding method thereof TW410444B (en)

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KR1019970028254A KR19990004211A (ko) 1997-06-27 1997-06-27 게이트슬롯이 형성된 서브스트레이트

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TW410444B true TW410444B (en) 2000-11-01

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US (1) US6013947A (zh)
JP (1) JPH1126489A (zh)
KR (1) KR19990004211A (zh)
SG (1) SG72771A1 (zh)
TW (1) TW410444B (zh)

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US6013947A (en) 2000-01-11
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KR19990004211A (ko) 1999-01-15

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