407341 A7 48 7 1twf.doc/008 五、發明説明（/ )407341 A7 48 7 1twf.doc / 008 V. Description of the invention (/)
I 本發明是有關於一種動態隨機存取記憶體(DRAM)的製 造方法，且特別是有關於一種在動態隨機存取記憶體之記, 憶胞(memory cell)中，形成接觸窗開口的方法。 當電腦微處理器功能逐漸增強、軟體所進行的程式與 運算愈來愈龐大時，對於記憶體的容量需求也就愈來愈 高，而增加記憶體容量的方法之一就是增加積集度。 當DRAM製程到達0.18微米以下時，其中一種增加 積集度的製造方法，係於記憶胞中形成源極/汲極區之接 觸窗開口的同時，在接觸窗開口相鄰之閘極的側壁上形成 氮化矽閘極間隙壁。當製作接觸窗開口時，首先蝕刻作爲 絕緣層之氧化矽層，其必須使用高選擇比(high selectivity) 之飩刻劑，避免在蝕刻氧化矽層時，氮化矽損失太多，影 響間隙壁的形成。接著，再以低選擇比之蝕刻劑蝕刻氮化 矽層，形成氮化矽閘極間隙壁。 然而，形成此接觸窗開口時，在開口底部容易有聚合 物(polymer)的殘留，造成在形成接觸窗插塞時，因爲殘留 之聚合物而使的接觸窗插塞之接面電阻升高。 因此，本發明提供一種接觸窗開口的製造方法，可避 免聚合物在接觸窗開口底部之殘留，避免殘留之聚合物使 接觸窗插塞之接面電阻升高。 本發明提供一種接觸窗開口的製造方法，在半導體基 底之閘極堆疊層上形成共形之間隙壁材質層，接著覆蓋一 層絕緣層。然後在絕緣層上形成用以製作接觸窗開口之圖 案化的光阻層。之後以光阻層爲罩幕，使用高選擇比之蝕 3 ^紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐) ' f請先閲讀背面之注意事項再填寫本頁}The present invention relates to a method for manufacturing a dynamic random access memory (DRAM), and more particularly, to a method for forming a contact window opening in a memory of a dynamic random access memory, a memory cell. . As computer microprocessors become more powerful and programs and calculations performed by software become more and more large, the demand for memory capacity becomes higher and higher. One of the ways to increase memory capacity is to increase the degree of accumulation. When the DRAM process reaches below 0.18 microns, one of the manufacturing methods for increasing the accumulation degree is to form a contact window opening of a source / drain region in a memory cell while on the sidewall of the gate adjacent to the contact window opening. A silicon nitride gate spacer is formed. When making a contact window opening, first etch the silicon oxide layer as an insulating layer. It must use a high selectivity etchant to avoid too much silicon nitride loss when the silicon oxide layer is etched and affect the spacer. Formation. Next, the silicon nitride layer is etched with a low selectivity etchant to form a silicon nitride gate spacer. However, when the contact window opening is formed, polymer residues are liable to be present at the bottom of the opening, which causes the contact resistance of the contact window plug to increase due to the residual polymer when the contact window plug is formed. Therefore, the present invention provides a method for manufacturing a contact window opening, which can avoid the polymer remaining on the bottom of the contact window opening, and avoid the residual polymer from increasing the contact resistance of the contact window plug. The invention provides a method for manufacturing a contact window opening. A conformal spacer material layer is formed on a gate stack layer of a semiconductor substrate, and then an insulating layer is covered. A patterned photoresist layer is then formed on the insulating layer to make a contact window opening. Then use the photoresist layer as the cover and use the high selectivity etch. 3 ^ The paper size applies the Chinese national standard (CNS > A4 size (210X297 mm) 'f Please read the precautions on the back before filling this page}
-,1T " 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（·ν ) 刻劑，去除部分絕緣層，於閘極堆疊層之間形成接觸窗開 口，暴露出間隙壁材質層。接著去除光阻層，以及開口底 部可能形成之聚合物。然後使用低選擇比之蝕刻劑，進行 全面性鈾刻，去除部分該間隙壁材質層，暴露出接觸窗開 口底部之基底表面，且同時於接觸窗開口與閘極堆疊層相 接之側壁形成側壁間隙壁。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1F圖是繪示依照本發明一較佳實施例之 製程剖面示意圖。 圖式之標記說明： 100 :半導體基底 102 :週邊區域 104 :記憶胞區域 110、120、130 :鬧極堆疊層 114、124、134 :閘極頂蓋層 經濟部智慧財產局員工消費合作社印製 407341 4 8 7 1 1 w f. d ο c/0 Ο 8 (請先閱讀背面之注意事項再填寫本頁) 116 :側壁間隙壁 140 :間隙壁材質層 142 ' 142a :絕緣層 144 :光阻層 146、146a :接觸窗開口 148 :側壁間隙壁 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4871( wf.doc/0〇8 407341 ^ B7 五、發明説明（}) 較佳實施例 請參照第1A圖，提供一半導體基底100。在基底100, 上規劃出用以儲存資料之記憶胞區域104，以及用以輸入/ 輸出資料之週邊區域102。 接著在基底1〇〇之週邊區域102上形成用以製作電晶 體之閘極堆疊層110,以及在記憶胞區域104形成用以製 作電晶體之閘極堆疊層120與130。閘極堆疊層110、120 與130 —般包括由下而上堆疊之閘極氧化層（未顯示）、閘 極導電層112、122與132，以及閘極頂蓋層114、124與 134。其中，閘極導電層112、122與132 —般比如是由複 晶矽層及矽化鎢層所構成，而閘極頂蓋層Π4、124與134 一般比如是由氮化矽層所構成。在閘極導電層與閘極頂蓋 層之間，通常形成黏著層（未顯示）如氮氧化矽層，藉以增 進兩者之間的黏合。至於閘極堆疊層11〇、120與130之 形成方法皆爲熟習該技藝者所熟知之技術，因此不再贅 述。 仍參照第1A圖，在基底100上覆蓋一層共形之間隙 壁材質層140,比如是以化學氣相沉積法（CVD)沉積而成 之氮化矽層，所形成之厚度約500埃左右。在形成間隙壁 材質層140之前，可先在閘極110、120與130之側壁選 擇性地形成黏著層（未顯示），比如使用矽酸四乙酯 (TEOS)，以低壓化學氣相沉積法(LPCVD)，沉積厚度約120 埃之氧化矽層。 請參照第1B圖，接著僅去除於週邊區域1〇2中’在 5 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） C請先閱讀背而之注意事項存瑱寫本頁)-, 1T " Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (· ν) Engraving agent, remove part of insulation layer, form contact window openings between the gate electrode stack layers, and expose the gap wall material Floor. Then remove the photoresist layer and any polymer that may be formed at the bottom of the opening. Then use a low selectivity etchant to perform a comprehensive uranium engraving, remove part of the spacer material layer, expose the substrate surface at the bottom of the contact window opening, and simultaneously form a side wall at the side wall where the contact window opening and the gate stack layer are connected. Gap wall. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1 to FIG. 1F are schematic cross-sectional views illustrating a manufacturing process according to a preferred embodiment of the present invention. Explanation of drawing symbols: 100: semiconductor substrate 102: peripheral area 104: memory cell area 110, 120, 130: alarm stack layer 114, 124, 134: gate cap layer Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperative Printed 407341 4 8 7 1 1 w f. D ο c / 0 Ο 8 (Please read the precautions on the back before filling in this page) 116: Side wall spacer 140: Spacer material layer 142'142a: Insulation layer 144: Photoresist layer 146, 146a: Contact window openings 148: Side wall gap wall 4 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 4871 (wf.doc / 0〇8 407341 ^ B7 V. Description of the invention ()) Compared with For a preferred embodiment, please refer to FIG. 1A, a semiconductor substrate 100 is provided. On the substrate 100, a memory cell area 104 for storing data and a peripheral area 102 for inputting / outputting data are planned. Then on the substrate 100, A gate stack layer 110 for forming a transistor is formed on the peripheral region 102, and a gate stack layer 120 and 130 for forming a transistor are formed in the memory cell region 104. The gate stack layers 110, 120, and 130 are the same Includes gate oxide layer stacked from bottom to top (Not shown), the gate conductive layers 112, 122, and 132, and the gate cap layers 114, 124, and 134. Among them, the gate conductive layers 112, 122, and 132 are typically composed of a polycrystalline silicon layer and a tungsten silicide layer. The gate cap layers Π4, 124, and 134 are generally made of, for example, a silicon nitride layer. Between the gate conductive layer and the gate cap layer, an adhesive layer (not shown) such as a silicon oxynitride layer is usually formed. In order to improve the adhesion between the two, as for the method of forming the gate stack layers 110, 120, and 130 are techniques familiar to those skilled in the art, so I will not repeat them. Still referring to FIG. 1A, on the substrate 100 Covering a conformal spacer material layer 140, such as a silicon nitride layer deposited by chemical vapor deposition (CVD), has a thickness of about 500 angstroms. Before forming the spacer material layer 140, First, an adhesive layer (not shown) is selectively formed on the sidewalls of the gate electrodes 110, 120, and 130. For example, using tetraethyl silicate (TEOS) and low pressure chemical vapor deposition (LPCVD), a thickness of about 120 angstroms is deposited. Silicon oxide layer. Please refer to Figure 1B, and then remove only the periphery Regional 1〇2 in 'paper in five scales applicable Chinese National Standard (CNS) A4 size (2I0X297 mm) C Please read the Notes on the back and deposit Zhen wrote on this page)
,1T 經濟部智慧財產局員工消費合作社印製 487It\vf.doc/008 407341 A7 B7_ 五、發明説明（k ) 基底100上及在閘極堆疊層110上之間隙壁材質層140， 並且同時在週邊區域102中之閘極堆疊層110之側壁形成 側壁間隙壁116。其方法比如是只在記憶胞區域1〇4上形 成陣列區塊之光阻層，而不在週邊區域102上形成。接著 以光阻層爲罩幕進行蝕刻，在閘極堆疊層110之側壁上形 成側壁間隙壁116,同時去除基底100及閘極堆疊層110 上之間隙壁材質層140，而後再去除光阻層。 請參照第1C圖，在整個基底1〇0上覆蓋至少一層絕 緣層 I42 ’ 以作爲內層介電層（Interlayer dielectric layer)， 比如先以常壓化學氣相沉積法(APCVD)，沉積厚度約8000 埃之氧化矽層，接著以塗佈方式，在其上形成一層旋塗式 玻璃(SOG)。 請參照第1D圖，在絕緣層M2上形成用以製作接觸 窗開口之圖案化光阻層144。光阻層144中具有開口，用 以製作接觸窗開口，開口之寬度可略大於閘極堆疊層120 與130之間的寬度，藉以形成大的接觸窗開口。接著以光 阻層爲罩幕’先以局選擇比（high selectivity)之飽刻劑（其 對絕緣層M2之蝕刻速率相對地比對間隙壁材質層14〇之 蝕刻速率高），如CH2F2/C4F8，對絕緣層H2進行非等向 性乾蝕刻，僅去除閘極堆疊層120與130之間的部分絕緣 層M2,藉以形成開口 M6。由於在進行高選擇性蝕刻製 程時’在間隙壁材質14〇上會形成一層聚合物(p〇lymer)， 以保護間隙壁材質層14〇，藉以提高蝕刻選擇比。然而， 此聚合物對於後續進行間隙壁材質層140蝕刻時容易造成 ί I ^^^1 mi l·—— ml n · n I (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 4871 twf.doc 407341 五、發明説明（匕） 阻礙，而在開口 146的底部造成殘留。 請參照第1E圖，接著比如以氧電槳(oxygen plasma)剝 除方式，剝除光阻層M4,同時去除在接觸窗開口 146內（即 在間隙壁材質層140上）的聚合物。由於光阻層144大多 使用高分子聚合物材質，與間隙壁材質層140上的聚合物 材質近似，因此可在同一步驟中，完全去除殘留的聚合物。 請參照第1F圖，由於本發明在去除光阻層144之步驟 已完全去除開口 146內殘留之聚合物，因此稍後在去除間 隙壁材質層140時，可以順利進行且不會在開口 146底部 造成聚合物殘留。接著，以低選擇比（low selectivity)之蝕 刻劑，如CHF3/C4F8，進行全面性蝕刻（blanket etch)，同 時飩刻表面暴露之絕緣層142及間隙壁材質層140，形成 絕緣層142a，並且在開口 146與閘極堆疊層120及130相 接之位置處，形成間隙壁148，同時去除在開口 146底部 之間隙壁材質層140，直到暴露出底部的基底表面，如源 極/汲極區，而成開口 146a。最後，可在接觸窗開口 146a 內塡入導電性材質， 由上述本發明較佳實施例可知，本發明在形成接觸窗 開口時’可避免聚合物在開口底部殘留，藉以避免形成接 觸窗插塞時，增加接觸電阻。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) ,?τ 經濟部智慧財是局員工消費合作社印製, 1T Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 487It \ vf.doc / 008 407341 A7 B7_ V. Description of the Invention (k) The spacer material layer 140 on the substrate 100 and on the gate stack layer 110, and at the same time The sidewall of the gate stack layer 110 in the peripheral region 102 forms a sidewall spacer 116. The method is, for example, to form a photoresist layer of an array block only on the memory cell region 104, but not on the peripheral region 102. Then, the photoresist layer is used as a mask for etching, and a sidewall spacer 116 is formed on the sidewall of the gate stack layer 110. At the same time, the substrate 100 and the spacer material layer 140 on the gate stack layer 110 are removed, and then the photoresist layer is removed. . Please refer to FIG. 1C, and cover at least one insulating layer I42 'on the entire substrate 100 as an interlayer dielectric layer. For example, firstly, atmospheric pressure chemical vapor deposition (APCVD) is used to deposit a thickness of about A silicon oxide layer of 8000 angstroms is then applied to form a spin-on-glass (SOG) on top of it. Referring to FIG. 1D, a patterned photoresist layer 144 for forming a contact window opening is formed on the insulating layer M2. The photoresist layer 144 has an opening for making a contact window opening, and the width of the opening may be slightly larger than the width between the gate stack layers 120 and 130 to form a large contact window opening. Then use the photoresist layer as a mask. 'First use a high selectivity saturation agent (the etching rate of the insulating layer M2 is relatively higher than that of the spacer material layer 14), such as CH2F2 / C4F8, anisotropic dry etching is performed on the insulating layer H2, and only a part of the insulating layer M2 between the gate stack layers 120 and 130 is removed to form the opening M6. During the highly selective etching process, a layer of polymer is formed on the spacer material 14 to protect the spacer material layer 14 so as to improve the etching selection ratio. However, this polymer is likely to cause ί I ^^^ 1 mi l · —— ml n · n I for subsequent etching of the spacer material layer 140 (please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Property Bureau, 4871 twf.doc 407341 V. Description of the invention (dagger) Obstructed, leaving a residue at the bottom of the opening 146. Referring to FIG. 1E, the photoresist layer M4 is stripped, for example, by an oxygen plasma stripping method, and the polymer in the contact window opening 146 (that is, on the barrier material layer 140) is removed at the same time. Since the photoresist layer 144 is mostly made of a high-molecular polymer material, which is similar to the polymer material on the partition wall material layer 140, the remaining polymer can be completely removed in the same step. Please refer to FIG. 1F. Since the polymer remaining in the opening 146 is completely removed in the step of removing the photoresist layer 144 according to the present invention, when the spacer material layer 140 is removed later, it can be performed smoothly and will not be at the bottom of the opening 146. Causes polymer residue. Next, perform a blanket etch with a low selectivity etchant such as CHF3 / C4F8, and simultaneously etch the exposed insulating layer 142 and the spacer material layer 140 to form an insulating layer 142a, and A gap wall 148 is formed at the position where the opening 146 meets the gate stack layers 120 and 130, and the gap wall material layer 140 at the bottom of the opening 146 is removed at the same time until the bottom substrate surface is exposed, such as the source / drain region ， 而起 孔 146a。 Opening 146a. Finally, a conductive material can be inserted into the contact window opening 146a. According to the above-mentioned preferred embodiments of the present invention, when the contact window opening is formed in the present invention, the polymer can be prevented from remaining at the bottom of the opening, thereby avoiding the formation of a contact window plug. , Increase the contact resistance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page).?