407321 A7 _ B7 五、發明說明（f ) 發明領域： 本發明係關於一種積體電路中銅金屬之阻障層的製作方 法，特別是關於一種利用物理氣相沉積法及化學氣相沉積法 所形成的複層阻障層結構。 發明背景： 一般而言，半導體元件隨著積體電路密度的增加及體積 的縮小’可明顯改善電性動作的速度，並減少電子產品的生 產成本，是以元件尺寸極小化與高積集度，一直是積體電路 製作上極爲重要的發展方向之一。然而，元件尺寸極小化使 得晶片的表面無法提供足夠面積來製作所需的導線結構，多 層導線結構的需求也就越來越重要，此外，發展優於傳統鋁 金屬的新金屬材料，亦是當今迫切需解決的課題。 傳統積體電路製程中，主要利用的鋁（A1)金屬製程， 在進入深次微米領域時，由於鋁金屬電阻値尙不夠低、階梯 覆蓋率隨接觸窗尺寸縮小而變差、應力導致空洞形成及抗電 子遷移（electromigmtion)不足等問題，將影響到產品的可 靠度’故如今已是面臨到發展新的金屬材料或新的沉積技術 的時代。新的金屬材料中具有先天上優勢的金屬銅（Cu) 也開始廣泛的被硏究，其優點如：（1)低電阻特性，可提供 較快的傳輸速度及減少電阻-電容延遲時間（RC delay time); (2)良好的抗電子遷移性，避免造成斷路；⑶良好的抗應力 致空洞形成性質等。 然而’無論在傳統的鋁金屬製程或新發展之銅金屬製 程，同時面臨了一個問題，即爲金屬與砂接面間產生的尖峰 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) <請先閲讀背面之注意事項再填寫本頁) -I 裝·11-訂·！-------線 經濟部智慧財產局員工消費合作社印製 A7 407321 B7_____ 五、發明說明（>) (spike)現象，所述尖峰現象之成因爲當金屬（鋁或銅） 沉積在矽表面，而溫度高於兩者之互溶溫度時，矽對金屬有 一固態溶解度，矽將藉擴散效應而進入金屬層中，金屬也會 回塡因擴散所遺留下來之空隙，使得矽與金屬之接面形成尖 峰，如果這些尖峰的長度太長，則可能會造成迴路短路 (short)，解決此問題的一種方法即在金屬與政之間加入一 稱爲阻障金屬（barrier metal)的材料，而現行在積體電路 之銅金屬溝塡製程中，通常在沉積銅金屬成核層50之前，選 擇利用物理氣相沉積法（Physical Vapor Deposition; PVD) 或化學氣相沉積法（Chemical Vapor Deposition; CVD )沉積 單一阻障層40於矽基板10上，如圖一所示，然而，PVD-阻 障層在接觸尺寸小及高深寬比的接觸洞中無法得到理想的階 梯覆蓋率，而CVD -阻障層雖然階梯覆蓋率佳，但是卻有附 著力不夠的問題，是以本發明揭露一種在積體電路中銅金屬 之阻障層的製作方法，提供介電孔（void) —同時兼具結構 穩固、良好之階梯覆盖率及較低且均勻分佈的電阻値的阻障 層。 發明之槪述： 本發明之主要目的是提供一種積體電路中銅金屬之阻障 層的製作方法，形成一兼具結彳Μ固、良好之階梯覆蓋率及 較低且均勻分佈的電阻値的阻障層。 本發明之次要目的是提供一種利用物理氣相沉積法及化 學氣相沉積法所形成的堆疊式複層阻障層結構。 本發明係使用下列步驟來達到上述之各項目的：首先， -------------3 本紐尺度刺巾國國家標準（CNS)A4規格（21〇 χ 297公£3---- (請先閱讀背面之注意事項再填寫本頁) I-----裝-----1!-訂 --------- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 20-介電層 40-阻障層 40b-CVD阻障層 60-銅金屬層 407321 A? B7 五、發明說明（)） 提供一表面已形成有一介電層的基板；接著，於所述基板中 開啓數個溝槽（trench);接下來爲本發明之重要特徵，係 依序沉積一 PVD-阻障層及一 阻障層以形成一堆疊式 複層阻障層結構；再接著，依序形成一銅金屬成核層 (nucleation layer)及銅金屬層於所述阻障層上；最後，進 行化學機械硏磨（CMP)移除所述介電層上之銅金屬層、 銅金屬成核層及PVD/CVD阻障層，完成了具有複層阻障層 結構之銅金屬溝塡製作。 圖式簡要說明： 圖一爲習知技藝於銅金屬成核層與矽基板接面間形成單 一阻障層之剖面示意圖。 圖二爲本發明實施例中於基板上形成溝槽之剖面示意 圖。 圖三爲本發明實施例中依序形成PVD/CVD複層阻障層 結構之窗厕示意圖。 圖四爲本發明實施例中於阻障層上依序形成一銅金屬成 核層及銅金屬層之剖面示意圖。 圖五爲本發明實施例中經化學機械硏磨之平坦化處理後 之咅[J®示意圖 圖號說明： 10-基板 30-麵 40a-PVD阻障層 50-銅金屬成核層 ____ 4 ---Μ--- ------ - l·------訂 -------線 - (請t閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） A7 407321 --------B7____ 五、發明說明（f) 發明詳細說明： 本發明係有關於積體電路中銅金屬之阻障層的製作方 法，其主要特徵乃是形成一堆疊式複層阻障層結構，其詳細 的製程實施步驟，則如以下圖二至圖五所示： 首先，請參閱圖二，提供一半導體基板ίο，所述基板ίο 上已形成有一介電層20，並利用微影及非均向之乾式餓刻技 術於所述基板10中開啓一個或數個溝槽（trench) 30，其中 所述介電層20係爲化學氣相沉積（CVD)或旋塗（spin-coating)形成之氧化層，或爲其他低介電係數（low k )材 質。 接下來爲本發明之重要特徵，請參閱圖三，依序利用物 理氣相沉積法（PVD)及化學氣相沉積法’於所述基板10上 及所述溝槽30中沉積一 PVD-阻障層40a及一 CVD-阻障層40b 之堆疊結構，其中所述PVD-阻障層40a係利用離子化金屬 電漿（Ionized Metal Plasma; IMP :係爲PVD的一種）源鍍形 成之鉅金屬（Ta)或氮化鉬（TaN)結構，其於所述介電層 20上方之厚度係介於100A至400A之間，而CVD-阻障層40b 則爲氮化鉅（TaN)、氮化鈦（TiN)、氮化鎢（WNx)、 氮矽化鉬（TaSiN)、氮矽化鈦（TiSiN)、氮矽化鎢（WSiN) 或其他具上述金屬之四元化合物（ternary compound)結構， 其於所述介電層20上方之厚度係介於50A至200人之間。 上述之製程步驟係利用一完整的PVD/CVD整合系統進 行，其優點之一在於：習知技藝中僅形成單一之阻障層於矽 基板上，但無論是爲PVD-阻障層或CVD-阻障層皆有其自身 _____5 _ 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公爱)_ ~ ---；----：-------t--------訂---------線 I (請也閱讀背面之注意ί項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 407321 A7 ____B7____ 五、發明說明（f ) 之優缺點，就PVD-阻障層而言，雖然物理氣相沉積法沉積 之結構可提供較佳之附著力，但當進入深次微米的領域中， 面對接觸尺寸小及高深寬比的接觸洞時，利用PVD-阻障層 無法提供理想的階梯覆蓋率，使得阻障層側壁太薄，亦可能 形成接觸洞孔肩部沉積（shoulder or overhang)使得洞口完 全被封住，而於底部留下孔隙且無法達到所需的沉積厚度； 反觀CVD-阻障層，雖然其階梯覆蓋率佳，但是卻有與矽材 質間附著力不夠的問題，可能使得阻障層結構不夠穩固，而 造成剝落或斷裂影響到元件的可靠度。故本發明擷取物理氣 相沉積法及化學氣相沉積法兩者之優點，先沉積一附著力佳 的PVD-阻障層，提供穩固的阻障層結構，再沉積一階梯覆 蓋率佳的CVD-阻障層，提供足夠之底部覆蓋率，可避免銅 矽界面的尖峰（spike)現象。其優點之二在於：將離子化 金屬電槳（IMP)與CVD系統同時應用，除了不需使用個別 的PVD及CVD兩套設備，而且製程未因中斷而暴露於大氣 之中，可避免界面氧化、吸濕及微塵等問題，提高產品的良 率與元件的電性及可靠度。 再接著，請參閱圖四’先利用CVD法或IMP法形成一銅 金屬成核層50於所述CVD-阻障層40b上，再利用電化學沉積 (Electro-Chemical Deposition; ECD) —銅金屬層60塡滿所 述溝槽30，其中所述銅金屬成核層5〇於所述介電層20上方之 厚度係介於1000A至2500人之間。 最後，請參閱圖五，進行化學機械硏磨（CMP)移除 所述介電層20上之所述銅金屬層6〇、所述銅金屬成核層50及 ___6____ 本紙張尺度適用中國國家標準（CNS)A^規格（210 X 297"¥釐） ----------------裝 -------.訂i:-------線' (請先閱讀背面之注意事項再填寫本頁) 407321407321 A7 _ B7 V. Description of the Invention (f) Field of the Invention: The present invention relates to a method for manufacturing a barrier layer of copper metal in an integrated circuit, and more particularly to a method using physical vapor deposition and chemical vapor deposition. The formed multi-layer barrier layer structure. Background of the Invention: Generally speaking, with the increase of the integrated circuit density and volume reduction of semiconductor devices, the speed of electrical operation can be significantly improved, and the production cost of electronic products can be reduced. Has always been one of the most important development directions in the fabrication of integrated circuits. However, the miniaturization of components has made the surface of the wafer unable to provide sufficient area to make the required wire structure, and the demand for multilayer wire structures has become more and more important. In addition, the development of new metal materials that are superior to traditional aluminum metals is also today. Urgent issues to be addressed. In the traditional integrated circuit manufacturing process, the aluminum (A1) metal process is mainly used. When entering the sub-micron field, the aluminum metal resistance is not low enough, the step coverage deteriorates with the reduction of the contact window size, and voids are formed due to stress. And the lack of resistance to electron migration (electromigmtion) and other issues will affect the reliability of the product 'so it is now facing the era of the development of new metal materials or new deposition technology. Among the new metal materials, copper (Cu), which has inherent advantages, has also been widely studied. Its advantages are as follows: (1) Low resistance characteristics, which can provide faster transmission speed and reduce resistance-capacitance delay time (RC (delay time); (2) Good resistance to electron migration to avoid breaking; ⑶ Good resistance to stress-induced void formation. However, 'no matter in the traditional aluminum metal process or the newly developed copper metal process, it also faces a problem, that is, the peaks generated between the metal and the sand interface. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Mm) < Please read the notes on the back before filling out this page) -I pack · 11-order ·! ------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 407321 B7_____ 5. Description of the invention (spike) phenomenon, the spike phenomenon is caused when the metal (aluminum or copper) is deposited on When the temperature of the silicon surface is higher than the mutual solubility temperature of the two, silicon has a solid solubility for the metal. The silicon will enter the metal layer by the diffusion effect, and the metal will return to the void left by the diffusion, making the silicon and the metal Spikes are formed on the junction. If the length of these spikes is too long, it may cause short circuits. One way to solve this problem is to add a material called barrier metal between the metal and the government, and In the current copper metal gully manufacturing process of integrated circuits, usually before the copper metal nucleation layer 50 is deposited, a physical vapor deposition method (Physical Vapor Deposition; PVD) or a chemical vapor deposition method (Chemical Vapor Deposition; CVD) is selected. ) A single barrier layer 40 is deposited on the silicon substrate 10, as shown in Figure 1. However, the PVD-barrier layer cannot obtain an ideal step in a contact hole with a small contact size and a high aspect ratio. Coverage, and although the CVD barrier layer has good step coverage, it has a problem of insufficient adhesion. The present invention discloses a method for manufacturing a barrier layer of copper metal in a integrated circuit, and provides a dielectric hole ( void) —A barrier layer with both structural stability, good step coverage, and low and uniformly distributed resistance chirp. Description of the invention: The main object of the present invention is to provide a method for manufacturing a barrier layer of copper metal in an integrated circuit, so as to form a combination of solid state, good step coverage and low and uniformly distributed resistance. Barrier layer. A secondary object of the present invention is to provide a stacked multi-layer barrier layer structure formed by a physical vapor deposition method and a chemical vapor deposition method. The present invention uses the following steps to achieve the above items: First, ------------- 3 National Standard (CNS) A4 specification (21 × χ297). 3 ---- (Please read the precautions on the back before filling out this page) I ----- Installation ----- 1! -Order --------- Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Consumer Cooperative printed 20-dielectric layer 40-barrier layer 40b-CVD barrier layer 60-copper metal layer 407321 A? B7 5. Description of the invention ()) A surface has been formed A substrate with a dielectric layer; then, several trenches are opened in the substrate; the next important feature of the present invention is to sequentially deposit a PVD-barrier layer and a barrier layer to form a A stacked multi-layer barrier layer structure; then, a copper metal nucleation layer and a copper metal layer are sequentially formed on the barrier layer; finally, a chemical mechanical honing (CMP) is performed to remove the The copper metal layer, the copper metal nucleation layer and the PVD / CVD barrier layer on the dielectric layer were completed, and the copper metal trench with the multilayer barrier layer structure was completed. Brief description of the drawings: Fig. 1 is a schematic cross-sectional view of a conventional technique for forming a single barrier layer between a copper metal nucleation layer and a silicon substrate interface. FIG. 2 is a schematic cross-sectional view of a trench formed on a substrate according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a window toilet in which a PVD / CVD multi-layer barrier layer structure is sequentially formed in an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of sequentially forming a copper metal nucleation layer and a copper metal layer on the barrier layer in the embodiment of the present invention. FIG. 5 is a schematic view of a chemical-mechanical honing planarization process in the embodiment of the present invention [J® schematic drawing number description: 10-substrate 30-face 40a-PVD barrier layer 50-copper metal nucleation layer __ 4 --- Μ --- -------l · ------ Order ------- line- (Please read the notes on the back and fill in this page) This paper size applies to China National Standard (CNS) A4 specification (21〇X 297 public love) A7 407321 -------- B7____ V. Description of the invention (f) Detailed description of the invention: This invention relates to the resistance of copper metal in integrated circuits The main feature of the barrier layer manufacturing method is to form a stacked multi-layer barrier layer structure. The detailed process implementation steps are shown in Figures 2 to 5 below: First, please refer to Figure 2 to provide a semiconductor A substrate ο has a dielectric layer 20 formed thereon, and one or more trenches 30 are opened in the substrate 10 using lithography and non-uniform dry etching technology, wherein the The dielectric layer 20 is an oxide layer formed by chemical vapor deposition (CVD) or spin-coating, or other materials with a low dielectric constant (low k). Next is an important feature of the present invention. Referring to FIG. 3, a PVD-resistance is sequentially deposited on the substrate 10 and the trench 30 using a physical vapor deposition (PVD) method and a chemical vapor deposition method. A stacked structure of a barrier layer 40a and a CVD-barrier layer 40b, wherein the PVD-barrier layer 40a is a giant metal formed by using an ionized metal plasma (Ionized Metal Plasma; IMP: a type of PVD) source plating The thickness of the (Ta) or molybdenum nitride (TaN) structure above the dielectric layer 20 is between 100A and 400A, and the CVD-barrier layer 40b is nitrided (TaN), nitrided. Titanium (TiN), tungsten nitride (WNx), molybdenum silicide (TaSiN), titanium silicide (TiSiN), tungsten silicide (WSiN), or other ternary compound structures with the above metals The thickness above the dielectric layer 20 is between 50A and 200 people. The above process steps are performed using a complete PVD / CVD integrated system. One of its advantages is that in the conventional art, only a single barrier layer is formed on a silicon substrate, but whether it is a PVD-barrier layer or a CVD- The barrier layer has its own _____5 _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) _ ~ ---; ----: --------- ------ Order --------- Line I (Please also read the note on the back and fill in this page again) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economy Printed 407321 A7 ____B7____ V. Advantages and Disadvantages of the Invention (f) As far as PVD-barrier layer is concerned, although the structure deposited by physical vapor deposition method can provide better adhesion, when entering the sub-micron field When facing contact holes with small contact size and high aspect ratio, the PVD-barrier layer cannot provide ideal step coverage, making the sidewall of the barrier layer too thin, and it may also form a shoulder or overhang of the contact hole. ) Makes the hole completely sealed, leaving pores at the bottom and unable to reach the required deposition thickness In contrast CVD- barrier layer, although good step coverage, but there is not enough interstitial silicon material adhesion problems, the barrier layer may be such that the structure is not stable, causing spalling or fracture affect the reliability of the element. Therefore, the present invention captures the advantages of both physical vapor deposition and chemical vapor deposition. First, a PVD-barrier layer with good adhesion is deposited to provide a stable barrier layer structure, and then a layer with good step coverage is deposited. The CVD-barrier layer provides sufficient bottom coverage to avoid spikes at the copper-silicon interface. The second advantage is that the ionized metal electric paddle (IMP) and CVD systems are used simultaneously. In addition to the separate PVD and CVD equipment, the process is not exposed to the atmosphere due to interruption, which can avoid interface oxidation. , Moisture absorption and dust, etc., to improve the product yield and the electrical and reliability of components. Then, please refer to FIG. 4 'firstly, a copper metal nucleation layer 50 is formed on the CVD-barrier layer 40b by a CVD method or an IMP method, and then an electro-chemical deposition (ECD) -copper metal is used. A layer 60 fills the trenches 30, wherein the thickness of the copper metal nucleation layer 50 above the dielectric layer 20 is between 1000A and 2500 people. Finally, referring to FIG. 5, a chemical mechanical honing (CMP) is performed to remove the copper metal layer 60, the copper metal nucleation layer 50 and _6____ on the dielectric layer 20. This paper is applicable to China Standard (CNS) A ^ Specification (210 X 297 " ¥ centi) ---------------- install ---------. Order i: ------- Line '(Please read the notes on the back before filling this page) 407321
況。謹請貴審查委員明鑑，並祈惠准，是所至禱 B7 五、發明說明（k) 所述卩胃(：\^阻障層4(^,401?，完成具有複層阻障金屬層結 構之銅隱塡製作。 利用本發明製作積體電路中銅之阻障金屬層具有下列W 優點： 1. 本發明係在積體電路中銅金屬溝塡製作時提供一堆 疊式複層阻障層結構。 2. 本發明係提供一種兼具結構穩固及階梯覆蓋率佳之 阻障層的製作方法。 3. 本發明係提供一種具較低且均勻分佈的電阻値之阻 障層的製作方法。 4. 本發明係提供一種可有效避免銅矽界面尖峰（spike) 現象之阻障層的製作方法。 以上所述係利用較佳實施例詳細說明本發明，而非P 本發明的範圍，因此熟知此技藝的人士應能明瞭， 些微的改變與調整，仍將不失本發明之要義所在， 本發明之精神和範圍，故都應視爲本發明的進一氺％晚離 «ΙΊI — I------裝 -------—ν'Ί-------線 (請知閱讀背面之注意事項再填寫本頁> _ 經濟部智慧財產局員工消費合作社印製condition. I would like to ask your reviewing committee to make a clear reference and pray for your approval. B7 V. Stomach (: \ ^ Barrier layer 4 (^, 401?) As described in the invention description (k), complete with a multi-layer barrier metal layer Fabrication of copper recesses in structures. The use of the present invention to produce copper barrier metal layers in integrated circuits has the following W advantages: 1. The present invention provides a stacked multi-layer barrier in the production of copper metal trenches in integrated circuits. Layer structure. 2. The present invention provides a method for manufacturing a barrier layer having both a stable structure and an excellent step coverage. 3. The present invention provides a method for manufacturing a barrier layer with a low and uniform distribution of electrical resistance. 4. The present invention provides a method for manufacturing a barrier layer which can effectively avoid the spike phenomenon of the copper-silicon interface. The above description uses the preferred embodiments to describe the present invention in detail, but not the scope of the present invention, so it is well known Those skilled in the art should be able to understand that minor changes and adjustments will still not lose the essence of the present invention, and the spirit and scope of the present invention should be regarded as a further percent departure from the present invention «ΙΊI — I-- ---- install --------- ν '—------- line (please Read the Notes on the back to fill out Page > _ Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed