TW405204B - Method to control the etching process - Google Patents

Abstract

The present invention provides a method to control the etching process for striping the dielectric layer on a semiconductor substrate, which comprises the steps as follows: (1) proceed the chemical mechanical polishing on a semiconductor wafer surface to strip a predetermined thickness of the first dielectric layer; (2) measure the residual thickness of said dielectric layer; (3) provide a etching checklist for a plural set of the residual thickness containing all ranges for the dielectric layer and the etching back process or parameters related to the thickness range; and (4) proceed flatly the etching back process according to said checklist to strip the altitude from the first to the second dielectric layer.

Description

—405204 V. Description of the invention (1) " The present invention provides an etching process control method, in particular, an etching process control method for removing a dielectric layer on the surface of a semiconductor wafer. Chemical-mechanical polishing (CMP for short) is a very common technique in the semiconductor surname engraving process. It is used to remove unnecessary substances on the surface of semiconductor wafers, and to make the semiconductor wafers local (local) or global (global). ) Surface planarization »The polishing rate of CMP is very difficult to control. The polishing rate often changes with the use of a polishing medium. Therefore, the results of each polishing will be slightly different, resulting in excessive semiconductor wafer names. Undercutting or etching is insufficient. In the shallow trench isolation process, in order to prevent micro-scratch caused by excessive etching of semiconductor wafers, only a part of the material is removed by CMP, and the remaining material is more stable at the etching rate. Method to remove. Please refer to Figure 1 to Figure 3. Figures 1-3 show the implementation steps of the shallow trench isolation process in the semiconductor process. The semiconductor wafer 10 shown in FIG. 1 has completed the previous process of CMP. The semiconductor wafer 10 is provided with shallow trenches 18 and has been filled with a dielectric material. The semiconductor wafer 10 includes a silicon substrate 12 and a silicon oxide substrate ( A pad layer 14 made of SiOx) is formed on the silicon substrate 12, and a second dielectric layer 16 made of silicon silicon nitride (SiNx) is deposited on the pad layer 14. The semiconductor wafer 10 further includes a plurality of shallow trenches 18 for isolating adjacent components on the semiconductor wafer 10, and a first dielectric layer 20 composed of an oxite material is covered. To fill shallow trenches

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Five 'invention description (2) 18. Subsequently, the first dielectric layer 20 on the surface of the semiconductor chip 10 is subjected to a CMP planarization process to remove one of the predetermined thicknesses of the first dielectric layer 20, and the surface of the conductor wafer 10 is approximately formed into a flat plane, as shown in the figure. Shown in two. After Z, the residual thickness of the first dielectric layer 20 is measured. 'If the residual thickness is in a pre-defined range β, dry etching such as a relatively reactive ion ionization & magnetic field selective reactive ion etching method is used. During the manufacturing process, the first dielectric layer 20 remaining on the semiconductor substrate 10 etched back is etched back horizontally to remove the surface height of the first dielectric layer 20 to the second dielectric layer 16. Finally, the semiconductor wafer 10 of No. 3 Institute forms a flat surface, which includes only the second dielectric layer 16 and several shallow trenches 18 containing the first dielectric layer 20. Please indicate the thickness of 圊, because the range can not be called after the body is turned into wafers, please refer to Figure 4 for the work. . In order to accurately predict the range, set this number after grinding. When the measurement is performed, the production engineer performs special measures to make the measurement. Figure 4 shows the control of etch back by the known surname. Taipa is very small. The residual thickness of a dielectric layer 20 does not match the operation on the production line to address the residual thickness. Knowing that the engraving process is suspended, another process is the process control method 22, the process of the first dielectric layer, the polishing rate of the CMP residue is unstable, and the residual thickness can easily exceed the pre-expected range. When etching back, the personnel must make the process. Pause, semiconducting process control method that does not meet the expected range 2 2 Very rigid aspects will also increase process engineers

405204 V. Description of the invention (3) _ ~ -------- I. Summary: 面 ίΪ: The main purpose is to provide an etching process control method that removes the semiconductor wafer surface, so that the etching process can be smoothly shown in the figure. Brief description Figures 1 to 3 are schematic diagrams of the implementation steps of the conventional shallow trench isolation process. FIG. 4 is a schematic flowchart of a conventional etching process control method. 5 to 7 are schematic diagrams showing implementation steps of the method for controlling an etching process according to the present invention. FIG. 8 is a schematic flow chart of the etching process control method of the present invention. FIG. 9 is a schematic cross-sectional view of a multi-metal interconnect structure of an integrated circuit. Symbols shown in the figure 12, 5 2 Silicon substrate 14 Underlayer 16 Second dielectric layer 18 Shallow trench 20 First dielectric layer 30, 50 Semiconductor wafer 40 Dry etching system 42 Etching table 48 Dry etching machine 58 Please refer to FIG. 5 to FIG. 7 for a metal dielectric layer. FIG. 5 to FIG. 7 are schematic diagrams of a shallow trench isolation process using the etching process control method of the present invention. In the shallow trench isolation process using the method of the present invention, a semiconductor wafer 30 is first prepared. As shown in FIG. 5, the semiconductor wafer 30 includes a silicon substrate 12 and a silicon oxide (Si χ) structure.

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A completed pad layer 14 is formed on the silicon substrate 12, a second dielectric layer 16 composed of a silicon nitride (SiNx) is deposited on the pad layer 14, and the silicon substrate 12, The pad layer 14 and the second dielectric layer n include a plurality of shallow trenches 18 for isolating adjacent components on the semiconductor wafer 30. The semiconductor wafer 30 further includes a first dielectric layer 20 made of silicon oxide (SiOx) overlying the second dielectric layer 16 to fill the shallow trenches 18. The underlayer 14 can be used to prevent damage to the semiconductor wafer 30 caused by excessive surface stress of the second dielectric layer 16 due to heating. The first dielectric layer 20 is then subjected to CMP to remove a pre-thickness of one of the first dielectric layers, and the surface of the semiconductor wafer 30 is approximately formed into a flat plane, and then the remaining thickness of the first dielectric layer is measured. As shown in Figure 6, it is the residual thickness. Next, an etching comparison table is provided, which includes the residual thickness range of the first dielectric layer 20 of the complex array, and a retelling process or parameter corresponding to each thickness range, and is based on the residual thickness and engraving of the first dielectric layer. The etch back process corresponding to the residual thickness in the table is used to perform an etch back process to horizontally remove the surface height of the first dielectric layer 20 to the second dielectric layer 16. The etch back process is usually a dry etching process. The electrical reaction removes the surface material of the conductor wafer 30. As shown in FIG. 6, after the etch-back, the surface of the conductor wafer 30 includes a second dielectric layer and a plurality of shallow trenches 18 containing a dielectric layer 20, and the semiconductor wafer 30 forms a flat surface. The process steps of the wafer 30 are performed by a process control system.

405204 Five 'Invention (5) Control' and the etch control table is stored in the process control system. The process and process control system determines the corresponding etch-back procedure based on the residual thickness of the first dielectric layer and the etch control table. To perform an etch-back process. Please refer to Figure 8. 28 is a schematic flow chart of the etching process control method 24 of the present invention. When the semiconductor wafer 30 has completed the previous process before CMP, and after CMP, the remaining thickness of the first dielectric layer 20 is then measured, and the process flow control system then uses the remaining thickness of the first dielectric layer 20 and the etching comparison table. To determine the corresponding etch-back procedure to automatically perform the etch-back process "," and then perform subsequent processes. Compared to the conventional etching process control method 22, only one etch-back process can be performed, and the residual of the first dielectric layer The expected range of thickness is set to be small, so that the process flow is often suspended due to non-compliance with the residual thickness. In the etching process control method 24 of the present invention, the process flow control system can determine different etch-back procedures according to different residual thicknesses. The expected range is expanded in size, and the semiconductor wafer that meets the expected range can be etched back in seven steps, which makes the process flow of the semiconductor wafer very smooth and reduces the number of special treatments by the process engineer. First residual dielectric layer The etch-back process performed by 20 is a dry etching process performed in the dry etching system, and the #etch comparison table can also be stored. = In the engraving system. The dry engraving system will automatically perform an etch-back process in accordance with ^ = of the first dielectric layer 2 {) and the corresponding thickness in the etching comparison table to remove it horizontally. The surface height of the dielectric layer 16 is removed from the first dielectric layer 20 to the second by ten.

405204 V. Description of the invention (6) Please refer to Figure IX. FIG. 9 is a schematic cross-sectional view of a multi-metal interconnect structure of an integrated circuit. The method for controlling an etching process of the present invention can also be applied to a multi-metal interconnect process of an integrated circuit. The semiconductor wafer 50 includes a silicon substrate 52. A prepared Mos transistor 54 is formed on the silicon substrate 52. A first metal interconnect layer 56 is deposited on the MOS transistor 54 and is connected by two. Each transistor and component 'and an inner metal dielectric layer 58 are deposited on a metal interconnect layer 56. The "inner metal dielectric layer 58" is used to isolate the first metal interconnect layer 56 from subsequent deposition in the inner A second metal interconnect layer on the metal dielectric layer 58 to avoid short contact between the two metal interconnect layers. When a second metal interconnect layer is deposited on the inner metal dielectric layer 58 'needs to be The planarization process of the inner metal dielectric layer 58 is performed because it is easier to fabricate a second metal interconnect layer on the flat inner metal dielectric layer 58 and the transferred wire pattern is more accurate. When the planarization process of the inner metal dielectric layer 58 is performed, in order to avoid micro traces on the surface of the semiconductor wafer on the CMP, the method of the present invention can be used to provide an etching comparison table, which contains the residues of the metal dielectric layer 58 in the array Thickness range, and etch-back procedures or parameters corresponding to each thickness range. The planarization process of the metal dielectric layer using the method of the present invention includes the following steps: (1) CMP the inner metal dielectric layer 58 to remove a predetermined thickness of the inner metal dielectric layer 58; (2) within the measurement The residual thickness of the metal dielectric layer 58;

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V. Description of the invention (7) (3) Provide an etching comparison table, including the residual thickness 4SHI ,, n ', the residual thickness range u and the length or parameter including the metal dielectric layer 58 in the array; and each thickness range Corresponding etch-back procedure (4) An etch-back process is performed according to the etch-back procedure corresponding to the residual thickness of the inner metal dielectric thunder jgu 蛊 & / t # ^ Β 58 and the residual thickness in the etching comparison table to remove the inner metal The dielectric layer 58 is planarized. Compared with Xi, the control method 24 is an etch control. Corresponding etchback control is set to a large dynamic etchback. Wafer process conditions are rare. Knowing the etching process control uses the process flow table to automate the method according to the dielectric engraving program, the first range, and in the pre-etching process, the production is smoother. And it happened, so the reduction method 22, the etching process control system or the dry etching system of the present invention provides the residual thickness of the layer and its residual thickness for the etch-back process. After using the dielectric layer of the present invention, the residual thickness of CMP semiconductor wafers within the range can be suspended from time to time, so the semiconductor and the residual thickness does not meet the expectations. It is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to the patent of the present invention ^

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Claims (1)

Δ (ί ^ 9ΜΛ_ VI. Patent application scope The etching process of the first dielectric layer is controlled on top of a second dielectric layer, which is subjected to a predetermined thickness of mechanical mechanical polishing; > Multiple arrays of the first The etchback process corresponding to the residual range of the dielectric layer and the etching comparison table and the procedure to perform a touch-etching process layer to the surface of the second dielectric layer 1. A method for removing the surface of a semiconductor wafer The first dielectric layer covering method includes the following steps: providing an etching comparison table for the first dielectric process on the surface of the semiconductor wafer to remove the first dielectric layer and measuring the residual thickness of the first dielectric layer, It includes a range of remaining thicknesses and thickness sequences or parameters; and an etchback corresponding to the residual thickness of the first dielectric layer to remove the first dielectric level horizontally. Item method, wherein the etching comparison table is stored in a process flow control system. The process flow control system is used to determine the process steps of the semiconductor wafer. The process flow control system According to the residual thickness of the first dielectric layer and the etching comparison table, a corresponding etch-back process is performed to perform the etch-back process. 3. The method according to item 1 of the scope of patent application, wherein the second dielectric layer is _ Silicon nitride (SiNχ), whose surface contains a plurality of shallow trenches to isolate components on the semiconductor wafer, and the first dielectric layer is a silicon silicon * (Si〇x), which is used to fill the plurality of shallow trenches. ditch. C: \ CARRIE \ Desktop \ QR code \ NAU \ NAU-10.PTD page 11 4. If the method of item 2 of the patent is applied, wherein the semiconductor crystal contains a pad layer (pad Uye〇 under the second dielectric layer) made of silicon oxide (SiOx), it is used to prevent the first The second dielectric layer caused damage to the semiconductor wafer due to excessive surface stress caused by the addition. “,” 5. If the method of the scope of patent application No. 1, wherein the etch-back process is a dry etch process. '6 The method of claim 4 in which the dry etching process is completed in a dry etching system, and the etching comparison table is stored in the dry & engraving system, and the dry etching system will be based on the first The residual thickness of the dielectric layer and the etch-back procedure corresponding to the residual thickness in the etch lookup table automatically perform an etch process to horizontally remove the surface height from the first dielectric layer to the second dielectric layer.