--4Q396d________ 五、發明說明（1) 本發明係為一種多晶石夕層的ϋ刻方法，尤指_種閘極 之多晶矽層的蝕刻方法。 在半導體製程中，金氧半導體 (metal-oxide-semiconductor,簡稱M0S)電 (gate)主要是由一層多晶矽（pol y-s i 1 ic〇n)所構成，多晶 矽層經過微影與蝕刻製程之後，便能於一半導體晶片之二 電層上定养出閘極的結構。習知閘極線寬為小於〇Β Θ丨8 ": 的半導體製程中’為了調整M0S電晶體的起始電壓 (threshold voltage)，會先對多晶矽層進行離子佈植 (ion implantation)，然後微影與蝕刻製程，再進行熱處 理（heat treatment)製程以使雜質均勻地佈植於多晶矽層 内。對多晶矽層進行蝕刻製程時，多晶矽層上摻有雜質之 區域常會發生過度蝕刻的情形，使最後製作完成之各個閘 極的輪廓不同，進而降低半導體產品的可靠度 (reliability)。 請參閱圖一至圖三，圖一至圖三為使用習知蝕刻多晶 石夕層14的方法來製作閘極26、28的方法的示意圖。如圖一 所示’閘極線寬為〇 ·丨8 μ m的半導體製程中，習知m〇s電晶 體之閘極26、28的製作方法是先於一半導體晶片1 0表面依 序形成一介電層1 2 ’以及一多晶矽層丨4用來作為閘極之電 極。然後對多晶矽層1 4表面一特定區域進行一離子佈植製 程，使多晶石夕層1 4表面之一預定厚度内摻入雜質，以形成--4Q396d ________ V. Description of the invention (1) The present invention is a method for engraving a polycrystalline silicon layer, especially _ a method for etching a polycrystalline silicon layer of a gate electrode. In the semiconductor manufacturing process, a metal-oxide-semiconductor (M0S) gate is mainly composed of a layer of polycrystalline silicon (pol ys i 1 ic〇n). After the polycrystalline silicon layer is subjected to a lithography and etching process, The structure of the gate electrode can be set on two electrical layers of a semiconductor wafer. It is known that in a semiconductor process where the gate line width is less than 〇Β Θ 丨 8 ": In order to adjust the threshold voltage of the M0S transistor, an ion implantation is performed on the polycrystalline silicon layer, and then Lithography and etching processes, and then a heat treatment process to uniformly implant impurities in the polycrystalline silicon layer. During the etching process of the polycrystalline silicon layer, the regions doped with impurities on the polycrystalline silicon layer often undergo over-etching, which makes the contours of the final gates different from each other, thereby reducing the reliability of the semiconductor product. Please refer to FIGS. 1 to 3. FIGS. 1 to 3 are schematic diagrams of a method for fabricating the gate electrodes 26 and 28 using a conventional method for etching the polycrystalline silicon layer 14. As shown in Figure 1, in a semiconductor process with a gate line width of 0 μm and 8 μm, it is known that the manufacturing method of gates 26 and 28 of a m0s transistor is sequentially formed before a semiconductor wafer 10 surface. A dielectric layer 12 'and a polycrystalline silicon layer 4 are used as gate electrodes. Then, an ion implantation process is performed on a specific area on the surface of the polycrystalline silicon layer 14 so that impurities are doped into a predetermined thickness on the surface of the polycrystalline silicon layer 14 to form
_403964______ 五、發明說明（2) 一離子佈植層18。接著於多晶矽層14上形成一抗反射底層 2 2，用來減低半導體晶片1 〇之表面反射率，以避免影響閘 極圖案轉移的準確性。然後以一微影製程於抗反射底層2 2 表面之預定區域形成複數個剖面近似方形之光阻層2 4，用 來定義閘極圖案。 如圖二所示’接下來將未被光阻層24覆蓋之抗反射底 層22去除《然後對半導體晶片1 〇進行一蝕刻製程，垂直向 下去除未被光阻層24覆蓋之多晶矽層14以及離子佈植層 18。如圖三所不，隨後將光阻層24去除，而於預定區域内 之抗反射底層22以及多晶矽層丨6則會形成複數個剖面近似 長方形之閘極26、28。 習知蝕刻多晶矽層1 4的方法中，是使用氣氣（c u ' 溴化氫（HBr)、氦氣（He)以及氧氣（〇2)所組合而成的蝕刻 敗體。使用這種組合的蝕刻氣體會使多晶矽層丨6與離子佈 植層18之侧壁上產生二種差異極大的蝕刻速率，離子佈植— :18之側壁很容易被過度姓刻而產生凹陷，使含有離子佈-18的閘極26不具有近似垂直之側帛，而不含有離 =層18的閘極28則具有近似垂直之側②，如圖三所示。由 知蝕刻多晶矽層14的方法使製作完成之閘極⑼與閘極 28的輪廓不同，會降低半導體產品的可靠度。 因此本發明之主要目的在於提供一種蝕刻多晶矽層的_403964______ 5. Description of the invention (2) An ion implanted layer 18. An anti-reflective bottom layer 22 is then formed on the polycrystalline silicon layer 14 to reduce the surface reflectance of the semiconductor wafer 10 to avoid affecting the accuracy of the gate pattern transfer. Then, a photolithography process is used to form a plurality of photoresist layers 24 with a square cross-section in a predetermined area on the surface of the anti-reflection bottom layer 2 2 to define the gate pattern. As shown in FIG. 2 'the next step is to remove the anti-reflective underlayer 22 not covered by the photoresist layer 24, and then perform an etching process on the semiconductor wafer 10 to vertically remove the polycrystalline silicon layer 14 not covered by the photoresist layer 24 and Ion-implanted layer 18. As shown in FIG. 3, the photoresist layer 24 is subsequently removed, and the anti-reflection bottom layer 22 and the polycrystalline silicon layer 6 in a predetermined area will form a plurality of gates 26 and 28 having a substantially rectangular cross section. The conventional method for etching the polycrystalline silicon layer 14 is an etching failure composed of a combination of gas (cu 'hydrogen bromide (HBr), helium (He), and oxygen (〇2). Using this combination The etching gas will cause two very different etching rates on the sidewalls of the polycrystalline silicon layer 丨 6 and the ion implantation layer 18. The ion implantation —: 18 sidewalls can easily be engraved by excessive surnames to cause depressions, so that the ionic cloth- The gate electrode 26 of 18 does not have an approximately vertical side, and the gate electrode 28 without the ionization layer 18 has an approximately vertical side ②, as shown in Fig. 3. The method of etching the polycrystalline silicon layer 14 is known to complete the fabrication. The profile of the gate electrode ⑼ is different from that of the gate electrode 28, which will reduce the reliability of the semiconductor product. Therefore, the main object of the present invention is to provide an etching method for a polycrystalline silicon layer.
第5頁 403964 五 發明說明（3) 可以製作出相同輪廓之閘極， 曼。 矢高半導體產品 方法 的 可靠度 圖示之簡單說明 來製作M0S電 圖—至圖三為使用習知蝕刻多晶矽層的方、、 晶體之閘極的方法示意圖。 法 圖四至圖八為使用本發明蝕刻多晶矽層Page 5 403964 V Description of the invention (3) Gates with the same contour can be made. Reliability of the Yako Semiconductor product method. A simple explanation of the diagram. To make the MOS electrogram-Figure 3 is a schematic diagram of the conventional method for etching the square and crystal gates of a polycrystalline silicon layer. Method Figures 4 to 8 illustrate the use of the present invention to etch a polycrystalline silicon layer.
電晶體之閘極的方法示意圖。 、方法來製作M0S 圖示之符號說明 4〇半導體晶片 44多晶矽層 48抗反射底層 Μ、58閘極 42介電層 4 6 離qfL v心 5。植層 請參閱 晶硬層4 4的 明餘刻一半 閘極線寬小 閘極5 6、58 片4 0上經由 片40包含有 電層42，一 圖四至圖八，圖四至圖八為 方法來製作閘極56、58的方法用本發明蝕刻多 導體晶片40之多晶矽層44的方的不意圖。本發 於〇.18"m的半導體製程中來去，可以運用於 。製作MOS電晶體之閘極時，是電晶體之 J &先在半導體3 微影製程定義閘極圖案。定義完成的半導體晶 一由二氧4匕石夕（silicon dioxide)所構成的介 多晶矽層44設於介電層42上，一離子佈植層46 s又於多晶破層44表面·特定區域之預疋厚度内，一抗反 _i〇.396^______ 五、發明說明⑷ ' ' 射底層4 8設於多晶矽層4 4上，用來降低半導體晶片4 〇之表 面反射率，以及數個剖面近似方形之光阻層5 〇設於抗反射 底層48之數個預疋區域上方’如圖四所示。離子佈植層 是於多晶石夕層44表面之特定區域進行一離子佈植製程所形 成’使多晶矽層44表面之預定厚度内摻有雜質（d〇pant)， 用來調整MOS電晶體的起始電壓。在蝕刻多晶石夕層4 4之 前，先，行一底層乾蝕刻製程，以垂直向下去除未被光阻 層50覆蓋之抗反射底層48，直到多晶矽層44表面，如圊五 所示。 接下來進行本發明蝕刻多晶矽層44的方法，將半導體 晶片40置於一電漿氣壓驗（未顯示）中，在電漿的環境下進 行多晶矽層44的蝕刻製程。首先進行一第一乾蝕刻製程， 垂直向下去除未被光阻層50覆蓋之離子佈值層46，而未被 光阻層50覆蓋之多晶矽層44表面也會同時被去除掉相同的 厚如圖六所示。在第一蝕刻製程中’蝕刻氣體包含有 (：2^、氦與氧，其中以CgFe為主要蝕刻氣體，而且之氣 體流量為70至150sccm。電衆氣壓搶的操控條件如下：氣 壓艙壓力為10至20毫托耳（mTorr)，上電極功率為2〇〇至 300瓦（W) ’下電極功率為50至100瓦（W)，艙體溫度為攝氏 50至70度，以及承放半導體晶片之靜電承座 (electrostatic chuck)之溫度為攝氏65 至75 度。 然後進行一第二乾蝕刻製程’垂直向下去除多晶石夕層Schematic diagram of transistor gate method. Method to make the MOS icon symbol description 40 semiconductor wafer 44 polycrystalline silicon layer 48 anti-reflection bottom layer M, 58 gate 42 dielectric layer 4 6 away from qfL v center 5. Please refer to the crystal hard layer 44 for the engraving layer. The half gate width of the gate is small. The gate 5 is small. The gate 5 contains the electrical layer 42 through the sheet 40. Figures 4 to 8 and Figures 4 to 8 show the methods. The method of making the gate electrodes 56 and 58 is not intended to etch the polycrystalline silicon layer 44 of the multi-conductor wafer 40 by the present invention. This invention came and went in the semiconductor process of 0.018 " m and can be applied to. When making the gate of a MOS transistor, it is the J & transistor that first defines the gate pattern in the semiconductor 3 lithography process. The finished semiconductor crystal is defined. A dielectric polycrystalline silicon layer 44 composed of silicon dioxide is provided on the dielectric layer 42. An ion implantation layer 46 s is on the surface of the polycrystalline broken layer 44 in a specific area. Within the pre-thickness thickness, primary anti-reflection_i〇.396 ^ ______ 5. Description of the invention '' 'The radiation base layer 4 8 is provided on the polycrystalline silicon layer 44 to reduce the surface reflectance of the semiconductor wafer 40 and several A photoresist layer 50 having an approximately square cross section is provided over a plurality of predetermined regions of the antireflective bottom layer 48 'as shown in FIG. The ion implantation layer is formed by performing an ion implantation process on a specific area of the surface of the polycrystalline silicon layer 44 so that a predetermined thickness of the surface of the polycrystalline silicon layer 44 is doped with impurities (dopant) to adjust the MOS transistor. Starting voltage. Prior to etching the polycrystalline silicon layer 44, a bottom dry etching process is performed to vertically remove the anti-reflective bottom layer 48 not covered by the photoresist layer 50, until the surface of the polycrystalline silicon layer 44 is shown in Fig. 5. Next, the method for etching the polycrystalline silicon layer 44 according to the present invention is performed. The semiconductor wafer 40 is placed in a plasma pressure test (not shown), and the polycrystalline silicon layer 44 is etched in a plasma environment. First, a first dry etching process is performed to vertically remove the ionic cloth value layer 46 not covered by the photoresist layer 50, and the surface of the polycrystalline silicon layer 44 not covered by the photoresist layer 50 is also removed at the same time. As shown in Figure 6. In the first etching process, the etching gas contains (: 2 ^, helium and oxygen, in which CgFe is the main etching gas, and the gas flow rate is 70 to 150 sccm. The operating conditions of the electric pressure grab are as follows: 10 to 20 millitorr (mTorr), the upper electrode power is 2000 to 300 watts (W) 'the lower electrode power is 50 to 100 watts (W), the cabin temperature is 50 to 70 degrees Celsius, and the semiconductor The electrostatic chuck temperature of the wafer is 65 to 75 degrees Celsius. Then a second dry etching process is performed to remove the polycrystalline layer vertically downward.
第7頁 403964 五、發明說明（5) 4 4未被光阻層5 0覆篆夕悉丨丨你z丨人Λ 復盍之剩餘部份直到介電層42之表面，如 不，便完成本發明蝕刻多晶矽層4 4 一 蝕刻製程中，蝕刻氣俨勿人古备rri、 次在第一 iHe)以；有氣（2)、溴化氫（ΗΒΓ)、氦 域内之ίη將光阻層5〇完全去除，而於預定區 :8以及多晶矽層44則會形成數個剖面近 似長方形之閘極56、58，如圖八所示。 迎 利用本發明蝕刻多晶矽層44的方法來製 時1電裝氣壓艙中使用…刻氣體來 蝕刻製程，以蝕刻吝曰访s a 咕+琨仃弟及第一 刻氣體包含有cf、h 第一蝕刻製程所使用的蝕 進行第-蝕ί 46程時及02，而以Μ6為主要蝕刻氣體。 例以及電漿氣壓艙整主要㈣和其他敍刻1體的比 雜質之多晶矽層條件離子佈植層46與未摻雜 以避免離子佈植；46的上產生的姓刻速率大致相同，可 一蝕刻^ 側壁被過度蝕刻而產生凹陷。而第 〇：』去二ίΓ的餘刻氣體包含有、，、He以* 產品的可靠度提$ :成為近似垂直的輪廓，可以使半導體 利用本發明方、、上 微鏡（SEM)觀察，鬥1所製成的閘極56、58於掃瞄式電子顯 廓。除此之外，姆56、58的側壁均為近似垂直的輪 晶矽層44之方法所制實驗統計後得知，使用本發明蝕刻多 爰作的閘極56、58，其最小閘極線寬變Page 7 403964 V. Description of the invention (5) 4 4 is not covered by the photoresist layer 5 0 丨 丨 you z 丨 the rest of the Λ compound is up to the surface of the dielectric layer 42, if not, it is completed In the etching process of the polycrystalline silicon layer of the present invention, the photoresist layer is etched in the first iHe), and the photoresist layer is formed by gas (2), hydrogen bromide (ΗΒΓ), and helium. 50 is completely removed, and in the predetermined region: 8 and the polycrystalline silicon layer 44, a plurality of gate electrodes 56 and 58 having approximately rectangular cross-sections are formed, as shown in FIG. The method for etching the polycrystalline silicon layer 44 according to the present invention is used to make an etching process using a ... etching gas in an electric equipment pressure chamber to etch a sa + 琨 仃 and the first engraving gas contains cf, h The etching used in the etching process is performed at the 46th and 02th, and M6 is the main etching gas. Examples and plasma pressure chambers are mainly polycrystalline silicon and other polycrystalline silicon layers that are etched in the polycrystalline silicon layer. The ion implantation layer 46 is not doped to avoid ion implantation. The engraving rate generated on 46 is approximately the same. Etching ^ Side walls are over-etched to create depressions. And 〇: "The second-minute gas contains", "," He "is improved by the reliability of the product: it becomes an approximately vertical profile, which enables the semiconductor to be observed using the present invention, the upper micromirror (SEM), The gates 56, 58 made by the bucket 1 are displayed in a scanning electronic display. In addition, the side walls of M56 and M58 are made by the method of approximately vertical ring-shaped silicon layer 44. According to the experimental statistics, it is known that using the present invention to etch multiple gates 56,58, the minimum gate line Wide change
第8頁 403964___ 五、發明說明（6) ' " ' 化之三個標準差小於1〇毫微米（nm) ’而且蝕刻前和蝕刻後 的最小閘極線寬的偏差（bias)也能獲得良好的控制，可以 使問極56、58之最小閘極線寬（criticai dlmensi〇n gate length)數值維持穩定。 相車乂於省知I虫刻_多晶矽層1 4的方法，本發明飯刻多晶 石夕層44的方法是以做為主要蝕刻氣體來進行第一蝕刻 製程.，以去除離子佈植層46和多晶矽層44 ,並使其側壁均 ，，近似垂直的輪廓，然後再使用成分不同之蝕刻氣體進 订第二乾蝕刻製程，將未為該光阻層覆蓋的剩餘多晶矽岸 44去除’使閘極56、58之側壁均為近似垂直的輪廓。因在曰 使用本發明方法所製作的閘極56、5 8均具有相同的輪廓， 可以提高半導體產品的可靠度。 以上所述僅為本發明之較佳實施例，凡依本發明申枝 專利範圍所做之均等變化盥修飾，皆應屬本發明專利二 蓋範圍。一 ，、 艾/函Page 8 403964___ 5. Description of the invention (6) '"' Three standard deviations of less than 10 nanometers (nm) 'and the minimum gate line width deviation (bias) before and after etching can also be obtained Good control can keep the minimum gate line length (criticai dlmension gate length) of the question poles 56 and 58 stable. According to the method of engraving the polycrystalline silicon layer 14 in the province I, the method of engraving the polycrystalline stone layer 44 of the present invention is to perform the first etching process as the main etching gas to remove the ion implanted layer. 46 and polycrystalline silicon layer 44 and make their sidewalls uniform and approximately vertical outline, and then use an etching gas with a different composition to order a second dry etching process to remove the remaining polycrystalline silicon shore 44 that is not covered by the photoresist layer. The side walls of the gate electrodes 56 and 58 are approximately vertical contours. Because the gates 56 and 58 produced by the method of the present invention all have the same profile, the reliability of the semiconductor product can be improved. The above description is only a preferred embodiment of the present invention, and any equivalent modification made in accordance with the scope of the patent application of the present invention shall fall within the scope of the second patent of the present invention. A, Ai / letter