TW396613B - Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods - Google Patents

Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods Download PDF

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Publication number
TW396613B
TW396613B TW087105867A TW87105867A TW396613B TW 396613 B TW396613 B TW 396613B TW 087105867 A TW087105867 A TW 087105867A TW 87105867 A TW87105867 A TW 87105867A TW 396613 B TW396613 B TW 396613B
Authority
TW
Taiwan
Prior art keywords
metal
layer
insulating layer
opening
bit line
Prior art date
Application number
TW087105867A
Other languages
English (en)
Chinese (zh)
Inventor
Jian-Mai Sung
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW087105867A priority Critical patent/TW396613B/zh
Priority to JP12240098A priority patent/JP3950547B2/ja
Application granted granted Critical
Publication of TW396613B publication Critical patent/TW396613B/zh

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  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW087105867A 1998-04-17 1998-04-17 Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods TW396613B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW087105867A TW396613B (en) 1998-04-17 1998-04-17 Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods
JP12240098A JP3950547B2 (ja) 1998-04-17 1998-05-01 低いビット線間結合容量を有する低抵抗ビット線構造の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087105867A TW396613B (en) 1998-04-17 1998-04-17 Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods

Publications (1)

Publication Number Publication Date
TW396613B true TW396613B (en) 2000-07-01

Family

ID=21629897

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087105867A TW396613B (en) 1998-04-17 1998-04-17 Low resistance bitline structure with low bitline to bitline coupling capacitance and its methods

Country Status (2)

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JP (1) JP3950547B2 (ja)
TW (1) TW396613B (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100393971B1 (ko) * 2000-12-29 2003-08-06 주식회사 하이닉스반도체 임베디드 디램 로직의 비트라인 및 그 형성방법
JP2004128395A (ja) 2002-10-07 2004-04-22 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
EP2328171A1 (en) * 2002-12-27 2011-06-01 Fujitsu Semiconductor Limited Method of producing dram integrated circuit device
WO2005024957A1 (ja) 2003-08-29 2005-03-17 Fujitsu Limited 半導体装置とその製造方法
JP2009246374A (ja) * 2009-06-04 2009-10-22 Renesas Technology Corp 半導体装置
KR20130044496A (ko) * 2011-10-24 2013-05-03 에스케이하이닉스 주식회사 배선 상에 셀 패턴이 형성되는 반도체 메모리 소자 및 그 제조 방법

Also Published As

Publication number Publication date
JP3950547B2 (ja) 2007-08-01
JPH11307742A (ja) 1999-11-05

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