五、發明說明（1) --—__ 本發明是有關於一種半導體製程，且特別是 種解決解決隔離製程中孔洞引起電性短路的方法。於一 習知一種電容器下電極或者導電插栓製程主 含半導體元件之基底表面覆蓋一介電層，例如氧化3 在 漿加強-四乙氧基矽化物（PE-TEOS)等，然後再利用I馬電 序以及蝕刻技術定義此介電層，並在預定形成電容界’v程 極或導電插栓處定義出一連接半導體元件之接觸下電 著再形成一導電層例如金屬層或者複晶矽層於該二電層接 上，並且溝填該接觸開口，然後再利用化學機械研磨 回蝕刻法進行平坦化處理，去除介電層上多餘的導電層及 於接觸開口内形成一連接該些半導體元件的導電層，^ 為電容器之下電極或導電插栓等。然而，由於元二的線^ 逐漸縮小’積集度也曰益增加，因此以介電層覆蓋含半導 體元件之基底時，溝填特性不佳的介電材料便容易導致孔 洞的出現。此孔洞將導致後續形成之電容器下層電極或導 電插栓產生非設計的電性短路現象，影響設計元件的性 能。 為使此習知製程之缺點更清楚可見，玆將以以〜^圖 以及1A ’〜1E ’圖詳細說明如下。 首先’§青參照第1A圖’提供一半導體基底，且基 底100上更形成有電晶體丨4〇a、14〇b、14〇c以及140d。第 1A圖顯示的乃是根據第1 a圖中的剖面線I — I ’剖開之剖面 圖’由圖中更可看到電晶體14〇a以及14此均係由一閘極氧 化層11 0、閘電極1 20以及環繞於閘極側壁之絕緣侧壁子V. Description of the invention (1) ---__ The present invention relates to a semiconductor process, and in particular to a method for solving an electrical short circuit caused by a hole in an isolation process. In a conventional method, a capacitor lower electrode or a conductive plug is mainly covered with a dielectric layer on the surface of a substrate containing a semiconductor element, such as oxide 3 in a slurry reinforced-tetraethoxysilicide (PE-TEOS), etc., and then use I The Ma Dian sequence and etching technology define this dielectric layer, and define a conductive layer such as a metal layer or a polycrystalline silicon under contact with a semiconductor element at a predetermined distance to form a capacitor boundary or a conductive plug. Layers are connected to the two electrical layers, and the contact openings are filled by trenches, and then chemical mechanical polishing and etch-back are used for planarization to remove excess conductive layers on the dielectric layer and form a connection to the semiconductors in the contact openings. The conductive layer of the component is the electrode below the capacitor or the conductive plug. However, due to the gradual shrinking of the wiring of Yuaner ', the accumulation degree also increases, so when a semiconductor layer is used to cover a substrate containing a semiconductor element, a dielectric material with poor trench filling characteristics can easily cause holes to appear. This hole will cause un-designed electrical short circuit of the capacitor's lower electrode or conductive plug which will be formed later, which will affect the performance of the designed component. In order to make the shortcomings of this conventional process more clearly visible, the following will be described in detail with the drawings ~ 1 and 1A '~ 1E'. First, a semiconductor substrate is provided by "§ 青 referencing Fig. 1A", and transistors 100a, 140b, 140c, and 140d are further formed on the substrate 100. Fig. 1A shows the section line I-I in Fig. 1 a. "Cross-section view" The transistor 14Oa and 14 can be seen from the gate oxide layer 11 0, gate electrode 1 20 and insulating side wall surrounding the gate side wall
C:\ProgramFiles\Patent\0503-3999-E. ptd第 4 頁C: \ ProgramFiles \ Patent \ 0503-3999-E. Ptd page 4
1 3 0所構成。 其次’請參照第1 Β圖及第1Β，圖，利用習知的女 相沉積法形成一介電層150於基底1〇〇上，其中介 予乱 例如可為一般的氧化矽或電漿加強四乙氧基化' 1 50 (PE-TEOS)等介電材料。其中，由於元件的積極度择 導致介電層1 50沉積於基底1 〇0上時，因為溝 9 口， 生一條如圖所示的孔洞1 5 5。 土而產 η 接著，請參照第1C圖及第lc，圖，介電層15〇經平坦化 後，形成一表面平坦的介電層150，，然後再利用微影程 以及蝕刻技術定義之，並於電晶體14〇3和14〇1>間以及電晶 體140c和140d間分別形成一接觸開口 16〇a和16〇1)。其中曰，曰 接觸開口 l6〇a和160b並被先前存在的孔洞155所貫穿。 然後’請參照第1D圖及第1D’圖，形成一導電層 170(複晶矽層或金屬層）於介電層15〇，上，並且溝填接觸 開口 160a和1 60b。其中，由於接觸開口 160a和！ 6〇b被先前 存在的孔洞155所貫穿，故在導電層17〇溝填接觸開口丨6〇a 和160b時，導電層170也會進入貫穿接觸開口的孔洞丨55 内’導致接觸開口 1 60a和1 6 Ob内的導電層1 70是連接的。 最後請參照第1 E圖和第1 E ’圖，以化學機械研磨法或 回蝕刻法進行平坦化處理’去除介電層15〇，上多餘的導電 層1 70 ’於接觸開口 1 60a和1 60b内分別形成一預備作為電 容器下電極或導電插栓之導電層l80a和1801：)。然而，此二 導電層1 8 0 a和1 8 0 b間是互相導通的，因此將發生非設計的 電性短路現象’在元件運作時將導致元件性能受損。1 3 0. Secondly, please refer to FIG. 1B and FIG. 1B, using a conventional female phase deposition method to form a dielectric layer 150 on the substrate 100. The intervening disorder can be reinforced by ordinary silicon oxide or plasma, for example. Tetraethoxylated '1 50 (PE-TEOS) and other dielectric materials. Among them, when the dielectric layer 150 is deposited on the substrate 1000 due to the active selection of the element, a hole 1 55 is formed because of the groove 9 as shown in the figure. Η from soil Next, please refer to FIG. 1C and FIG. 1c, the dielectric layer 150 is planarized to form a dielectric layer 150 with a flat surface, and then defined by lithography and etching technology, A contact opening 160a and 1601 are formed between the transistors 1403 and 1401 and between the transistors 140c and 140d, respectively). Among them, the contact openings 160a and 160b are penetrated by the previously existing holes 155. Then, referring to FIG. 1D and FIG. 1D, a conductive layer 170 (a polycrystalline silicon layer or a metal layer) is formed on the dielectric layer 150, and the trenches fill the openings 160a and 160b. Among them, due to the contact opening 160a and! 6〇b is penetrated by the preexisting hole 155, so when the conductive layer 170 fills the contact opening 丨 60a and 160b, the conductive layer 170 will also enter the hole penetrating the contact opening 55, which will cause the contact opening 1 60a It is connected to the conductive layer 1 70 in 16 Ob. Finally, please refer to FIG. 1E and FIG. 1E 'to perform planarization by chemical mechanical polishing method or etch-back method' to remove the dielectric layer 15 and the extra conductive layer 1 70 'on the contact openings 1 60a and 1 In 60b, a conductive layer 180a and 1801, which are prepared as capacitor lower electrodes or conductive plugs, are formed respectively :). However, the two conductive layers 180a and 180b are conductive with each other, so a non-designed electrical short-circuit phenomenon will occur, and the performance of the device will be impaired when the device is operating.
C:\Program Files\Patent\0503-3999-E.ptd第 5 頁 五、發明說明（3) ' — 有鑑於此，本發明乃揭示一種解決隔離製程中孔洞引 起電性短路的方法，其步驟包栝：提供一含半導體元件之 基底；、形成一介電層於該基底上；利用微影程序及蝕刻技 術形$ —連接該半導體元件之接觸開口；形成一薄絕緣層 於該介電層上以及該接觸開口的内壁和底部；去除位在該 介電層，面以及該接觸開口底部之該薄絕緣層；形成一導 電層於該介電層上，並且溝填該接觸開口；以及施一平坦 化處理’去除多餘的該導電層至該介電層為止。如上所述 之方法’其中該介電層之材料係選自電漿加強-四乙氧基 f化物（PE-TEOS)和高密度電漿氧化物（HDp 〇xide)等化學 氣相沉積層所構成之族群；該導電層之材料係由複晶矽或 金屬，構成；該薄絕緣層之材料可為厚度為3 〇 〇埃之低壓 化學氣相沉積層’例如低壓化學氣相沉積的四乙氧基矽化 物（LP-TEOS)或低壓化學氣相沉積的氮化矽（Lp_si3D，或 者厚度為300埃之電漿加強的化學氣相沉積的氧化層或電 漿加強的化學氣相沉積的四乙氧基石夕化物層。 為使本發明之優點以及特徵更清楚可見，玆將以根據 本發明之較佳實施例，並配合相關圖式，詳細說明如下。 圖式之簡單說明： ，第1A〜1 E圖是習知一種隔離製程之上視圖。 第1A〜1 E’圖是根據第丨a〜丨E圖中的剖面線j —丨，剖 開之剖面製程。 第2A〜2F圖是根據本發明之隔離製程的上視圖。 第—2 A〜2 F V圖是根據第2 A〜2 F、圖中的剖面線π — Π，C: \ Program Files \ Patent \ 0503-3999-E.ptd page 5 V. Description of the invention (3) '— In view of this, the present invention discloses a method for solving an electrical short caused by a hole in an isolation process, and the steps thereof Baggage: providing a substrate containing a semiconductor element; forming a dielectric layer on the substrate; using a lithography process and an etching technique to form a contact opening to the semiconductor element; forming a thin insulating layer on the dielectric layer And the inner wall and bottom of the contact opening; removing the thin insulating layer located on the dielectric layer, the surface, and the bottom of the contact opening; forming a conductive layer on the dielectric layer, and trench filling the contact opening; and applying A planarization process' removes the excess of the conductive layer to the dielectric layer. The method as described above, wherein the material of the dielectric layer is selected from chemical vapor deposition layers such as plasma reinforced-tetraethoxyfide (PE-TEOS) and high-density plasma oxide (HDp oxide). The material of the conductive layer is composed of polycrystalline silicon or metal; the material of the thin insulating layer may be a low pressure chemical vapor deposition layer having a thickness of 300 angstroms, such as low pressure chemical vapor deposition of tetraethyl Oxide silicide (LP-TEOS) or low-pressure chemical vapor deposition of silicon nitride (Lp_si3D, or plasma-enhanced chemical vapor deposition oxide layer or plasma-enhanced chemical vapor deposition with a thickness of 300 angstroms) Ethoxylate layer. In order to make the advantages and features of the present invention more clearly visible, the preferred embodiment according to the present invention will be described in detail below in conjunction with the related drawings. Brief description of the drawings:, 1A Figure 1E is a top view of a conventional isolation process. Figure 1A ~ 1E 'is a cross-sectional process taken according to the section line j — 丨 in Figures 丨 a ~ 丨 E. Figures 2A ~ 2F are Top view of the isolation process according to the present invention. -2 A ~ 2 FV The figure is based on 2A ~ 2F, the section line π — Π in the figure,
C:\Program Files\Patent\0503-3999-E.ptd第 6 頁 五、發明說明（4) 剖開之剖面製程。 <· 實施例： 首先’請參照第2A圖，提供一半導體基底2〇〇，且基 底2 0 0上更形成有電晶體240 a、240b、240c以及240d。第 2 A圖顯示的乃疋根據第2 A圖中的剖面線；π — π，剖開之剖 面圖，由2Α’圖中更可看到電晶體24 0a以及24Ob均係由一 閘極氧化層2 1 0、閘電極2 2 0以及環繞於閘極側壁之絕緣側 壁子23 0所構成。 其次’請參照第2 B圖及第2B，圖，利用習知的化學氣 相沉積法形成一介電層250於基底200上，其中該介電層 2 5 0例如可為一般的氧化矽或電漿加強—四乙氧基石夕化物 (PE-TE0S)等介電材料。其中，由於元件的積極度增加， 導致介電層250沉積於基底200上時，因為溝填性不佳而產 生一條如圖所示的孔洞2 5 5。 接著’請參照第2 C圖及第2 C ’圖’介電層2 5 〇經平坦化 後’形成一表面平坦的介電層25 0’ ，然後再利用微影程序 以及蝕刻技術定義之，並於電晶體2 4 0 a和2 4 0 b間以及電晶 體240c和240d間分別形成一接觸開口 260a和2 6 0b。其中， 接觸開口260a和260b並被先前存在的孔洞255所貫穿。 然後，請參照第2D圖’為防止貫穿接觸開口 26 〇a和 260b的孔洞2 55在導電層填入後導致兩接觸開口 26〇a和 2 6 0 b產生短路’故本發明乃施一封孔的步驟，形成一絕緣 層270於介電層250上以及接觸開口 260a和260b之内壁以及 底部’將接觸開口 2 6 0 a和2 6 0 b侧壁之孔洞封住。絕緣層C: \ Program Files \ Patent \ 0503-3999-E.ptd page 6 V. Description of the invention (4) Sectional cutting process. < Example: First, please refer to FIG. 2A, a semiconductor substrate 200 is provided, and transistors 240a, 240b, 240c, and 240d are further formed on the substrate 200. Figure 2A shows Naaru according to the section line in Figure 2A; π — π, the cut-away section view, it can be seen from Figure 2A ′ that the transistors 24 0a and 24Ob are oxidized by a gate. The layer 2 10, the gate electrode 220, and an insulating sidewall 230 surrounding the gate sidewall are formed. Secondly, please refer to FIG. 2B and FIG. 2B, a dielectric layer 250 is formed on the substrate 200 by a conventional chemical vapor deposition method, where the dielectric layer 250 can be, for example, ordinary silicon oxide or Plasma Strengthening-Diethoxylate (PE-TE0S) and other dielectric materials. Among them, due to the increased enthusiasm of the components, when the dielectric layer 250 is deposited on the substrate 200, a hole 2 5 5 is generated because of poor trench filling properties. Next, 'please refer to Figure 2C and 2C' Figure ', after the dielectric layer 250 is flattened,' a dielectric layer 25 0 with a flat surface is formed. Then, it is defined by the lithography process and etching technology. A contact opening 260a and 2 6 0b are formed between the transistors 2 40 a and 2 4 0 b and between the transistors 240 c and 240 d, respectively. Wherein, the openings 260a and 260b are contacted and penetrated by the previously existing holes 255. Then, please refer to FIG. 2D. In order to prevent the holes 2 55 penetrating through the contact openings 26 0a and 260b after the conductive layer is filled, the two contact openings 26 0a and 2 6 0 b are short-circuited. In the step of forming a hole, an insulating layer 270 is formed on the dielectric layer 250 and the inner walls and the bottom of the contact openings 260a and 260b to seal the holes in the sidewalls of the contact openings 2 60 a and 2 60 b. Insulation
C:\Program Files\Patent\0503-3999-E.ptd第 7 頁 五、發明說明（5) 2 7 0之材料例如可為低壓化學氣相沉積法所形成的四乙氧 基矽化物層（LP-TEOS)、氮化矽層（Lp_Si3N4)，或者利用電 漿加強化學氣相沉積法所形成的氧化層（pE_〇xide)或四乙 氧基矽化物層（PE-TEOS)等。 然後，請參照第2E圖以及第2E，圖，施一乾蝕刻法， 去除介電層2 50’表面以及接觸開口 26〇a和26(^底部之絕緣 層270去除。 最後，請參照第2F圖以及第評，圖，先形成一複晶矽 或金屬所構成之導電層（未顯示）於介電層25〇，上，並且溝 填接觸開口260a和260b。其_，由於接觸開口 26〇&和26〇1) 之侧壁已經被絕緣層270所覆蓋，孔洞255已盔法貫穿此二 接，開口，故導電層270填入接觸開口“仏和“⑽後不會 =:1L=5内，阻止電性短路的現象發生。然後，再 :用化子機械研磨法或回蝕刻法去除多餘的導電層2冗 ΐ哭;I於接觸開口26〇3和26心内分別形成一預備作為電 谷m下電極或導電插栓之導電層28(^和28(^。 發明已以較佳實施例揭露如上，然其並非用以 所：何熟習此技藝者，在不脫離本發明之精神 内’所作之各種更動與潤飾均落在本發 内，因此本發明之專利保護範圍當 所界定者為準。 段町 < 甲5月專利粑圍C: \ Program Files \ Patent \ 0503-3999-E.ptd page 7 5. Description of the invention (5) The material of 2 7 0 can be, for example, a tetraethoxy silicide layer formed by a low pressure chemical vapor deposition method ( LP-TEOS), silicon nitride layer (Lp_Si3N4), or an oxide layer (pE_〇xide) or a tetraethoxysilicide layer (PE-TEOS) formed by plasma enhanced chemical vapor deposition. Then, referring to FIG. 2E and FIG. 2E, a dry etching method is applied to remove the surface of the dielectric layer 250 ′ and the contact openings 26〇a and 26 ″, and the insulating layer 270 at the bottom is removed. Finally, please refer to FIG. 2F As shown in the figure, a conductive layer (not shown) composed of polycrystalline silicon or metal is first formed on the dielectric layer 250, and the trench fills the contact openings 260a and 260b. Since the contact opening 26o & And 26〇1) The side wall has been covered by the insulating layer 270, and the hole 255 has been passed through the two joints and opened, so the conductive layer 270 fills the contact opening "仏 and" ⑽ will not =: 1L = 5 Within, to prevent the occurrence of electrical short circuit. Then, use the chemical mechanical polishing method or etch-back method to remove the excess conductive layer. 2 I form a cryoelectric electrode or conductive plug in the contact openings 2603 and 26 respectively. The conductive layer 28 (^ and 28 (^.) The invention has been disclosed in the preferred embodiment as above, but it is not intended to be used: Any person skilled in this art can make various changes and finishes without departing from the spirit of the present invention. Within the scope of this publication, the scope of patent protection of the present invention shall prevail as defined.