鉀濟部中央樣準而只工消贽合作妇印架 33 5 6twf.d〇c/〇〇6 A 7 ——— B7 五、發明説明（/ ) 本發明是有關於一種埋入式動態隨機存取記憶體 (Embedded DRAM)自動對準金屬矽化物（sal icide)的製造 方法，且特別是有關於一種防止邏輯電路區（logic region) 雙閘極（dual gate)結構發生內擴散（inter diffusion)， 且降低閘極阻値（resistance)之自動對準金屬矽化物的 製造方法。 埋入式動態隨機存取記憶體定義成邏輯電路區與動態 隨機記憶體區（下文以記憶體區稱之），傳統邏輯電路區之 閘極結構係由以N型複晶矽閘極形成之N型金氧半場效電 晶體（N-type MOS Field Effect Transistor，nMOSFET) 與P型金氧半場效電晶體（pMOSFET)所構成而形成互補式 金氧半導體（CMOS)結構，由於以N型複晶矽閘極形成之 PM0S易產生擊穿效應（punch through)，與較差的關閉特 性（turnoff characteristics)，因此趨向採用N型複晶 矽閘極NM0S與P型複晶矽層閘極PM0S之雙閘極結構應用 在邏輯電路區上，以降低上述不良的效應。 其中，爲避免埋入式DRAM源/汲極區電流遺漏（current leakage)的現象過於嚴重，因此埋入式DRAM中的源/汲極 區不能形成自動對準矽化物，但爲降低複晶矽閘極阻値， 故在複晶矽層上提供一矽化鎢層以增進閘極的導電性。然 對於埋入式DRAM邏輯電路區之雙閘極結構而言，於複晶 矽層上形成矽化鎢，雖可降低雙閘極結構阻値，但卻也引 發了一些問題，如第1A圖至第1C圖所示，爲習知埋入式 動態隨機存取記憶體自動對準金屬矽化物之製造流程剖 3 (誚先閱讀背面之注意事項再填寫本I) ο! 裝. 、vs 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3356twf.doc/006 A7 B7 經濟部中央榀準'^只工消贽合作拉卬製 五、發明説明（1) 面圖。 請參照第1A圖，在一基底100上形成有一閘極氧化物 層102與一複晶矽層104a、1〇4b，接葦利用植入罩幕覆蓋 基底100 ’而分別對複晶矽層104進行植入p型離子與N 型離子的步驟’接著，在複晶矽層104上形成一矽化鎢 ，106，以增進後續形成閘極之導電性，續定義矽化鎢106、 複晶砍層104與閘極氧化物層102,而形成如第1B圖所示 之雙閘極結構l〇8a與閘極結構i〇8b。其中第2圖所示爲 第1B圖雙閘極結構108a與閘極結構1〇8b之立體圖，而 雙閘極結構l〇8a具有N型104a，與P型複晶矽層104a"， 閘極結構108b具有N型複晶矽層104b。再分別對基底進 行N型與P製淡摻雜汲極（LDD)結構u〇，並在閘極結構 108a、108b側邊形成氮化矽間隙壁（spacer)112，繼續對 基底100進行植入的步驟，以分別完成N型與P型源/汲 極區114’並進行約1000°C之高溫快速熱製程（Rapid Thermal Process, RTP)，以使源/汲極區114之離子活性 化。 如第1C圖所示，接著對基底1〇〇覆蓋一氧化物層，並 藉形成罩幕蝕刻定義氧化物層，使氧化物層116覆蓋住部 分基底100，而覆蓋氧化物層116的部分定義爲邏輯電路 區118a ’而未遭覆蓋的部分則定義爲記憶體區118b。 之後，在基底100形成一鈦金屬層，再進行RTP，使鈦 金屬層與暴露出的基底100反應，在邏輯電路區118a暴 露出的源/汲極區114形成鈦矽化物120,如第1D圖所示。 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (諳先閱讀背面之注意事項再填寫本頁) Θ $ 、τ A7 B7 3356twf.d〇c/〇〇6 五、發明説明（多） 在上述製程中，矽化鎢106形成的目的在增加複晶矽 層104的導電性，然在進行RTP製程中，由於高溫的影響， 再加上雜質在矽化鎢層1〇6中的_散係數（diffusion coefficient)較大’導致邏輯電路區118a之雙閘極結構 108a，複晶矽層中的N型雜質經由矽化鎢106擴散 進入P型複晶矽層104a"，而複晶矽層l〇4a〃中的P型雜質 亦經由矽化鎢1〇6擴散進入N型複晶矽層104a'中，而引 發所謂內擴散丨22的現象’如第2圖所示，而內擴散現象 將導致雙閘極失效。 另一方面，矽化鎢106/複晶矽層104因形成閘極結構 而需進行的定義步驟’亦因矽化鎢的存在而使得定義 製程較爲困難。 有鑑於此，本發明的主要目的之一，就是在避免雙閘 極結構中的內擴散現象’而確保元件的可靠性。 本發明之另一目的，就是在邏輯電路區的閘極、源/汲 極區與記憶體區之閘極上形成自動對準金屬矽化物，以增 加閘極的導電性。 爲達上述之目的，本發明提供一種埋入式動態隨機存 取記憶體自動對準金屬化物之製造方法，首先在一基底的 邏輯電路區形成一複晶砂雙閘極結構，在記憶體區形成一 閘極結構。之後，對基底依序形成一絕緣層、一硬材料層 與一介電層。經由回鈾刻、光罩定義，再蝕刻等步驟，而 暴露出邏輯電路區之雙閘極結構與源/汲極區以及記憶體 區之閘極結構。之後再於暴露出邏輯電路區之雙閘極結構 5 尺度迫则’國國家標準（CNS )八4職（210X297公楚） (請先閲讀背面之注意事項再填寫本頁)The central sample of the Ministry of Economics and Economics is only used to eliminate the cooperative printing frame 33 5 6twf.d〇c / 〇〇6 A 7 ——— B7 V. Description of the invention (/) The present invention relates to an embedded dynamic random Manufacturing method for automatically aligning metal silicide (Embedded DRAM) with access memory, and in particular, it relates to a method for preventing dual diffusion gate structure in logic region from inter diffusion ), And a method for automatically aligning metal silicide with reduced gate resistance (resistance). The embedded dynamic random access memory is defined as a logic circuit area and a dynamic random memory area (hereinafter referred to as a memory area). The gate structure of the traditional logic circuit area is formed by an N-type complex silicon gate. N-type MOS Field Effect Transistor (nMOSFET) and P-type MOSFET (pMOSFET) form a complementary metal-oxide-semiconductor (CMOS) structure. The PM0S formed by the crystalline silicon gate is prone to punch-through effects and poor turnoff characteristics. Therefore, the dual use of the N-type compound silicon gate NM0S and the P-type compound silicon layer gate PM0S is preferred. The gate structure is applied to the logic circuit area to reduce the above-mentioned undesirable effects. Among them, in order to prevent the current leakage of the source / drain region of the embedded DRAM from being too serious, the source / drain region of the embedded DRAM cannot form an auto-aligned silicide, but to reduce the polycrystalline silicon The gate resistance is high, so a tungsten silicide layer is provided on the polycrystalline silicon layer to improve the conductivity of the gate. However, for the dual-gate structure of the buried DRAM logic circuit area, the formation of tungsten silicide on the polycrystalline silicon layer can reduce the resistance of the dual-gate structure, but it also causes some problems, as shown in Figure 1A to As shown in Figure 1C, the manufacturing process of the conventional embedded dynamic random access memory to automatically align with metal silicide is shown in section 3 (诮 Read the precautions on the back before filling in this I) ο! Packing, vs. this paper The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 3356twf.doc / 006 A7 B7 Central Ministry of Economic Affairs, Standardization, Cooperation, and Cooperative Production System V. Description of the invention (1) Plan view. Referring to FIG. 1A, a gate oxide layer 102 and a polycrystalline silicon layer 104a, 104b are formed on a substrate 100. Then, the polycrystalline silicon layer 104 is covered by the implant mask to cover the substrate 100 ', respectively. The step of implanting p-type ions and N-type ions is performed. Next, a tungsten silicide, 106 is formed on the polycrystalline silicon layer 104 to improve the conductivity of the subsequent formation of the gate electrode. The tungsten silicide 106 and the polycrystalline cleave layer 104 are further defined. And the gate oxide layer 102 to form a double gate structure 108a and a gate structure 108 as shown in FIG. 1B. FIG. 2 shows a perspective view of the double-gate structure 108a and the gate structure 108b of FIG. 1B, and the double-gate structure 108a has an N-type 104a, and a P-type polycrystalline silicon layer 104a. The structure 108b has an N-type polycrystalline silicon layer 104b. N-type and P-type lightly doped drain (LDD) structures u0 are formed on the substrate, and silicon nitride spacers 112 are formed on the sides of the gate structures 108a and 108b, and the substrate 100 is continuously implanted. Step to complete the N-type and P-type source / drain regions 114 'and perform a rapid thermal process (RTP) at about 1000 ° C to activate the ions of the source / drain regions 114. As shown in FIG. 1C, the substrate 100 is then covered with an oxide layer, and the oxide layer is defined by forming a mask etch, so that the oxide layer 116 covers part of the substrate 100, and part of the oxide layer 116 is defined. The uncovered portion which is the logic circuit area 118a 'is defined as the memory area 118b. After that, a titanium metal layer is formed on the substrate 100, and then RTP is performed to make the titanium metal layer react with the exposed substrate 100, and a titanium silicide 120 is formed in the source / drain region 114 exposed in the logic circuit region 118a, as shown in FIG. 1D. As shown. 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (谙 Please read the notes on the back before filling this page) Θ $ 、 τ A7 B7 3356twf.d〇c / 〇〇6 5. Description of the invention (Most) In the above process, the purpose of forming tungsten silicide 106 is to increase the conductivity of the polycrystalline silicon layer 104. However, in the RTP process, due to the influence of high temperature, the impurities in the tungsten silicide layer 106 are added. _The larger the diffusion coefficient 'causes the double-gate structure 108a of the logic circuit region 118a, the N-type impurities in the polycrystalline silicon layer diffuse into the P-type polycrystalline silicon layer 104a via tungsten silicide 106, and the polycrystalline silicon The P-type impurity in the layer 104a〃 also diffuses into the N-type polycrystalline silicon layer 104a 'through tungsten silicide 106, and causes the so-called internal diffusion. The phenomenon' 22 'is shown in FIG. 2, and the internal diffusion phenomenon Will cause double gate failure. On the other hand, the definition step of tungsten silicide 106 / polycrystalline silicon layer 104 due to the formation of the gate structure is also difficult to define due to the presence of tungsten silicide. In view of this, one of the main objects of the present invention is to ensure the reliability of the device while avoiding the internal diffusion phenomenon in the double-gate structure. Another object of the present invention is to form an auto-aligned metal silicide on a gate of a logic circuit region, a gate of a source / drain region, and a gate of a memory region to increase the conductivity of the gate. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing an embedded dynamic random access memory to automatically align metallization. First, a complex crystal sand dual-gate structure is formed on a logic circuit region of a substrate. A gate structure is formed. After that, an insulating layer, a hard material layer, and a dielectric layer are sequentially formed on the substrate. Through the steps of back engraving, mask definition, and etching, the double gate structure of the logic circuit area, the gate structure of the source / drain area, and the memory area are exposed. After that, the double-gate structure of the logic circuit area was exposed. The 5-scale rule ’National Standards (CNS) of the 8th position (210X297). (Please read the precautions on the back before filling this page)
G 、τ 經米部中喪"'^-而員工消贽合作社印製 3356twf.doc/006 A7 B7 五、發明説明（γ) 與源/汲極區以及記憶體區之閘極結構上形成金屬砂化 物。因爲在金屬矽化物形成前，源/汲極區回火已先完成， 因此後續製程無高溫步驟，故不會引趄內擴散的現象，亦 無熱穩定度的問題。另外在邏輯電路區之雙閘極結構與源 /汲極區以及彳思體區之闊極結構上形成金屬砂化物則可 增加閘極之導電性。 爲議本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下\ 圖式之簡單說明： 第1A圖至第1D係顯示一種習知埋入式動態隨機存取 記憶體之製造流程剖面圖；以及 第2圖係顯示根據第1A圖雙閘極結構i〇8a與閘極結 構108b之jlL體圖，以及 第圖至第3G圖係顯不根據本發明較隹實施例之埋 入式動態隨機存取記憶體之製造流程剖面圖。 其中，各圖標號之簡單說明如下： 100、300 :基底 102、302 :閘極氧化物層 104、105、104a、104b :複晶矽層 106、106a、106b :砂化鎢 108a、304a :雙閘極結構 108b、304b :閘極結構 110、306 :淡摻雜汲極結構 6 本紙張尺度適州中國國家標準（CNS ) A4規格（210X297公釐） (誚先閲讀背面之注意事項再填寫本頁) οι 擎· 經於部中次榀準Λ只工消贽合竹杜印製 經濟部中央榀準而只-Χ消费合作妇印製 3356twf.doc/006 ηι B7 五、發明説明（f) 112、308 :間隙壁 114、310 :源/汲極區 116 :氧化物層 _ 120 :鈦砂化物 312、312a :絕緣層 314、314a、314b:硬材料層 316、316a、316b、316c :介電層 320 :金屬矽化物 實施例 ^ 習知之雙閘極結構，爲增加複晶矽閘極的導電性，而 在複晶矽層上提供一矽化鎢，然此不僅造成閘極結構定義 的困難，亦在後續有熱製程進行時，雙閘極複晶矽層的N 型與P型離子更藉著矽化鎢層互相擴散，引發內擴散現象 而導致元件失效。因此本發明係提供一種自動對準金屬矽 化物的製造方法，係在邏輯電路區的雙閘極、源/汲極區 與記憶體區之閘極上均形成金屬矽化物，以使複晶矽層閘 極導電性不需藉由矽化鎢而可增加，因此可避免習知內擴 散的現象，且因爲無須形成矽化鎢層，因此亦不會增加定 義製程的困難。 第3A圖至第3G圖所示，爲根據本發明一較佳實施例 埋入式DRAM自動對準金屬矽化物的製造流程剖面圖。請 參照第3A圖，在一具有淺溝渠隔離結構（STI)(未繪出）的 基底300上例如以熱氧化法形成一閘極氧化物層302，接 著對基底300形成一複晶矽層，包括以SiH4爲反應氣體之 7 本紙張尺度適用中國國家標隼（CNS ) A4规格（210X297公釐〉 (誚先閱讀背面之注意事項再填寫本頁) οί .裝.G and τ are described in the Ministry of Foreign Affairs " '^-and printed by the staff consumer cooperative 3356twf.doc / 006 A7 B7 5. Description of the invention (γ) is formed on the gate structure of the source / drain region and the memory region Metal sand. Because the source / drain region tempering has been completed before the metal silicide is formed, there is no high temperature step in the subsequent process, so it does not cause the phenomenon of internal diffusion and no thermal stability issues. In addition, the formation of metal sand on the double-gate structure of the logic circuit area and the wide-pole structure of the source / drain area and the body area can increase the gate conductivity. In order to discuss the above and other objects, features, and advantages of the present invention, it will be more obvious and easy to understand. 'A preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows. \ Brief description of the drawings: Figure 1A 1D is a sectional view showing a manufacturing process of a conventional embedded dynamic random access memory; and FIG. 2 is a block diagram showing a jlL body of a double-gate structure 108 and a gate structure 108b according to FIG. 1A. And FIGS. 3 to 3G are cross-sectional views showing the manufacturing process of the embedded dynamic random access memory according to the third embodiment of the present invention. Among them, a brief description of each icon number is as follows: 100, 300: substrate 102, 302: gate oxide layers 104, 105, 104a, 104b: polycrystalline silicon layers 106, 106a, 106b: sanded tungsten 108a, 304a: double Gate structure 108b, 304b: Gate structure 110, 306: Lightly doped drain structure 6 Paper size Shizhou Chinese National Standard (CNS) A4 specification (210X297 mm) (诮 Please read the precautions on the back before filling in this p) οι engine in part-time by the quasi-Pin Λ eliminate only work together bamboo Zhi Du Pin quasi-central Ministry of economic printed only -Χ consumer cooperative women printed 3356twf.doc / 006 ηι B7 V. description of the invention (f) 112, 308: spacers 114, 310: source / drain regions 116: oxide layer 120: titanium sand 312, 312a: insulating layers 314, 314a, 314b: hard material layers 316, 316a, 316b, 316c: dielectric Electrical layer 320: Example of a metal silicide ^ The conventional double-gate structure, in order to increase the conductivity of the polycrystalline silicon gate, provides a tungsten silicide on the polycrystalline silicon layer, but this not only causes difficulty in defining the gate structure Also in the subsequent thermal process, the N-type and P-type ions of the double-gate complex silicon layer are more preferably made of tungsten silicide. The layers diffuse to each other, causing internal diffusion and component failure. Therefore, the present invention provides a manufacturing method for automatically aligning metal silicide. Metal silicide is formed on the gates of the double gate, source / drain region, and memory region of the logic circuit region to make the polycrystalline silicon layer. The gate conductivity can be increased without using tungsten silicide, so the phenomenon of internal diffusion can be avoided, and because it is not necessary to form a tungsten silicide layer, it will not increase the difficulty of defining the process. Figures 3A to 3G are cross-sectional views showing the manufacturing process of an embedded DRAM auto-aligned metal silicide according to a preferred embodiment of the present invention. Referring to FIG. 3A, a gate oxide layer 302 is formed on a substrate 300 having a shallow trench isolation structure (STI) (not shown), for example, by a thermal oxidation method, and then a polycrystalline silicon layer is formed on the substrate 300. Includes 7 paper sizes with SiH4 as the reaction gas. Applicable to China National Standards (CNS) A4 specifications (210X297 mm) (诮 Please read the precautions on the back before filling this page).
、1T 3356twf.doc/006 A7 B7 經濟部中央极枣而只工消於合作社印製 五、發明説明（έ) 低壓化學氣相沉積法（LPCVD)進行。接著利用罩幕而分別 對複晶砍層進彳了 N型與P型離子之植入，並定義複晶石夕 層，而形成如第3A圖所示之雙閘極結第304a與閘極結構 304b。。之後，如習知技藝，對基底300進行植入步驟， 形成淡摻雜汲極結構306,續在雙閘極結構304a與閘極結 構304b側邊形成間矽壁308，例如對基底形成一氮化矽 層，再回蝕刻氮化矽層而形成。接著，再對基底300進行 植入的步驟，並經高溫回火（annea 1)製程，在基底300雙 閘極結構304a與閘極結構304b側邊形成源/極區310。 請參照第3B圖，對基底300形成一絕緣層312，例如 以化學氣相沉積法形成厚度約爲500-1000A的氧化物層， 接著’在絕緣層312上形成一硬材料層314,例如以LPCVD 或加強式電漿CVD(PECVD)形成氮化矽層或相似之硬材料 等。續在硬材料層314上形成一較厚的內介電層（inter-layer dielectric)316，包括形成磷矽玻璃（PSG)或硼磷 矽玻璃（BPSG)覆蓋在硬材料層316上，並進行化學機械硏 磨法（CMP)加以平坦化’或形成旋塗式玻璃（S〇G)之平坦化 介電層等。 之後，回蝕刻介電層316，去除部分介電層316，暴露 閘極區上的硬材料層，如第3C圖所示。接著，在部份基 底300上覆蓋一罩幕層（未繪出），例如爲光阻層，以微影 蝕刻技術定義介電層316a，並定義出邏輯電路區318a與 記億體區318b。其中，並續將邏輯電路區318a之介電層 316a去除，例如利用乾蝕刻法進行，以硬材料層爲蝕刻終 _ 8 本紙張尺度適州中國國家標準（CNS ) A4規格7 210*^7公酱） ' 一 (誚先閲讀背面之注意事項再填寫本頁) οι .装_ 訂 線 3356twf.doc/006 A7 ___________________^_____B7_____ 五、發明说明（7) 點’而使邏輯電路區318a之硬材料層314完全暴露出， 如第3D圖所示，記憶體區318b之介電層316b則因受罩 幕層保護而依舊存在。 接續進行的製程爲將第3D圖中暴露出的硬材料層314 去除’例如以蝕刻法去除，而暴露出邏輯電路區318a之 絕緣層312 ’且記憶體區318b亦暴露出部分的絕緣層 312，如第3E圖所示。之後，去除暴露出的絕緣層312， 則在邏輯電路區318a暴露出基底300之源/汲極區310與 複晶砍雙閘極結構304a，如第3F圖所示，另外記憶體區 318b亦暴露出複晶矽閘極3〇4b表面。由於絕緣層312a係 在沉積時精確控制厚度，因此在此步驟蝕刻進行時，亦可 精確控制鈾刻厚度，因此不致過度蝕刻絕緣層，而致使淺 溝渠隔離結構凹陷（recess)，影響元件效能》 接著’對基底300形成一金屬層，覆蓋基底300，再進 行高溫製程，使金屬層與暴露出之基底300與複晶矽層反 應’而在邏輯電路區318a之源/汲極區310與雙閘極結構 304a以及記憶體區318b之閘極304b形成自動對準金屬矽 化物320，如第3G圖所示。其中金屬層例如爲鈦金屬，則 金屬矽化物爲鈦矽化物。之後，則以習知技藝繼續進行製 作電容及所需製程。 本發明所形成的雙閘極結構係以複晶矽層形成，且源/ 汲極區之高溫回火在自動對準金屬矽化物形成前即已完 成，因此不會如習知技藝因高溫製程而導致雙閘極結構中 .內擴散的現象。且在邏輯電路區之源/汲極區與雙閘極以 9 本紙張尺度適W中國國家橾準（CNS ΓΑ4规格（21〇Χ297公釐> " (請先閲讀背面之注意事項再填寫本頁) .裝· 、?τ 3 3 5 6 tw f. d oc/0 0 6 A7 B7 五、發明説明（¾ ) 及記憶體區之閘極上皆形成金屬矽化物，因此可以降低閘 極之阻値，而記憶體區之源/汲極區未形成金屬矽化物亦 不會使漏電流過大。 ， 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) o' 裝., 1T 3356twf.doc / 006 A7 B7 Central Ministry of Economic Affairs, but only printed by the cooperative. V. Description of the invention (έ) Low pressure chemical vapor deposition (LPCVD). Then, using the mask, the N-type and P-type ions were implanted into the polycrystalline slicing layer, and the polycrystalline stone layer was defined to form a double-gate junction 304a and a gate as shown in FIG. 3A. Structure 304b. . After that, according to a known technique, an implantation step is performed on the substrate 300 to form a lightly doped drain structure 306, and an inter-silicon wall 308 is formed on the sides of the double gate structure 304a and the gate structure 304b, for example, a nitrogen is formed on the substrate. The silicon layer is formed, and then the silicon nitride layer is etched back. Next, a step of implanting the substrate 300 is performed, and a source / electrode region 310 is formed on the sides of the double gate structure 304a and the gate structure 304b of the substrate 300 through a high temperature tempering (annea 1) process. Referring to FIG. 3B, an insulating layer 312 is formed on the substrate 300, for example, an oxide layer having a thickness of about 500-1000 A is formed by a chemical vapor deposition method, and then a hard material layer 314 is formed on the insulating layer 312, such as LPCVD or enhanced plasma CVD (PECVD) forms a silicon nitride layer or similar hard material. Continue to form a thicker inter-layer dielectric 316 on the hard material layer 314, including forming a phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) to cover the hard material layer 316, and perform Planarization by chemical mechanical honing (CMP) or formation of a planarized dielectric layer of spin-on glass (SOG). After that, the dielectric layer 316 is etched back, a part of the dielectric layer 316 is removed, and the hard material layer on the gate region is exposed, as shown in FIG. 3C. Next, a part of the substrate 300 is covered with a mask layer (not shown), such as a photoresist layer. The dielectric layer 316a is defined by a lithographic etching technique, and a logic circuit area 318a and a memory body area 318b are defined. Among them, the dielectric layer 316a of the logic circuit area 318a is continuously removed, for example, using a dry etching method, and the hard material layer is used as the etching end. 8 This paper is a Chinese standard (CNS) A4 size 7 210 * ^ 7. (Public sauce) 'One (诮 Please read the precautions on the back before filling this page) οι. Install _ order line 3356twf.doc / 006 A7 ___________________ ^ _____ B7_____ V. Description of the invention (7) Point' makes the logic circuit area 318a hard The material layer 314 is completely exposed. As shown in FIG. 3D, the dielectric layer 316b of the memory region 318b is still present because it is protected by the cover layer. The subsequent process is to remove the hard material layer 314 exposed in the 3D image, for example, by etching, and to expose the insulating layer 312 of the logic circuit region 318a and the memory region 318b to expose a part of the insulating layer 312. As shown in Figure 3E. After that, the exposed insulating layer 312 is removed, and the source / drain region 310 of the substrate 300 and the dual-crystal bi-gate structure 304a are exposed in the logic circuit region 318a, as shown in FIG. 3F, and the memory region 318b is also The surface of the polycrystalline silicon gate 304b was exposed. Because the thickness of the insulating layer 312a is precisely controlled during deposition, the thickness of the uranium can also be precisely controlled during the etching process at this step, so that the insulating layer will not be over-etched, and the shallow trench isolation structure will be recessed, which will affect the efficiency of the device. " Next, 'form a metal layer on the substrate 300, cover the substrate 300, and then perform a high-temperature process to make the metal layer and the exposed substrate 300 react with the polycrystalline silicon layer'. In the source / drain region 310 and the dual region of the logic circuit region 318a, The gate structure 304a and the gate 304b of the memory region 318b form an auto-aligned metal silicide 320, as shown in FIG. 3G. Wherein the metal layer is titanium, for example, the metal silicide is titanium silicide. After that, the capacitor manufacturing process and the required process are continued with the conventional techniques. The double-gate structure formed by the present invention is formed by a polycrystalline silicon layer, and the high-temperature tempering of the source / drain region is completed before the automatic alignment of the metal silicide is formed, so it will not be caused by the high-temperature process as is known in the art. This leads to the phenomenon of internal diffusion in the double-gate structure. And in the logic circuit area, the source / drain area and the double gate are suitable for the Chinese national standard (CNS ΓΑ4 size (21〇 × 297mm) > " (Please read the precautions on the back before filling in (This page). Installation,? Τ 3 3 5 6 tw f. D oc / 0 0 6 A7 B7 V. Description of the invention (¾) and metal silicide are formed on the gate of the memory area, so the gate can be reduced. Resistance, and no metal silicide is formed in the source / drain region of the memory region and the leakage current will not be too large. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any Those skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the back first (Please fill in this page again).
、1T 經淨-部中央樣牟而只工消贽合作社卬？衣 10 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）、 1T Jingjing-Ministry Central Committee only works to eliminate consumer cooperatives? Clothing 10 This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm)