445831 A7 B7 經滴部中央摞準局負工消费合作社印來 五、發明説明（1) 本發明係有關於一種半導體裝置的製造方法，特別 是在同一晶片（Chip)上混合設置有記憶體裝置（meIn〇ry device)以及邏輯裝置（l〇gic device)的埋入式半導體記憶 體裝置（embedded semiconductor memory device)的製造方 法。 習知將邏輯裝置與記憶裝置分別被形成於不同的晶 片’然後再設置於同一板上。然後形成於不同晶片的記 憶裝置與邏輯裝置的構造，無法確保其高速性，因此， 有一種將記憶裝置與邏輯裝置混合設置於同一晶片上的 裝置被提出’此種裝置亦即所謂的埋入式半導體記憶裝 置’例如 eRAM(embedded Random Access Memory)裝置 。上述eRAM裝置常將邏輯裝置電晶體之閘極氧化層變 ί專’以提昇電晶體之驅動能力，然而，在記憶裝置的電 晶體則需要形成較厚的閘極氧化層。故此種eRAM需要 雙閘極氧化層（dual gate oxide)，亦即，厚度不同的閘極 氧化層。 ~ 習知形成雙閘極氧化層之裝置的方法，例如在半導 體基底上形成隔離元件。然後，形成薄閘極氧化層，並 且在邏輯裝置的區域形成覆蓋薄閘極氧化層的光阻層， 然後，以該光阻層為罩幕，去除邏輯裝置區域以外的區 域（記憶裝置區域）之薄閘極氧化層，然後，去除上述光阻 層，接著，再於記憶體裝置區域形成一厚閘極氧化層。 然而，囟為上述光阻層直接與薄氧化層接觸，所以 光阻層中所含的各種不純物（例如金屬不純物）會擴散至 本紙張尺度通用中國國家標準（CNS ) A4規格（210X 297公釐） (讀先閱讀背面之注意事項再填寫本頁) ,π ^! 445631 經潢部中央榡率局貝Η消费合作社印製 A7 五、發明説明（2 ) ' ---- ’並且在剝除光阻層時，亦會損壞閘極氧 化層，而戚重影響薄閉極氧化層的可靠度。 有鑑於此’本發明的目的在於提供—種整合雙閑極 氧化層7G件的製造方法’可成功地整合記憶裝置以及邏 輯裝置之雙閉極氧化層製程，而且光阻層不與開極氧化 層直接接觸，而可確保_氧化層的可靠度。 —根據上述目的’本發明提出—種整合雙閘極氧化層 件的Ilk方法’包括下列步驟：⑷提供—半導體基底 該半導體基底形成有用以隔離邏輯區域與記憶體單元 區域的隔離元件；（b)在上述半導體基底全面性依序形成 -第1閘極氧化層、-第！複晶㈣、以及'絕緣氧化 層’其中該第1閘極氧化層具有第j厚度；(c)去除上述 記憶體單元區域的絕緣氧化層、第丨複晶矽層第以及第】 閘極氧化層，直到露出上述半導體基底為止；⑷在上述 記憶體單元區域的半導體基底表面形成一第2閘極氧化 層，該第2閘極氧化層具有第2厚度；（e)在上述記憶體 單元區域的第2閘極氧化層上以及上述邏輯區域的絕緣 氧化層上依序形成一第2複晶矽層以及一罩幕層（氮化矽 層）；（f)施以非等向性蝕刻法，用以選擇性去除該罩幕層 (氮化矽層）、該第2複晶矽層以及該第2閘極氧化層而形 成上述記憶體單元區域的閘極電極，並且在邏輯區域露 出3亥絕緣氧化層，（g)選擇性触刻上述邏輯區域的絕緣氧 化層、以及第1複晶矽層’而形成上述邏輯區域的閘極 電極；（h)進行LDD離子植入步驟：⑴同時在上述記憶艘 本紙張尺度通用中國國家揉準（CNS ) A4規格（210X297公釐）445831 A7 B7 Printed by the Central Laboratories and Consumers' Cooperatives of the Ministry of Div. 5. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor device, especially a memory device mixedly provided on the same chip. A method of manufacturing an embedded semiconductor memory device (meInry device) and a logic device (10gic device). It is known that the logic device and the memory device are respectively formed on different wafers' and then set on the same board. The structure of the memory device and the logic device formed on different chips cannot ensure its high speed. Therefore, a device that mixes the memory device and the logic device on the same chip has been proposed. 'This kind of device is also called embedding. For example, an eRAM (embedded random access memory) device. The above eRAM device often changes the gate oxide layer of the transistor of the logic device to improve the driving ability of the transistor. However, the transistor of the memory device needs to form a thicker gate oxide layer. Therefore, this type of eRAM requires dual gate oxide, that is, gate oxides with different thicknesses. ~ A method for forming a double-gate oxide layer is known, such as forming an isolation element on a semiconductor substrate. Then, a thin gate oxide layer is formed, and a photoresist layer covering the thin gate oxide layer is formed in a region of the logic device. Then, using the photoresist layer as a mask, a region other than the logic device region (memory device region) is removed. Thin gate oxide layer, then remove the photoresist layer, and then form a thick gate oxide layer in the memory device area. However, 囟 is that the above photoresist layer is in direct contact with the thin oxide layer, so various impurities (such as metal impurities) contained in the photoresist layer will diffuse to this paper standard Common Chinese National Standard (CNS) A4 specification (210X 297 mm) ) (Read the notes on the back before you fill out this page), π ^! 445631 Printed by A7 of the Ministry of Economic Affairs, Central Bureau of Economic Affairs, Beiya Consumer Cooperatives, A7. 5. Description of Invention (2) '----' When the photoresist layer is used, the gate oxide layer will also be damaged, and the reliability of the thin closed electrode layer will be greatly affected. In view of this, the object of the present invention is to provide a method for manufacturing a 7G component with integrated double-pole oxide layer, which can successfully integrate the double-closed oxide layer process of the memory device and the logic device, and the photoresist layer is not oxidized with the open-electrode layer. The layer is in direct contact, which can ensure the reliability of the oxide layer. -According to the above-mentioned object 'proposed by the present invention-an Ilk method for integrating a double-gate oxide layer member' includes the following steps: ⑷ providing-a semiconductor substrate which forms an isolation element useful for isolating a logic region from a memory cell region; (b ) The first semiconductor oxide layer is formed on the above-mentioned semiconductor substrate in a comprehensive manner-the first! The polycrystalline silicon and the "insulating oxide layer" wherein the first gate oxide layer has a j-th thickness; (c) removing the insulating oxide layer, the first and second silicon layers of the memory cell region, and the gate oxide Layer until the semiconductor substrate is exposed; 形成 forming a second gate oxide layer on the surface of the semiconductor substrate in the memory cell region, the second gate oxide layer having a second thickness; (e) in the memory cell region A second polycrystalline silicon layer and a mask layer (silicon nitride layer) are sequentially formed on the second gate oxide layer and the insulating oxide layer of the logic region; (f) applying anisotropic etching For selectively removing the mask layer (silicon nitride layer), the second polycrystalline silicon layer, and the second gate oxide layer to form a gate electrode in the above-mentioned memory cell region, and expose 3 in the logic region The insulating oxide layer (g) selectively touches the insulating oxide layer of the logic region and the first polycrystalline silicon layer to form the gate electrode of the logic region; (h) performing the LDD ion implantation step: ⑴ simultaneously In the memory of the above paper China National rubbing quasi (CNS) A4 size (210X297 mm)
(誚先聞讀背面之注意事項再填寫本頁J -訂 ^! 4 4 5 6 3 1 經满部中央標隼局員工消費合作社印聚 A7 B7 五、發明説明（3) 單元區域以及邏輯區域的閘極電極的侧壁形成一侧壁絕 緣層（氮化矽層）；（j)選擇性施以離子植入步驟，用以在邏 輯區域閘極電極兩侧的半導體基底表面形成源極/汲極 以及植入離丰於閘極電極（分別植入N+型離子於NM〇s 閘極並且植入P+型離子於PM〇s閘極）；（k)全面性形成一 阻抗保護氧化層（RP0);以及⑴去除上述邏輯區域的阻抗 保護氧化層，並且在上述邏輯區域該閘極電極以及該源 極/汲極表面形成一金屬矽化合物層。 為了讓本發明之上述目的、特徵 '和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖〜第8圖為本發明實施例之半導體裝置的製程 剖面圖。 符號之說明 10〜半導體基底；12〜第1閘極氧化層；14〜第1複 晶石夕層，16絕緣氧化層；18〜光阻層；2〇〜第2閛極氧 化層，22〜第2複晶妙層（摻雜n型離子之複晶石夕層）； 24〜金屬複晶矽化合物（例如欽化鎢）；26〜緩衝氧化層； 28~氮化碎層（亦即罩幕層）；30〜光阻層；32〜記憶體單 元區域之淺摻雜源極/汲極（LDD); 34〜光阻層；36、38 、40〜氮化矽側壁絕緣層；42〜p型離子摻雜區；44〜N 型離子摻雜區；46〜阻抗保護氧化層；48〜光阻層；50〜 金屬矽化合物層。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐> (讀先閱讀背面之注意事項再填寫本頁)(诮 Please read the notes on the back before filling in this page. J -Order ^! 4 4 5 6 3 1 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards and Printing A7 B7 V. Description of the invention (3) Unit area and logic area A sidewall insulation layer (silicon nitride layer) is formed on the sidewall of the gate electrode; (j) an ion implantation step is selectively performed to form a source / surface on the surface of the semiconductor substrate on both sides of the gate electrode in the logic region; The drain electrode and the implanted ion gate electrode (N + type ions are implanted in the NM0s gate and P + type ions are implanted in the PM0s gate, respectively); (k) an impedance protective oxide layer is formed comprehensively ( RP0); and ⑴ remove the impedance protection oxide layer in the logic region, and form a metal silicon compound layer on the surface of the gate electrode and the source / drain electrode in the logic region. In order to make the above-mentioned objects and features of the present invention, and The advantages can be more obvious and easy to understand. A preferred embodiment will be given below in conjunction with the accompanying drawings to make a detailed description as follows: A brief description of the drawings: FIG. 1 to FIG. 8 are semiconductor devices according to an embodiment of the present invention. Sectional view of manufacturing process. Explanation of symbols 10 ~ Conductor substrate; 12 ~ 1 gate oxide layer; 14 ~ 1 polycrystalline stone layer, 16 insulating oxide layer; 18 ~ photoresist layer; 20 ~ 2th anodic oxide layer, 22 ~ 2 complex crystal Layer (doped spar layer with n-type ions); 24 ~ metal polycrystalline silicon compound (such as tungsten tungsten); 26 ~ buffer oxide layer; 28 ~ nitrided layer (ie mask layer); 30 ~ Photoresist layer; 32 ~ shallow doped source / drain (LDD) of memory cell area; 34 ~ photoresist layer; 36, 38, 40 ~ silicon nitride sidewall insulation layer; 42 ~ p type ion doping Area; 44 ~ N-type ion doped area; 46 ~ resistance protective oxide layer; 48 ~ photoresist layer; 50 ~ metal silicon compound layer. This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm >) (Read the precautions on the back before filling this page)
,1T -^丨. A7 445631 五、發明説明（4) 實施例 以下利用第1圖至第8圖之製程剖面圖，以說明本 發明較佳實施例。 首先’請參照第1圖’提供一半導體基底1〇，其已 形成有用以隔離邏輯區域（logic region)以及記憶體單元 區域（memory cell region)的淺溝槽隔離元件Ila(shaU〇w trenchisolation ; STI)，並且在邏輯區域亦形成有後續用 以隔離元件的隔離元件lib ^接著，利用熱氧化法在存 在氧氣的環境下’於半導體基底表面形成厚度介於 20〜200 A的第1閘極氧化層12、然後利用化學氣相沈 積法（CVD)形成厚度介於500〜3000 A的第1複晶石夕層14 ’例如為未摻雜離子之複晶矽層，並且形成一厚度介於 100〜200 A的絕緣氧化層16。緊接著，利用微影製程 (photolithography)形成一覆蓋邏輯區域的光阻層18。 接著，請參照第2圖，以上述光阻層18為蝕刻罩幕 ’利用非等向性蝕刻法（aniS〇tr〇pic etching)去除記憶體 單元區域的絕緣氧化層16、第i複晶矽層14、以及第i 閘極氧化層12，直到露出半導體基底1〇的表面為止。 其次，請參照第3圖，去除上述光阻層18 ^接著， 在上述記憶體單元區域的半導體基底1〇表面形成—厚度 介於20〜200 A的第2閘極氧化層20，本實施例的第2 閘極氧化層20的厚度大於上述第！閘極氧化層12。但是 ，第2閘極氧化層20亦可能小於第1閘極氧化層12。然 後，利用同步（in-situ)摻雜N型離子之化學氣相沈積法， 私紙張尺度適用中關家標準（CNS) M規格（21t)x29?公整 (讀先聞讀背面之注意事項再填寫本頁), 1T-^ 丨. A7 445631 V. Description of the invention (4) Examples The following uses the process sectional views of Figs. 1 to 8 to illustrate the preferred embodiment of the present invention. First, please refer to FIG. 1 to provide a semiconductor substrate 10, which has been formed with a shallow trench isolation element Ila (shaU0w trenchisolation) for isolating a logic region and a memory cell region; STI), and a subsequent isolation element lib is formed in the logic region to isolate the element. Then, a first gate electrode with a thickness of 20 to 200 A is formed on the surface of the semiconductor substrate by using a thermal oxidation method in the presence of oxygen. The oxide layer 12 is then chemically vapor-deposited (CVD) to form a first polycrystalline stone layer 14 ′ having a thickness of 500 to 3000 A, for example, a polycrystalline silicon layer not doped with ions, and forming a thickness between 100 ~ 200 A of insulating oxide layer 16. Next, a photolithography process is used to form a photoresist layer 18 covering the logic area. Next, referring to FIG. 2, the photoresist layer 18 is used as an etching mask, and the insulating oxide layer 16 and the i-th polycrystalline silicon in the memory cell region are removed by using anisotropic etching (anisotropic etching). The layer 14 and the i-th gate oxide layer 12 are exposed until the surface of the semiconductor substrate 10 is exposed. Next, referring to FIG. 3, the photoresist layer 18 is removed. Next, a second gate oxide layer 20 having a thickness of 20 to 200 A is formed on the surface of the semiconductor substrate 10 in the memory cell region. In this embodiment, The thickness of the second gate oxide layer 20 is larger than the above! Gate gate oxide layer 12. However, the second gate oxide layer 20 may be smaller than the first gate oxide layer 12. Then, using the in-situ chemical vapor deposition method of doping N-type ions, the private paper size applies the Zhongguanjia Standard (CNS) M specification (21t) x 29? (Fill in this page again)
、1T 經满部中央梯準扃負工消費合作社印紫 經滴部中央標率局貝工消費合作社印製 445 63 1 A7 ____^___ 五、發明説明（5) 全面性形成一厚度介於500〜3000 A的第2複晶矽層22 ，亦即，在邏輯區域以及記憶體單元區域皆形成第2複 晶矽層22。然後，在第2複晶矽層22上方形成一厚度介 於500〜3〇00 A的金屬複晶矽化合物層24，其例如為妙 化鎢（tungsten silicide)層。上述在複晶矽層上形成金屬石夕 化物之製程亦即通稱之金屬複晶矽化物（Policide)製程。 然後，形成一厚度介於100〜2000 A的氧化緩衝層（buffer 〇xide)26 ’以及一氮化矽層28，其中氧化緩衝層26的目 的在於增加氮化矽層28的黏合度，以防止氮化矽層28 的剝落。再者’利用微影製程，在記憶體單元區域形成 一光阻層30。 然後，請參照第3圖以及第4圖，利用光阻層30為 蝕刻罩幕’且利用非等向性蝕刻法去除未被光阻層3〇覆 蓋的氮化矽層28、緩衝氧化層26、金屬複晶矽化合物 層24、第2複晶矽層22、以及第2閘極氧化層20，用 以在記憶體單元區域形成閘極電極GE，而在邏輯區域露 出絕緣氧化層16表面。接著，去除光阻層30。然後， 施以離子植入法，用以在摻雜N型離子之閘極電極GE 的兩側之半導體基底1〇表面形成淺摻雜源極/汲極 (LDD)32 ’上述植入離子步驟，可植入例如磷之N型離 子。另外’亦可視需要在記憶體單元區域之特定位置植 入硼等p型離子’以得到埋入式通道（burid channel)之 PM0S電晶體（圖未顯示）β 接下來’請參照第5圖，利用微影製程形成光阻層 ___ 7 本紙張尺度㈣中關家標率丨CNSy^4^ (2iQx 297公爱） ' - (請先閱讀背面之注意事項再填寫本Fc 訂 A7 445631 五、發明説明（6) 34，其覆蓋整個記憶體單元區域，並覆蓋部分邏輯區域 之絕緣氧化層16的表面。 然後，請參照第5圖以及第6圖，以光阻層34為蝕 刻罩幕’而施以非等向性蝕刻法’蝕刻邏輯區域未被光 阻層34覆蓋的絕緣氧化層16、第i複晶矽層14、以及 第Ϊ閘極氧化層12 ’用以形成邏輯區域的閘極電極G1 、G2。接著’進行分別在閘極電極gi以及G2兩側進行 P型以及N型之LDD離子摻雜（圖未顯示）然後，去除 光阻層34。 其次’ s奢參照第7圖，去除邏輯區域的絕緣氧化層 16。然後’同時在記憶體單元區域的閘極電極ge，以 及邏輯區域的閘極電極Gl、G2的側壁形成側壁絕緣層 36、38、40，本實施例係採用氮化矽材料當作側壁絕 緣層。上述a己憶體單元區域以氮化梦材料構成之側壁絕 緣層36，以及閘極電極GE上方之氮化矽層28，是用以 整合後續自我對準接觸窗（扣1卜&1丨61^(；0价似；从(：）製 程，當作後續姓刻氧化層（圖未顯示）以形成接觸窗之飯刻 停止層。 然後’植入Ρ型離子於閘極電極G1以及閘極電極 G1的兩側，使閘極電極G1摻入離子，並且使閘極電極 G1兩側之半導體基底1 〇表面形成一 ρ型摻雜源極/汲極 42 ’而得到一表面通道（surface charmel)PMOS電晶體。 接著’植入例如坤之N型離子於閘極電極G2以及閘極電 極G2的兩側，使閘極電極G2掺入離子，並且使閘極電 8 本紙乐尺度適用中國國家標準（CNS) A4規格（2〗〇Χ 297公釐） (讀先閱讀背面之注意事項再填寫本頁〕 -訂 經滴部中央掠準局貝工消費合作社印絜 445631 A7 經滴部中央標準局貝工消費合作社印製 ___ B7五、發明説明（7) 極G2兩側之半導體基底1 〇表面形成一 n型摻雜源極/；：及 極44。接著，利用化學氣相沈積法’形成一阻抗保護氧 化層（resist protect oxide ; RPO)46。然後，利用微影製 程以形成覆蓋記憶體單元區域的光阻層48。 最後’請參照第7圖以及第8圖，以上述光阻層4 8 為蝕刻罩幕，而去除邏輯區域的阻抗保護氧化層46，然 後’在邏輯區域施以一自我對準金屬矽化物（self_al丨gned silicide ; salicide)程序，用以在閘極電極οι、G2以及 源極Λ及極42、44的上表面形成一金屬妙化合物層5〇， 而形成金屬矽化合物層50的方法例如先濺鍍一層鈦層 (Ti)，然後’施以高溫熱處理，而形成鈦化矽層（Tisi2)， 另外’亦可利用姑代替欽。然後’去除光阻層48，以形 成雙閘極氧化層的半導體記憶裝置。 發明效果 根據本發明之製造方法’以較低成本的方式成功地 整合雙閘極氧化層之半導體裝置的製程。 再者，根據本發明之製造方法，不致因光阻層直接 覆蓋於閘極氧化層，而破壞閘極氧化層的可靠度。 而且，根據本發明之製造方法，不需額外增加光罩 數目亦可依記憶體單元區域以及邏輯區域的需要，而分 別形成上述兩區域的源極/汲極。 再者，根據本發明之製造方法，不需額外增加光罩 的數目’亦可整合邏輯區域之自我對準矽化物（Sancide) 製程（自我對準金屬矽化物層50)以及記憶體單元區域之 __ 9 氏法尺度適用中國國家標率{ CNS ) A4規格（210X297公釐） !,it------妗，- {諳先閲讀背面之注意事項再禎寫本頁) 445 63 1 A7 _______ B7_________ 五、發明説明（8) 複晶矽化物（Polycide)製程（金屬複晶矽化合物層24)。 再者，可有效地整合不同厚度閘極氡化層（邏輯區域 之第1閘極氧化層12、以及記憶體單元區域之第2閘極 氧化層20)之電晶體構造。並可整合後續自我對準接觸窗 製程。提供表面通道PMOS電晶體（閘極電極G1以及）以 及埋入式通道PM0S電晶體（記憶體單元區域）於同一晶 片上。並且由於邏輯區域以及記憶體單元區域可在不同 步驟植入LDD，故對於LDD離子植入，提供較彈性的選 擇（亦即可選#植入或不植入LDD)，而不需額外的光罩 ’亦可在5己憶體單元區域的閘極電極GE兩側植入例如 鱗專離子，而在邏輯區域的閘極電極G 2植入例如珅等離 子。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此項技藝者，在不脫離本發明 之精神和範圍内，當可作更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 —^n - ί^— I-I In ^ i^i —^ϋ If-. - -- - ' 一 - · (讀先閱讀背面之注意事項再填寫本頁〕 te濟部中央標準局貝工消費合作社印w 10 本紙張尺度適用中國國家標準（CNS )A4規梢2丨0X297公釐）、 1T printed by the Central Ladder of the Central Ladder Consumers Cooperative Cooperative, printed by the Central Standards Bureau of the Ministry of Standards, printed by the Shell Consumer Cooperative, 445 63 1 A7 ____ ^ ___ 5. Description of the invention (5) Comprehensively formed a thickness of 500 The second polycrystalline silicon layer 22 of ~ 3000 A, that is, the second polycrystalline silicon layer 22 is formed in both the logic region and the memory cell region. Then, a metal polycrystalline silicon compound layer 24 having a thickness of 500 to 3,000 A is formed over the second polycrystalline silicon layer 22, which is, for example, a tungsten silicide layer. The above-mentioned process for forming a metal oxide on a polycrystalline silicon layer is also referred to as a metal polysilicide (Policide) process. Then, an oxide buffer layer 26 ′ and a silicon nitride layer 28 with a thickness of 100˜2000 A are formed. The purpose of the oxide buffer layer 26 is to increase the adhesion of the silicon nitride layer 28 to prevent Exfoliation of the silicon nitride layer 28. Furthermore, a photoresist layer 30 is formed in the memory cell region by a lithography process. Then, referring to FIGS. 3 and 4, the photoresist layer 30 is used as an etching mask, and the silicon nitride layer 28 and the buffer oxide layer 26 not covered by the photoresist layer 30 are removed by an anisotropic etching method. The metal polycrystalline silicon compound layer 24, the second polycrystalline silicon layer 22, and the second gate oxide layer 20 are used to form a gate electrode GE in the memory cell region, and expose the surface of the insulating oxide layer 16 in the logic region. Next, the photoresist layer 30 is removed. Then, an ion implantation method is applied to form a shallow doped source / drain (LDD) 32 on the surface of the semiconductor substrate 10 on both sides of the gate electrode GE doped with N-type ions. Can be implanted with N-type ions such as phosphorus. In addition, 'P-type ions such as boron may also be implanted at specific positions in the memory cell area as needed' to obtain a PM0S transistor (burst channel) of the buried channel (not shown) β. Next, please refer to Figure 5, Photoresist layer formed using photolithography process ___ 7 This paper size ㈣ Zhongguan standard rate 丨 CNSy ^ 4 ^ (2iQx 297 public love) '-(Please read the precautions on the back before filling in this Fc Order A7 445631 V. Description of the invention (6) 34, which covers the entire memory cell area and covers the surface of the insulating oxide layer 16 of the logic area. Then, referring to FIG. 5 and FIG. 6, the photoresist layer 34 is used as an etching mask. Anisotropic etching is used to etch the insulating oxide layer 16, the i-th compound silicon layer 14, and the third gate oxide layer 12 that are not covered by the photoresist layer 34 in the logic region to form the gate electrode of the logic region. G1 and G2. Then, perform PDD and N-type LDD ion doping (not shown) on both sides of the gate electrode gi and G2, respectively, and then remove the photoresist layer 34. Secondly, referring to FIG. 7, Remove the insulating oxide layer 16 of the logic area. Then 'same The sidewall insulation layers 36, 38, and 40 are formed on the sidewalls of the gate electrode ge in the memory cell region and the gate electrodes G1 and G2 in the logic region. In this embodiment, a silicon nitride material is used as the sidewall insulation layer. The memory cell region is composed of a sidewall insulation layer 36 made of a nitride nitride material, and a silicon nitride layer 28 above the gate electrode GE, which are used to integrate subsequent self-aligned contact windows (button 1bu & 1 丨 61 ^ (; 0 valence is similar; from the (:) process, it is used as a subsequent etched oxide layer (not shown in the figure) to form a contact carved window stop layer. Then, P-type ions are implanted into the gate electrode G1 and the gate electrode On both sides of G1, the gate electrode G1 is doped with ions, and a surface of the semiconductor substrate 10 on both sides of the gate electrode G1 forms a p-type doped source / drain 42 ′ to obtain a surface charmel. PMOS transistor. Then 'implant, for example, Kun's N-type ions on the gate electrode G2 and both sides of the gate electrode G2, so that the gate electrode G2 is doped with ions, and the gate electrode is applied to the Chinese national standard. (CNS) A4 specifications (2〗 〇〇 297mm) (read first Note on the back, please fill in this page again]-Ordered by the Dibei Central Bureau of Standards and Accreditation of the Shellfish Consumer Cooperative Co., Ltd. 445631 A7 Printed by the Dibei Central Standards Bureau of the Division of Shellfish Consumer Cooperatives ___ B7 V. Description of the Invention (7) Pole G2 An n-type doped source /; is formed on the surfaces of the semiconductor substrates 10 on both sides, and the electrode 44. Then, a chemical vapor deposition method is used to form a resist protect oxide (RPO) 46. Then, using A lithography process is performed to form a photoresist layer 48 covering the memory cell area. Finally, please refer to FIG. 7 and FIG. 8, using the photoresist layer 4 8 as an etching mask, and remove the impedance protection oxide layer 46 in the logic area, and then apply a self-aligned metal silicide in the logic area ( self_al 丨 gned silicide; salicide) program for forming a metal compound layer 50 on the upper surfaces of the gate electrodes ο, G2, and the source electrodes Λ and 42, 42, and the method of forming the metal silicon compound layer 50 is, for example, first A layer of titanium (Ti) is sputtered, and then a high temperature heat treatment is performed to form a silicon titanium layer (Tisi2). In addition, a gu can be used instead of Chin. The photoresist layer 48 is then removed to form a semiconductor memory device with a double gate oxide layer. ADVANTAGE OF THE INVENTION According to the manufacturing method of the present invention ', a process for successfully integrating a semiconductor device with a double gate oxide layer in a lower cost manner is successfully integrated. Furthermore, according to the manufacturing method of the present invention, the reliability of the gate oxide layer is not damaged because the photoresist layer directly covers the gate oxide layer. In addition, according to the manufacturing method of the present invention, the source / drain of the above two regions can be formed separately according to the needs of the memory cell region and the logic region without additional number of photomasks. Furthermore, according to the manufacturing method of the present invention, the number of photomasks does not need to be increased, and the self-aligned silicide (Sancide) process (self-aligned metal silicide layer 50) of the logic region and the memory cell region can be integrated. __ 9 Applicable to China ’s national standard {CNS) A4 standard (210X297 mm) !, it ------ 妗,-{谙 Please read the notes on the back before writing this page) 445 63 1 A7 _______ B7_________ V. Description of the invention (8) Polycide process (metal polycrystalline silicon compound layer 24). Furthermore, the transistor structures of different gate thicknesses (the first gate oxide layer 12 in the logic region and the second gate oxide layer 20 in the memory cell region) can be effectively integrated. And can integrate subsequent self-aligned contact window process. A surface channel PMOS transistor (gate electrode G1 and) and a buried channel PM0S transistor (memory cell area) are provided on the same wafer. And because the logic region and the memory cell region can be implanted with LDD in different steps, it provides a more flexible choice for LDD ion implantation (that is, optional #implantation or non-implantation of LDD) without additional light. The mask can also be implanted with, for example, scaly ions on both sides of the gate electrode GE in the body region, and the gate electrode G 2 in the logic region can be implanted with, for example, tritium plasma. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. — ^ N-ί ^ — II In ^ i ^ i — ^ ϋ If-.---'一-· (Read the precautions on the back before filling this page] teBeijing Consumer Products Cooperative, Central Bureau of Standards, Ministry of Economic Affairs Print w 10 This paper size is applicable to China National Standard (CNS) A4 gauge 2 丨 0X297 mm)