經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 ) 本發明係有關於半導體記憶元件的製造，且特別是 有關於一種適用於半導體記憶元件之星型台座式（pedestal ........ ........ . . ----------- —- — ·*— type)儲存電容器構造及其製造方法纟其儲存電極包含一星 ........... .......... : 二.· . 型台座，是由一軸心部分和複數個呈放射狀展開的翼狀部 分所構成，可增加電極表面積而提高其電容量。 動態隨機存取記憶體(DRAM)是一種廣泛應用的積體 電路元件’尤其在今日資訊_子產業中更佔有極重要的地 位。隨著製程技術的演進，目前生產線上常見的動態隨機 存取記憶單元（memory cell)大多是由一電晶體和一儲存電 容器所構成《基本上，電晶體的源極係連接到一對應的位 元線(bit line)，汲極連接到儲存電容器的儲存電極（storage Plate) ’而閘極則連接到一對應的字元線(vvord line)，儲存 電容器的相對電極（0pp0site . plate)係連接到一固定電壓 源’而在儲存電極和相對電極之間則設置一介電質層。 尚度積集化的DRAM，例如大於一千六百萬位元（16M) 的儲存容量者’通常利用三度空間結構的儲存電容器來實 現’例如所謂的溝槽式（trench_type)或疊層式（stack_type) 電谷器S己憶元件。其中，由於前者在截刻溝槽時不可避免 地使基底產生晶格缺陷（defects)，造成漏電流機會的增加 而影響元件性質，並且隨著溝槽縱橫比（aspect ratio)的增 大’其蚀刻速率亦將遞減，不僅製程困難且影響了生產效 率’因此實際生產線上此類溝槽型電容器製程並不普遍。 相反地’疊層式電容器記憶元件的製程則則不會有上述缺 點’因此是目前生產線上普遍採用的技術。 不.浓㈣π關轉準（CNS)A4規格（·χ297公着） ---------一衣------1T------· - (請先聞填背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（2 ) 傳統的疊層式電容器稱為平台式電容器，如第1圖 所示者即為一例’其製造流程主要包含形成電晶體和形成 儲存電容器兩個部分。首先，於一半導體基底10，例如 是一矽晶圓上形成一場氧化層（field oxide layer)ll以界定 出元件區（active region)。接著依序形成一閘氧化層12、 一導電層13、及一遮蔽層14，並以微影成像 (microlithography)和蝕刻程序定義圖案，形成一閘極構 造。利用此閘極構造當作罩幕，佈植雜質進入半導體基底 10中，以形成一對淡摻植（lightly doped)源極區15a和汲 極區15b。然後，在閘極構造的侧壁上以沈積和回蝕刻程 序形成一絕緣側壁層（spacer)16，再以閘極構造和絕緣側 壁層16當作罩幕，佈植較高濃度的雜質進入半導體基底 1〇中，以形成一對源極區17a和汲極區17b，完成一電晶 體的製作。 一接著，進行儲存電容器的製作。先沈積—絕緣層（未 顯示）’例如是一硼磷矽玻璃（BPSG)層，覆蓋在前述電晶 體疋件的表面上，並以微影成像和蝕刻程序在其中形成一 接觸開口（contact opening) ’露出電晶體的源極和汲極區之 -。然後沈積-導電層’例如是一摻有雜質之複晶矽層， 其填滿前述接觸開口並延伸覆蓋在絕緣層21表面上。以 微影成像和姓刻程序定義此導電層’形成如第i圖所示之 平台式構造19a，其與餘留在接觸開口内的垂直主幹18共 同構成一儲存電極。接下來，在儲存電極露出的表面上， 依序形成一介電層和一相對電極（均未顯示），即可製 ( CNS ) 21^^57 (請先閲讀背面之注意事項再填寫本頁) 笨.Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (1) The present invention relates to the manufacture of semiconductor memory elements, and in particular to a star-type pedestal suitable for semiconductor memory elements. ................... ----------- ----* * type) Storage capacitor structure and manufacturing method. Its storage electrode contains one star. .......... ..........: Two ... The type base is composed of an axial center part and a plurality of wing-shaped parts that expand radially. The electrode surface area increases its capacitance. Dynamic random access memory (DRAM) is a widely used integrated circuit element ', which holds a very important position especially in today's information industry. With the evolution of process technology, the dynamic random access memory cells commonly used in production lines are mostly composed of a transistor and a storage capacitor. Basically, the source of the transistor is connected to a corresponding bit. Bit line, the drain is connected to the storage plate (storage plate) of the storage capacitor and the gate is connected to a corresponding vvord line, and the opposite electrode (0pp0site. Plate) of the storage capacitor is connected To a fixed voltage source 'and a dielectric layer is provided between the storage electrode and the opposite electrode. Accumulated DRAMs, such as those with a storage capacity greater than 16 million bits (16M), are usually implemented using storage capacitors with a three-dimensional space structure, such as the so-called trench-type or stacked-type (Stack_type) The valley device S has a memory component. Among them, because the former inevitably causes lattice defects on the substrate when the trench is truncated, which increases the chance of leakage current and affects the properties of the element, and as the aspect ratio of the trench increases, its The etch rate will also decrease, which is not only difficult to process but also affects production efficiency. Therefore, the manufacturing process of such trench capacitors on actual production lines is not common. On the contrary, the manufacturing process of the memory device of the multilayer capacitor does not have the above-mentioned disadvantages, so it is a technology generally used in current production lines. No. Concentrated π-turn to standard (CNS) A4 specification (· χ297) --------- yiyi ----- 1T ------ ·-(please fill in the back first Please pay attention to this page, please fill in this page) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) The traditional multilayer capacitor is called a platform capacitor, as shown in Figure 1 is an example ' Its manufacturing process mainly includes two parts: forming a transistor and forming a storage capacitor. First, a field oxide layer 11 is formed on a semiconductor substrate 10, such as a silicon wafer, to define an active region. Next, a gate oxide layer 12, a conductive layer 13, and a masking layer 14 are sequentially formed, and a pattern is defined by microlithography and etching procedures to form a gate structure. Using this gate structure as a mask, implanted impurities enter the semiconductor substrate 10 to form a pair of lightly doped source region 15a and drain region 15b. Then, an insulating sidewall layer 16 is formed on the sidewall of the gate structure by a deposition and etch-back process, and then the gate structure and the insulating sidewall layer 16 are used as a mask to implant a higher concentration of impurities into the semiconductor In the substrate 10, a pair of source regions 17a and drain regions 17b are formed to complete the fabrication of a transistor. Next, a storage capacitor was produced. Deposition-Insulation layer (not shown) 'is, for example, a borophosphosilicate glass (BPSG) layer, which covers the surface of the aforementioned transistor element, and forms a contact opening therein by lithography imaging and etching procedures. ) 'Exposing the source and drain regions of the transistor-. The deposition-conductive layer 'is, for example, an impurity-doped polycrystalline silicon layer which fills the aforementioned contact openings and extends to cover the surface of the insulating layer 21. This conductive layer is defined by lithography and engraving procedures to form a platform structure 19a as shown in Fig. I, which together with the vertical stem 18 remaining in the contact opening constitutes a storage electrode. Next, on the exposed surface of the storage electrode, a dielectric layer and a counter electrode (none of which are shown) are sequentially formed, and then can be made (CNS) 21 ^^ 57 (Please read the precautions on the back before filling this page ) stupid.
.1T 經濟部中央標準局貝工消費合作社印製 A7 BL_-- ----- &、發明说明（3 ) 0 健存電容器構造，完成動態隨機存取記憶单元的製程。 上述平台式電容器構造，在應用於〇·32μΠ1 (64MB dram)製程時’其因儲存電容值降低而比實際需求者為 小，因此在現今的生產線中，一般常採用皇冠式(cro wn-type) 儲存電容器構造，取代傳統的平台式儲存電容器構造，用 以增加電極表面積來提高其電容量。為清楚說明起見’第 2圖即顯示-穆具有皇冠式★容器之半導體記憶單元構造 的立體圖，其以一皇冠式構造19b取代傳統的平台式構造 19a。與第1圖比較，此一儲存電容器增加了皇冠式構造1外 内側四個表面，使電極表面積得以增加，恰可提供符合t 求的電容量。然而，隨著元件尺寸不斷縮小化的發展，此 種皇冠式儲存電容器所提供之電容量仍將不敷所需，因此 有必要尋求新的儲存電容器構造和製造方法，以應付更槪 細元件尺寸之製程的需求。 有鑑於此，本發明的一個目的’在提供一種積體％ 路儲存電容器的改良構造，其可進一步增加電極的表面 積，提昇電容器的電容量。 本發明另一個目的，在提供一種積體電路儲存電容 器的改良製程，其可在不增加製程步驟情況下，製造出符 合上述目的積體電路儲存電容器。 為了達成上述目的，本發明提出一種新的星型台座 式(pedestal type)儲存電容器構造及其製造方法，其利用自 動對準（self-aligned)程序形成一接觸窗，並在接觸窗内的 導電層主幹上形成一星型台座’共同構成一儲存電極，其 本紙張尺度適用中國國家檩準（CNS ) A4規格（21〇X297公釐） ----------衣------訂—-----、^· ί — (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製 A7 -----——~___ 五、發明说明（4 ) 中星楚台座係由-轴心部分和複數個呈放射狀展開的翼狀 部分所構成。如此’可進-步增加表面積而提供更大的電 容量，有利應用於更微細元件尺寸之製程。 本發一月所提出一種具星型台座式儲存電容器之半導 體記憶夺兀構造’包括：-電晶體，形成在一半導體基底 上，包含間極源極和;^極區，該電晶體表面上並覆蓋有 m m㈣開^露出源極和汲極區之一； 以及-儲存電谷器’電性輕接至電晶體的源極和沒極區之 -，其中該儲存電*器係、包括一儲存電極，形成在絕 緣層上並經由接觸開口而與源極和波極區之一連接，該儲 存電極至少包含位於接觸開口内的主幹(stem)和位於絕緣 層上方的星型台座’而該星型台座係由一轴心部分和複數 個呈放射狀展開的翼狀部分所構成，一介電層，形成在儲 存電極露出的表面上，及-相對電極，形成在介電層上。 依據本發明的較佳實施例，上述儲存電極之星型台 座係包含四個呈放射狀展開的翼狀部分。此外，上述儲存 電容器更可包括，複數個半球形石夕晶粒（hemi_sphericai siUcon grain，HSG)，形成在儲存電極表面上用以進一步 增加其表面積。 本發明所提出-種具星型台座式儲存電容器之半導 體記憶單元的製造方法，包括下列步驟：⑷提供一半導體 基底，其上形成有-電晶體，包含閘極、源極和没極區， 以及-絕緣層，覆蓋在電晶體上；（b)在絕緣層巾形成一接 觸開口，用以露出電晶體的源極和汲極區之一；（c)形成一 本紙張尺度適用中國國家標準（CNS ) A4規格（210χ297公釐） ^ '/'於 訂ii_ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印黎 A7 B7 五、發明説明（5 ) 第一導電層填滿接觸開口並延伸覆蓋在絕緣層表面上；（d) 選擇性地蝕刻第一導電層位於絕緣層上的部分以形成一星 型台座，其包括一軸心部分和複數個呈放射狀展開的翼狀 部分，該第一導電層餘留在接觸開口内的部分則形成一主 幹，並與星型台座共同構成一電容器的儲存電極；（e)形成 一介電層於儲存電極露出的表面上；以及（f)形成一相對電 極於介電層上，完成具星型έ座式儲存電容器之半導體記 憶單元的製造。 依據本發明的較佳實施例，上述在絕緣層中形成接 觸窗口的步驟，係以自動對準（self-aligned)程序來完成的。 上述絕緣層包括一删麟石夕玻璃（BPSG)層和一石夕氧化物層， 上述儲存電極和相對電極的材質均為複晶矽，而介電層的 材質可為氧化矽、氮化矽、氮氧化矽、氧化钽、或BST。 為了讓本發明之上述和其他目的、特徵、及優點能 更明顯易懂，下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡單說明 第1圖為立體圖，繪示一種習知之疊層式半導體記 憶單元，其具有平台式電容器構造； 第2圖為立體圖，繪示一種現有之疊層式半導體記 憶單元，其具有皇冠式電容器構造； 第3A圖為立體圖，繪示依據本發明之半導體記憶單 元，其具有星型台座式電容器構造； 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 笨..1T Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, A7 BL _-- ----- & Description of Invention (3) 0 The structure of a storage capacitor completes the process of the dynamic random access memory unit. When the above-mentioned platform capacitor structure is applied to a 0.32μΠ1 (64MB dram) process, it is smaller than the actual demand because of the lower storage capacitance value. Therefore, in the current production lines, the cro wn-type is often used. ) Storage capacitor structure, replacing the traditional platform storage capacitor structure, to increase the electrode surface area to increase its capacitance. For the sake of clarity, FIG. 2 shows a perspective view of a semiconductor memory cell structure with a crown-shaped container, which replaces the conventional platform-type structure 19a with a crown-type structure 19b. Compared with Figure 1, this storage capacitor adds four outer and inner surfaces of the crown structure 1 to increase the surface area of the electrode, which can provide a capacitance that meets the requirement of t. However, as the size of components continues to shrink, the capacitance provided by such crown storage capacitors will still be inadequate. Therefore, it is necessary to find new storage capacitor structures and manufacturing methods to cope with the thinner component sizes. Process requirements. In view of this, an object of the present invention is to provide an improved structure of an integrated capacitor, which can further increase the surface area of an electrode and increase the capacitance of the capacitor. Another object of the present invention is to provide an improved manufacturing process of an integrated circuit storage capacitor, which can manufacture an integrated circuit storage capacitor in accordance with the above purpose without increasing the number of manufacturing steps. In order to achieve the above object, the present invention proposes a new star-type pedestal type storage capacitor structure and a manufacturing method thereof, which uses a self-aligned procedure to form a contact window, and conducts electricity in the contact window. A star-shaped pedestal is formed on the trunk of the layer to form a storage electrode. The paper size is applicable to China National Standard (CNS) A4 (21 × 297 mm) ---------- clothing --- --- Order —-----, ^ · ί — (Please read and read the notes on the back before filling out this page) Printed by A7, Consumer Spending Cooperative of the Central Standards Bureau, Ministry of Economic Affairs --------- ~ ___ V. Description of the invention (4) The Star Chu platform is composed of a central axis part and a plurality of wing-shaped parts that expand radially. In this way, it is possible to further increase the surface area and provide a larger capacitance, which is advantageous for processes with finer component sizes. A semiconductor memory structure with a star-shaped pedestal storage capacitor proposed in January of this issue includes:-a transistor formed on a semiconductor substrate, including an interpolar source and a ^ electrode region on the surface of the transistor And it is covered with one of the source and drain regions exposed; and-the storage valley device is electrically connected to the source and non-electrode regions of the transistor, wherein the storage array device includes A storage electrode formed on the insulation layer and connected to one of the source and wave regions through the contact opening. The storage electrode includes at least a stem located in the contact opening and a star-shaped pedestal above the insulation layer. The star-shaped pedestal is composed of an axial center portion and a plurality of wing-shaped portions spreading radially, a dielectric layer formed on the exposed surface of the storage electrode, and an opposite electrode formed on the dielectric layer. According to a preferred embodiment of the present invention, the star-shaped pedestal of the storage electrode includes four wing-shaped portions that are radially expanded. In addition, the storage capacitor may further include a plurality of hemi_sphericai siUcon grains (HSG) formed on the surface of the storage electrode to further increase its surface area. The invention provides a method for manufacturing a semiconductor memory cell with a star-shaped pedestal storage capacitor, which includes the following steps: (1) providing a semiconductor substrate on which a -transistor is formed, including a gate, a source, and an electrodeless region; And-an insulating layer covering the transistor; (b) forming a contact opening in the insulating layer towel to expose one of the source and drain regions of the transistor; (c) forming a paper size applicable to Chinese national standards (CNS) A4 specification (210 x 297 mm) ^ '/' in order ii_ (Please read the precautions on the back before filling out this page) Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy Yin Li A7 B7 V. Description of Invention (5) Section A conductive layer fills the contact opening and extends to cover the surface of the insulating layer; (d) selectively etching a portion of the first conductive layer on the insulating layer to form a star-shaped pedestal, which includes a shaft portion and a plurality of The wing-shaped portion that is radially expanded, and the portion of the first conductive layer remaining in the contact opening forms a trunk, and together with the star-shaped base, forms a storage electrode of a capacitor; (e) forming a dielectric layer on the storage On the exposed surface of the electrode; and (f) forming an opposite electrode on the dielectric layer, a semiconductor έ complete fabrication pedestal with the storage capacitor star memorized cell. According to a preferred embodiment of the present invention, the step of forming a contact window in the insulating layer is performed by a self-aligned procedure. The insulating layer includes a BPSG layer and a stone oxide layer. The materials of the storage electrode and the counter electrode are polycrystalline silicon, and the material of the dielectric layer may be silicon oxide, silicon nitride, Silicon oxynitride, tantalum oxide, or BST. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings FIG. 1 is A perspective view showing a conventional laminated semiconductor memory unit having a platform capacitor structure; FIG. 2 is a perspective view showing an existing laminated semiconductor memory unit having a crown capacitor structure; FIG. 3A is A perspective view showing the semiconductor memory unit according to the present invention, which has a star-shaped pedestal capacitor structure; This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page ) stupid.
、tT 、發明説明（ό ) --——·.— 構造第以圖為第3A圖的上視圖，顯示星型的储存電極 第4A至4E圖均為剖面示意圖，說明依 星型台座式儲存電容器之半導體記憶單元的製造流程具 本發明所提出之星型台座式儲存電容器，其特徵在 於儲存電極形狀的改變’藉由修改光罩圖案，使得定義後 的儲存電極形成一星$二, 個個轴心部分和複數 放射狀展開的翼狀部分所組成，其中翼狀部分的數 目可以依實際需要及製程技術的進展而做適當調整。 第3A圖和第3B圖即顯示此種星型台座式儲 器應用於半導體記憶元件的-個例子，其中前者為立體圖 =後者為上視圖。如圖中所示者，在一形成有電晶體的半 體基底上，與電晶體源/汲極區相連接的導電層主幹Μ 和其上方的星型台a 29，共同形成_儲存電極，苴中星 型台座係由-個軸心部分29a和四個呈放射狀展開的翼狀 部分29b所構成。經由估算與實際量測的結果，在相同的 讀尺寸基準上’上述星型台座式電容器可較現有之皇冠 式電容器增加㈣以上的表面積，故可有效提高電容量。 欲製作上述具星型台座式電容器之半導體記憶元件 構造，可以有許多不同的製程方法，以下即配合第4a至 4E圖的r系列剖面圖’說明其中—種製法的流程，惟此 實施例僅為便於說明，並非用以排除其他製造方 經濟部中央標準局員工消費合作衽印製 A7 B7 i、發明説明（7 ) 首先，請參見第4A圖，在一半導體基底2〇上，依 序形成一閘氧化層22、一導電層23、及一遮蔽層24，並 以微影成像和银刻程序定義圖案，形成一閘極構造G。例 如.在一石夕晶圓上’以熱氧化(thermal oxidation)程序生成 一薄氧化層當作閘氧化層22，而以化學氣相沈積（CVD)程 序形成一複晶矽層當作導電層23，其可同步（in-situ)摻植 雜質以提高其導電度’之後樣以CVD程序形成一氧化 層當作遮蔽層24。接著，塗佈一層光阻（未顯示）並經微影 成像程序定義圖案，蓋住上述各層欲形成閘極的區域。以 此光阻圖案當作罩幕’依序钱刻遮蔽層24、導電層23、 及閘氧化層22至露出妙基底為止，形成一閘極構造〇， 然後去除該層光阻。 利用此閘極構造G當作罩幕，佈植雜質（ν型或ρ型） 進入半導體基底20中，以形成一對淡摻植(lightly d〇ped) 源極區25a和没極區25b。然後，在閘極構造g的側壁上 以沈積和回蝕刻（etch back)程序形成一絕緣侧壁層26 ,再 以閘極構造G和絕緣侧壁層26當作罩幕，佈植較高濃度 的雜質進入半導體基底20中’以形成一對源極區27a和 汲極區27b，完成一電晶體的製作。 接著，在前述電晶體元件上覆蓋一絕緣層，例如： 先以CVD程序沈積一硼磷矽玻璃（BPSG)層30,覆蓋在前 述電晶體元件的表面上’並以西溫熱氧化法形成一石夕氧化 物層31於BPSG層30上。然後’以微影成像和蝕刻程序， 在矽氧化物層31和BPSG層30中形成一接觸開口 32，露 -9- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) ------------4------訂------ 五、發明説明（8 ) ~ 出電晶體的没極區27b。隨著元件積集度的提高，各元件 之間的距離日趨縮小，圖中所示的没極區m寬度即較接 觸開口 32的上半部為小，一般製程因此如容易發生對準 偏移（miS-alignment)的現象，但在本實施例之製程中由 於閘極構U G侧壁上形成有絕緣侧壁層26，其與遮蔽層μ 共同作為银刻時的屏蔽，因此接觸開口 32的下半部能夠 以自動對準㈣f-aligned)方式自然形成，可精確露出没極 區27b而不會有對準偏移的問題。 請參見第4B W ’形成一導電層35以填滿前述接觸 開口 32並延伸覆蓋在矽氧化物層31表面上。例如：以cvd ，序沈積-複晶發層當作導電層35，其可摻植雜質以提 高其導電度。除此之外，為了提昇表面平坦度，亦可以先 形成-接觸餘（未顯示）填滿接觸開口 32後，再沈積形成 該導電層35。 接著，請同時參見第4C圖和第4D圖，分別為第3A 圖中沿I - I線和H-ϋ線所作的剖面圖。先在導電層％表 面上塗佈-層光阻（未顯示），並以改良的光罩（具有S星型圖 案）進行微影成像程序，使定義圖案的光阻蓋住導電層乃 欲形成儲存電極的區域，其為一星型放射狀圖案。然後， 以此光阻圖案當作罩幕，選擇性地蝕刻導電層％位於矽 氧化物層31上的部分形成一星型台座29，而留下導電層 35在接觸開口内的部分成為-主幹28，二者共同構成一 儲存電容器的儲存電極。在本實施例中，星型台座29包 括一轴心部分29a和四個呈放射狀展開的翼狀部外， 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（9 ) 當然，吾人仍可修改光罩圖案而製得包含其他數目之翼狀 部分29b的星型台座29。 去除上述光阻圖案後，請參見第4E圖，在儲存電極 露出的表面上形成一介電質層33.，例如是氧化石夕層、氣 化矽層、氮氧化矽層、氧化鈕（Ta205)層、或BST層。然 後，在介電質層33上形成另一導電層，例如，利用CVD 程序沈積一複晶矽層，且以i影成像和蝕刻程序定義圖案 而形成一相對電極34，完成一半導體記憶單元的儲存電 容器C。接著，可繼續進行絕緣護層和内連導線等後續製 程（未顯示），製得完整的記憶元件積體電路。 綜上所述，本發明星型台座式儲存電容器的製造方 法，利用自動對準程序形成一接觸窗，並在接觸窗内的導 電層主幹上形成一星型台座，共同構成一儲存電極。由於 星型台座係由一軸心部分和複數個呈放射狀展開的翼狀部 分所構成，平均可增加10%以上的表面積而提供更大的電 容量，因此可取代現有皇冠式儲存電容器，而應用於更微 細元件尺寸之製程。 本發明雖然已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0、〆297公釐） --------I ^-- (請先聞讀背面之注意事項再填寫本頁), TT, invention description (ό) --—— · .— Structure Figure top view is Figure 3A, showing star-shaped storage electrodes Figures 4A to 4E are cross-sectional schematic diagrams, illustrating star-shaped pedestal storage The manufacturing process of the semiconductor memory unit of the capacitor has the star-shaped pedestal storage capacitor proposed by the present invention, which is characterized by the change of the shape of the storage electrode. By modifying the pattern of the photomask, the defined storage electrode is formed into a star. It consists of a central axis part and a plurality of radiating wing parts. The number of wing parts can be adjusted appropriately according to the actual needs and the progress of process technology. Figures 3A and 3B show an example of such a star pedestal memory applied to a semiconductor memory element, where the former is a perspective view and the latter is a top view. As shown in the figure, on a half body substrate on which a transistor is formed, the conductive layer backbone M connected to the transistor source / drain region and the star stage a 29 above it form a storage electrode. The central star-shaped pedestal is composed of an axial center portion 29a and four wing-shaped portions 29b that are radially expanded. Based on the results of estimation and actual measurement, the above-mentioned star-type pedestal capacitors can increase the surface area by more than ㈣ compared with the existing crown-type capacitors on the same reading size basis, so the capacitance can be effectively improved. There are many different manufacturing methods that can be used to make the above semiconductor memory element structure with star base capacitor. The following is a description of the process of one of these methods in conjunction with the r series cross-sections of Figures 4a to 4E, but this embodiment only For the sake of explanation, it is not intended to exclude the consumption cooperation of employees of the Central Standards Bureau of the Ministry of Economic Affairs of other manufacturers. Printed A7 B7 i. Invention Description (7) First, please refer to Figure 4A on a semiconductor substrate 20 in order. A gate oxide layer 22, a conductive layer 23, and a shielding layer 24 are defined in a pattern by lithography and silver engraving procedures to form a gate structure G. For example, on a stone wafer, a thin oxide layer is generated as a gate oxide layer 22 by a thermal oxidation process, and a polycrystalline silicon layer is formed as a conductive layer 23 by a chemical vapor deposition (CVD) process. It can be implanted with impurities in-situ to increase its conductivity. Then, an CVD process is used to form an oxide layer as the shielding layer 24. Next, a layer of photoresist (not shown) is applied and a pattern is defined by the lithography imaging process to cover the areas where the gates are to be formed in each of the above layers. Using this photoresist pattern as a mask, the masking layer 24, the conductive layer 23, and the gate oxide layer 22 are engraved in order until a wonderful substrate is exposed to form a gate structure. Then, the photoresist of this layer is removed. Using this gate structure G as a mask, implanted impurities (v-type or p-type) enter the semiconductor substrate 20 to form a pair of lightly doped source regions 25a and non-electrode regions 25b. Then, an insulating sidewall layer 26 is formed on the sidewall of the gate structure g by a deposition and etch back procedure, and the gate structure G and the insulating sidewall layer 26 are used as a mask, and a higher concentration is planted. The impurities enter the semiconductor substrate 20 'to form a pair of source regions 27a and drain regions 27b, and a transistor is completed. Next, an insulating layer is covered on the transistor element, for example: a borophosphosilicate glass (BPSG) layer 30 is first deposited by a CVD process, covering the surface of the transistor element, and forming a stone by a thermal oxidation method. The oxide layer 31 is on the BPSG layer 30. Then, using a lithography imaging and etching process, a contact opening 32 is formed in the silicon oxide layer 31 and the BPSG layer 30. Expose 9- This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please (Please read the notes on the back before filling this page) ------------ 4 ------ Order ------ 5. Description of the invention (8) ~ Polar region 27b. With the increase of the component accumulation, the distance between the components is gradually reduced. The width of the non-polar area m shown in the figure is smaller than the upper half of the contact opening 32. Therefore, the general process is prone to misalignment. (MiS-alignment) phenomenon, but in the manufacturing process of this embodiment, since the insulating sidewall layer 26 is formed on the side wall of the gate structure UG, which together with the shielding layer μ serves as a shield during silver engraving, the contact of the opening 32 The lower half can be formed naturally in an automatic alignment (f-aligned) manner, and the non-polar region 27b can be accurately exposed without the problem of alignment shift. Referring to 4BW ', a conductive layer 35 is formed to fill the aforementioned contact opening 32 and extend to cover the surface of the silicon oxide layer 31. For example, cvd is used as the conductive layer 35, which can be doped with impurities to increase its conductivity. In addition, in order to improve the flatness of the surface, the contact opening 32 may be formed by forming a contact gap (not shown) before depositing the conductive layer 35. Next, please refer to FIGS. 4C and 4D at the same time, which are cross-sectional views taken along lines I-I and H-H in Figure 3A, respectively. First coat a layer of photoresist on the surface of the conductive layer (not shown), and perform a lithography imaging procedure with an improved photomask (with an S-shaped pattern), so that the photoresist of the defined pattern covers the conductive layer to form The area where the electrodes are stored, which has a star-shaped radial pattern. Then, using this photoresist pattern as a mask, a portion of the conductive layer% located on the silicon oxide layer 31 is selectively etched to form a star-shaped pedestal 29, and a portion of the conductive layer 35 left in the contact opening becomes the -stem 28. The two together constitute the storage electrode of a storage capacitor. In this embodiment, the star-shaped pedestal 29 includes an axial center portion 29a and four wing-shaped portions that spread out radially. It is printed by A7 B7 in the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of Invention (9) Of course, We can still modify the mask pattern to make a star-shaped pedestal 29 containing other numbers of wing-like portions 29b. After removing the photoresist pattern, please refer to FIG. 4E to form a dielectric layer 33 on the exposed surface of the storage electrode, such as a stone oxide layer, a vaporized silicon layer, a silicon oxynitride layer, and an oxide button (Ta205 ) Layer, or BST layer. Then, another conductive layer is formed on the dielectric layer 33. For example, a polycrystalline silicon layer is deposited by a CVD process, and a pattern is defined by an imaging process and an etching process to form a counter electrode 34 to complete a semiconductor memory cell. Storage capacitor C. Then, the subsequent processes (not shown) such as the insulating sheath and the interconnected wires can be continued to obtain a complete memory element integrated circuit. In summary, the method for manufacturing a star-type pedestal storage capacitor of the present invention uses an automatic alignment procedure to form a contact window, and forms a star-shaped pedestal on the trunk of the conductive layer in the contact window to collectively constitute a storage electrode. Since the star-shaped pedestal is composed of an axial center portion and a plurality of wing-shaped portions that expand radially, it can increase the surface area by more than 10% on average to provide greater capacitance, so it can replace the existing crown storage capacitors, and For processes with finer component sizes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies Chinese National Standard (CNS) Α4 specification (2 丨 0, 〆297 mm) -------- I ^-(Please read the precautions on the back before filling in this page)
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