TW382668B - Semiconductor device - Google Patents

Abstract

To prevent the power noise generated at the time of the operation of a buffer circuit from affecting other internal circuits. An internal circuit (102) and an output circuit (104) are provided with power cables (142a, 142b) and ground cables (146a, 146b) respectively. Only between the power csble and the ground cable of the internal circuit, a capacitor (C1) for stabilization is provided. No capacitance coupling between the power cable 142b and the ground cable 146b of the output circuit 104 is provided, and ground voltage is not lowered and a constant voltage level is held, even if power source noise generated and the power source voltage is lowered at the time when the output circuit is operating.

Description

Printed by the Consumers ’Cooperative of the Central Government Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (1) ---- This invention relates to semiconductor devices, especially to reduce the influence of power supply noise during snubber circuits < Composition. More specifically, the present invention relates to a configuration for reducing the influence of power supply noise on other internal circuits by mitigating the power of i circuits in semiconductor memory devices. / Qian 'is equipped with various semiconductor devices such as microcomputers, memory, and gates in various electrical products including personal computers and workstations. These semiconductor devices have a gain increaser for receiving signals or data from outside the device. When the semiconductor device is enclosed in an envelope, the gain increaser is connected to the external plug terminal; and when the semiconductor device is formed on the same wafer or other semiconductor conductor devices, the gain increaser is Consume in the inner Deng Xiao line. For the gain of the output signal or data, there is a large self-load due to the read capacitance and wiring capacitance of the external Deng device. Therefore, the gain increaser is driven out in order to store the signal or memory formed inside the device. Read out 'and install a drive circuit (wheel-out buffer circuit) with a huge current driving force. = Is when the semiconductor device is enclosed in an envelope and mounted in the second electrical plant. This—the plug terminals of the semiconductor device are connected to the conductors of the mounting substrate, and other semi-electrical elements that are connected to this plug terminal ^ and printed The drift capacitance of the wiring is large, and this large load capacitance (parasitic capacitance) must be charged and discharged within a fixed time. _This: The current driving force of the output buffer circuit (driving circuit) is far from the circuit. The current driving force is large. Fig. F is a diagram showing a configuration of a turn-out buffer circuit in a semiconductor memory device as shown in, for example, Japanese Patent Application Laid-Open No. 61_294929. (Please read the notes on the back before filling this page)

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (2) The pull-out buffer circuit includes: p-channel MOS transistor 3, which is connected between connection and input point 2; 1 transistor 4, connected between output node 2 and ground node 14 receiving ground voltage 14; NAND circuit 5, accepting internal readout 2 = and feeding data through inverter 7 to promote signal Z 'accepts the internal read data &amp; and the data output enable signal, and the output signal of the AND circuit 5 is fed to the MOS transistor 3 <idle pole. The output signal of the NOR circuit 6 is fed to the MOS transistor 4 &lt; gate. There is a large parasitic capacitance at the round-out node 2. Next, the operation of the output buffer circuit shown in FIG. 27 will be described with reference to the operation waveform diagram shown in FIG. The internal readout data d1 changes from the intermediate potential in the standby state to the low level. When the data wheel enable signal z0E is at a high level, the output signal of the inverter is at a low level, the output signal of the NAND circuit 5 is at a high level, and the output ^ of the NOR circuit 6 is at a low level. Therefore, the M0s transistor 34 is all OFF state. The output buffer circuit becomes an output high impedance state (Ηι-Z) ° At time TG 'If the data output promotes the signal z0E to a low level active state, it will reverse. The output signal of the phaser 7 becomes a high level. Both the ναν〇 circuit 5 and the NOR circuit 6 function as an inverter, and the output signals of the Ναν〇 circuit 5 and the NOR circuit 6 both become a high level. The 0FF state and the _3 transistor 4 are brought to the ON state. Therefore, the output node 2 discharges to the ground node 16 through the M0S transistor 4 in this ON state, and the externally read data signal D1 goes from the high impedance state to _2 toward the ground (please read the precautions on the back before filling this page)

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, 1T ..- uit: .. r;.:. L · 1-— ·. Master one one… .ι.ΐ This paper is a household name (c is called A4 · (2igx297 public magic A7 A7 Central Building of the Ministry of Economic Affairs) Printed by quasi-office consumer cooperatives 5. Description of invention (3) The level is lowered.,] Tl 'If the data rotation is enabled to cause the signal ZOE to be at a high level, regardless of this-the logical level of internally read data ⑴ , NMD circuit 5 and NOR circuit 6 bismuth mountain / order wheel out ㈣h divided into high level and low level, output; ^ red circuit again into a high impedance state. ',' Person 'if other storage units are Select, the high-level data is read ^ The internal read-out data dl becomes the high level, and at the moment, the data rotation enables the signal ZO0E to become the low level again. In this state, the NAND circuit 5 and the professional circuit 6 once again For the inverter, let these: the output number of 6 become low level. Therefore, the Mos transistor 3 is turned on, and the Mos transistor 4 is turned on. From this state, the output node is &lt;; M0S transistor 3 is charged to the power supply voltage ~ quasi 'to make the externally read data m high level. At ㈣T3' if the data is lost to the letter again If ZQE becomes high, the output buffer circuit becomes high-impedance state again. Figure 29 is a diagram showing a configuration example of a power supply line and a ground line of a semiconductor device. In FIG. 29, there are three circuits for generating internal readout data. η and the output buffer circuit 12, a power line and a ground line are provided in common. The power supply voltage Vcc is transmitted here-the power line is here: the ground voltage leakage is transmitted to the ground line 。. The readout from the round-out buffer circuit 12 The data signal is changed from a low level to a high level. As shown in Figure 27, the current flows from the power node 13 to the transistor 2 to the output node 2. The money-passing circuit 12 exists at high speed ^ for the huge parasitics of node 2 The capacitor is charged, so _s transistor =. ___ This paper size is suitable for 1¾¾ standard (CNS) reel (2) 0X297 / Jjy ------—— Λ4, (Please read the precautions on the back first (Fill in this page) — Order --- Line ----- A7 B7 V. Description of the invention (4) ^ ~ --- and 4 has a huge current driving force. Therefore, in this case, in the place shown in Figure Ϊ : Ϊ́ Read data signal D1 from the round-out buffer circuit 12 from low level = accurate When the time is high, the current on the power supply line 10a is rapidly eliminated. The power supply and voltage VCC on the power supply line 10a are reduced to approximately 0.5V. Also, the read data signal D1 from the output buffer circuit 12 is reduced from a high level At the lowest level, the MOS transistor 4 shown in FIG. 27 is turned on, and a large current <node 2 is rapidly discharged to the ground node lb. In this case, the ground line 10b cannot output an output buffer circuit from this. / 2 is suddenly absorbed by the discharge &lt; large current, and the potential level of this ground voltage GNd is about 0.5V. . Power supply noise (noise at the power supply voltage and ground voltage) on the power line 1 Oa and the ground line 1 Ob are transmitted to the internal circuit 11. In the case of power supply, Vcc is about 5V, this—power supply noise is about 1 / 10th of the power supply, this noise is relatively small, and no malfunction occurs due to power supply noise in the internal circuit 11. Problem. However, in recent years, with the increase in the density of semiconductor devices, in order to achieve low power consumption and fast speed operation, the potential level of the power supply voltage Vcc is generally lower than 33 V or lower. In this case, because the 105V power noise is about 1/6 of the power voltage Vcc, the power circuit noise will cause the internal circuit 11 to malfunction, and the high-level signal is determined to be the low-level. It is a problem that a signal of a low level is judged as a high level and a malfunction is caused. In order to absorb the power noise as described above, as shown in FIG. 31, Μ is set to Daan 7 near each of the internal circuit 11 and the output buffer circuit 12 ... I I-----^ Γ.ί &gt; · -I —— I &quot; 乂: (Please read the notes on the back before filling this page) Order I --- Member of the Central Standards Bureau of the Ministry of Economic Affairs. System A7 --------- B7 V. Description of the invention (5) &quot; — &quot; &quot; A certain retreat capacitors C1 and C2. These retraction capacitors 0 and 0 are connected between the power line 10a and the ground line 10, respectively. When the output buffer circuit 12 operates, consumes the current on the power supply line 10a, and the power supply voltage vcc decreases, this-the decoupling capacitor C2 supplies the stored positive charge to the power supply line 抑制, and suppresses the decrease of the power supply voltage Vcc. On the other hand, when the turn-out buffer circuit operates and discharges current to the ground line 10b, this discharge current is absorbed by the single capacitor c2 to suppress the increase of the ground voltage. In addition, a single capacitor 0 located near the internal circuit u is used to suppress the power noise of the internal voltage U and the voltage Vcc of the internal circuit U, and prevent the power noise caused by the operation of the output buffer circuit 12 from flowing to the internal circuit. 11 Communicating this-Retirement capacitors are designed to suppress power supply noise by their stored charges (positive and negative charges). 'It has a capacitance of hundreds of picofarads of about 45 GPF, for example. As a result, the capacitor CUC2 is renamed, and the power line and the ground line ⑽ are capacitively coupled. The decrease speed of the power supply voltage Vcc on the power supply line 10a is rapid, and a change in the AC mode occurs. Therefore, as shown in FIG. 32, due to the drop capacitor C2, the power supply line i0a and the ground line 10b are coupled in an AC manner, and the potential decrease of the power supply voltage Vcc is transmitted to the ground line i0b, The ground voltage GND decreases. The capacitors ci and C2 are designed to increase the ground voltage by self-absorption. Therefore, when mD is reduced, the absorption potential of the decoupling capacitors C1 and C2 cannot be reduced by this. When the semiconductor device is a semiconductor memory device and the internal circuit is a circuit for driving the ranks of the memory cells, the following problems occur. This paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7 V. Description of the invention (6) Figure 33 shows the structure of the storage unit. In FIG. 33, the memory cell MC includes an access transistor QM and a storage capacitor CM. The access transistor QM is connected by a conductive node connected to one side of the bit line BL and connected to the other side of the storage node SN. A node and an n-channel MOS transistor connected to the gate of the word line WL. The storage capacitor CM has an electrode connected to one side of the storage node SN and an electrode connected to the other side of the cell plate voltage. Generally, the cell plate voltage is maintained at the intermediate potential level of (Vcc + GND) / 2. The memory information is stored in the storage node SN as a charge. Now consider a case where the word line WL is in a non-selected state and its potential is 0V. When the itching buffer circuit 12 operates, the bit line BL is connected to the selected word line (a word line different from the word line WL), and according to the memory of the storage unit connected to the bit line BL Data to make it high or low. Now consider a case where the potential of the bit line BL is a low level and 0V. At this time, when the output buffer circuit 12 operates as shown in FIG. 32 and the power supply voltage Vcc decreases, the ground voltage GND also decreases. This decrease in the ground voltage GND is transmitted to the internal circuit 11 as shown in FIG. 31, and the potential OV of the bit line BL is reduced to a negative potential level. The potential of the word line WL is 0V, so the potential difference between the gate and the source of the storage transistor QM becomes larger than OV, and the storage transistor QM · becomes a weak conduction state, and the charge (positive charge) stored in the storage node SN is stored. The bit line BL is discharged. Therefore, the storage charge of the non-selected storage unit is reduced, and the data retention characteristics of the storage unit are deteriorated. In the worst case, the memory data of the non-selected storage unit will be destroyed. (Please read the notes on the back before filling this page)

'IT This paper size applies the Chinese National Standard (CNS) A4 specification (2K) × 297 mm] 5 Description of the invention (7 _ Also, in the selected storage unit to protect * The muscle potential is maintained in electrical data' bit line this one The power supply voltage Vee, H of the bit line BL, and the potential of the data written to the high level of the cell due to the electrical transmission: "In" is written in the charge necessary for selective storage and stored in the storage node. When the level of data cannot be written or restored, such pride will occur at high heights ... The knowledge point SN will be reduced, the amount of charge will decrease, and this error will cause the problem of deterioration of the charge retention characteristics. The buffer current is reduced by a person, a person, and a person. The ground voltage on the ground line is low and low, which is used to drive the low level. T MOS 4 The potential difference between the source and the source is increased. Large: electric-body 4 state, and there is power reduction from this output node ... invited to become a weak 0N shape 丨 out of the knowledge point 2 flow to the ground node ib. Therefore, = the potential level is more reduced, and the ground voltage: c message increased, and the data letter was read out ... the low-level I occurred 51 * correct data &lt; problem. Also, here The problem is that the current consumption of the snubber circuit increases from the power node 13 through the M0S transistors 3 and 4 to the ground node lb '. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. A diagram of another structure of the punching circuit. In FIG. 34, the output buffer circuit includes: an inverter 13 for connecting the internal readout data dl; a NOR circuit M, which receives the data output facilitating signal zoe and the inverse The phase output signal of the phaser 13; the NOR circuit, accepts the internal readout data dl and the data output enabling signal ζ〇Ε; n-channel M0s transistor 16, connected between the power node 1a and the output node 2 , When the output signal of the NOR circuit 14 is high, it will be turned on; ^ channel survey ^ transistor 17, when the output signal of the NOR circuit μ is high, it will be turned on. This paper standard Gu Xiangmu family standard A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (8) The substrate field of MOS transistors 16 and 17 (semiconductor substrate or # 领 城) is subject to a negative bias voltage VBB. The data output enables the signal ZOE When high, NOR power The output signals of 14 and voltage level are both low level, and the MOS transistors 16 and 17 are in the OFF state, so that the output buffer circuit becomes a high impedance output state. If the data output promotion signal ZOE is at a low level, the NOR circuit 14 and 15 both act as inverters. When the internal read data dl is at a low level, the output signal of the NOR circuit 14 is at a low level, and the output signal of the NOR circuit 15 is at a high level. The MOS transistor 17 becomes the OFF state and the output node 2 Discharge to the ground voltage GND level. When the internal read data dl is at a high level, the NOR circuit 14 becomes a high level due to the lack of output signals, the output signal of the NOR circuit 15 becomes a low level, and the output node 2 passes the ON state MOS transistor 16 and discharge to the power supply voltage Vcc level. In the case of the output buffer circuit shown in FIG. 34, the same problem of power noise as that of the output buffer circuit described above occurs. In the case of the configuration of the output buffer circuit as shown in FIG. 34, a problem due to the substrate bias voltage VBB occurs even more. FIG. 35 is a diagram schematically showing a cross-sectional structure of a memory cell included in the output buffer circuit and the internal circuit shown in FIG. 34. FIG. In FIG. 35, the output buffer circuit is formed in a 卩 -type # 22 formed on the surface of the P-type semiconductor substrate 20. In FIG. 35, only the structure of the MOS transistor 16 included in the output buffer circuit is shown. This MOS transistor 16 includes: high-concentration N-type impurity regions (N + impurity regions) 22a and 22b; and a gate electrode 22c formed between the impurity regions 22a and 22b via a gate insulating film (not shown). 11 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) --------- Γ1 ^ ------ Order ------- _ i S (please first Read the notes on the back and fill in this page) A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of Inventions (9) On the channel city. The impurity region 22b is connected to the power node la. On the surface of P # 22, a high-concentration P-type impurity region (P + impurity region) 22d is formed. The bias voltage VBB is applied to P # through an impurity region 22d. The memory cell is formed in P # 24 formed on the surface of the P-type semiconductor substrate 20 separately from P # 22. The storage unit includes: N-type impurity regions 24a and 24b formed on the surface of P # 24 separated from each other; and a gate formed on the channel region between the impurity regions 24a and 24b via a gate insulating film (not shown).极 electrode 24c. The impurity collar 24a is connected to the bit line BL, and the gate electrode 24c is connected to the word line WL. The storage unit further includes a conductive layer 24d connected to the impurity collar 24b and a conductive layer 24e formed opposite to the conductive layer 24d. These conductive layers 24d and 24e form the electrodes of the storage capacitor. On the surface of P # 24, a bearing is further formed. The P-type impurity region 24f of the bias voltage VBB. This bias voltage VBB is fed from a common bias voltage generating circuit. That is, P # 22 and P # 24 are electrically connected by a bias voltage VBB transmission line. A coupling capacitor 22e is formed between the impurity collar 22e and P # 22. As shown in FIG. 36, when power supply noise occurs and the power supply voltage Vcc decreases, the potential of P # 22 also decreases due to this parasitic capacitance 22e. This potential decrease of P # 22 is transmitted to the N-type impurity region 24f of P # 24 via impurity collar 22d, and the bias voltage level of P # 24 also changes accordingly. The threshold voltage of the n-channel MOS transistor is proportional to the square root of the absolute voltage | VBB | of the bias voltage VBB. Therefore, when the bias voltage VBB of P # 24 decreases, the critical voltage of this storage transistor becomes large. Therefore, Cheng Fu 12 (Please read the notes on the back before filling this page) Binding

0C This paper size applies to Chinese National Standard (CNS) Α4 size (210X 297 mm) A7 A7

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (1/10 / The conductivity of the misstored transistor included in the image storage unit in the selected state becomes larger. The problem that a sufficient amount of charge is transferred to the storage node (impurity field 24b).… If the VBB of Genpower is reduced due to the parasitic capacitance 22e, the bias voltage level of P # 24 will also be trapped with ## ^ M, 4, &lt; The decrease is due to the coupling of the electric field of the impurity region 24b and the junction capacitor, φ,% valley coupling 13, and the electric current flows out of the impurity field 24b to the impurity, so the amount of stored charge of the #storage cell is reduced. Due to such knowledge, the problem of deterioration of the load retention characteristics due to the change in the voltage VBB occurs. In the semiconductor memory device, there is a big loss of data as the data is input and output. It is expected that the noise of the power supply will also increase α + and the output circuit will have a larger tendency. Also, in the logic, with its high density, there will be rounds, and thousands of conductors will be placed in the center. , And the number of circuits also increases, ㈣ the tendency of output The problem of power noise caused by the average door sample is obvious. The charge and discharge speed can be reduced, but in this field: Although the output node is reduced: the output speed is reduced, so i method 2 will be generated * The problem of this issue is to send out the letter of “-,” and “speed-out of data.” The purpose of the present invention is to provide: Low power noise when the buffer circuit operates to the internal circuit ::: ... The purpose is to provide the charge retention characteristics of a semiconducting storage unit. Ak, which can be changed in Z paper size.

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W 13 V. Description of the invention (11) ~~~ —___ If you apply for a patent, the first semiconductor semiconductor source supply line to convey the potential of the i-th wire is equipped with: the first power to communicate the second power supply potential; the internal circuit, Let the first = supply line, use the first! Power supply potential and the second power supply: = on-line and one-side action power supply voltage while _ two ^ potential for processing and out of the "· capacitor, the result is between <signal plus power supply line; the first 3Electricity second; == Separate from the first, used to convey that the first ^ supply line is set separately from the second power supply line, using the original supply line. 3 power supply and buffer circuit, so that the third power supply = =: 4th power supply line: reasonably ^ press and operate 'the buffer circuit for the internal circuit's output signal, please call on the semiconductor in the first scope of the patent The device is equipped with the first power to communicate the first power potential; the second power supply line uses 2 = source potential; the internal circuit 'makes the first power supply line printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The second potential of the power supply line acts on the source voltage, and a capacitor with an effective capacitance 加 is applied to the fed-in signal. The third power source and the first power source supply line; the third power supply line is provided separately from the fourth power source and the original power supply line, and is used to communicate the first power source and the potential; the supply line 'and the second power source The supply line is set separately and used for the 14 1 power supply potential; and _ the circuit to make the 3 «supply line printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The first power supply potential on the description of the invention (12) and the first The second power supply potential on the 4 power supply line operates as the operating power supply voltage of the-side and the other side, and the output signal of the internal circuit is buffered and output; the fourth power supply line on the third power supply reel In between, there is only a parasitic capacitor having a substantially smaller effective capacitance, as a means for capacitively coupling the third electric green supply line and the fourth power supply supply line. For example, the semiconductor device under the scope of patent application No. 3 is provided with: &amp; power supply line to convey the number! Power supply potential; a second power supply line to communicate the second power supply potential; an internal circuit that makes the first power supply line {the first power supply potential and the second power supply potential on the second power supply line as one side and the other It operates with the operating power supply voltage, and processes the signal input from the library. The capacitor with effective capacitance is consumed between the first power supply line and the second power supply line. The third power supply line, The power supply line is provided separately and is used to communicate the i-th power supply potential; 2 4 power supply lines are provided separately from the second power supply line and used to equal the second power supply potential; The third power supply line = the i-th power supply potential and the second power supply potential on the fourth power supply line operate on the 2-side and the other-side operating power supply voltages, and the number of the internal circuit is output by buffer processing ; And 0 with effective capacitance 値, ... a semiconductor device such as the fourth item in the scope of patent application, which is combined with the third power supply line and the fourth power supply line, is provided with: first to communicate the first power supply potential ; The second power supply line, used to communicate 2 power supply potential; an internal circuit, enabling the first power supply line 15 Shu scale paper applicable 210X297 mm) t · * ·, - (Read Notes on the back page and then fill}

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs) Μ Β7 ~ «_ --------- 1 &quot; ~ V. Description of the invention (13) '~-' 一-The first power supply potential and the The second power supply potential on the second power supply line operates as the operating power supply voltage on one side and the other side, and the fed-in number is processed and output; the first insulated gate-type electric field effect transistor, including: 1st and 1st 2 conduction nodes, both of which are connected to the} th power supply line; and the pole of the second power supply line; the third electric green supply line is provided separately from the first power supply line to communicate The first power supply potential; the fourth power supply line is provided separately from the second power supply line to communicate the second power supply potential; and the buffer circuit causes the third power supply potential on the third power supply line and the fourth power supply line The second power supply potential on the power supply line operates as the one-side and the other-side operating power voltages, and buffers the remaining signals from the internal circuit; and the second insulated gate-type electric field effect transistor includes: the i-th And the second conduction node are respectively connected to the third power supply ,, And springs, and gates that are not connected to the fourth power supply line. The semiconductor device that is pleased to apply for the fifth item of patent, such as the device of any one of the items 1 to 4 of the scope of patent application, further includes: the &quot; wonder device, and the common ground handle of the first and third power supply lines Close, to withstand the 电源 j power supply potential; and the second booster helmet, which is coupled to the second and fourth power supply lines in common, to withstand the second power supply potential. ~ If you apply for a full-time semiconductor device of the sixth material, it is a device such as any one of the first to fourth of the target circle of the patent application, and it also includes the &quot; loss device, which fits with the first power supply line, It is used to bear the i-th power source potential; the second heart loss is coupled to the second power supply line to bear the second power-supply potential; the third loss increaser is connected to the first! The picker is set separately and is in conjunction with the '3th power supply line' to withstand the first power supply potential, and the fourth increase and loss 16 This paper is of suitable size ^ (Please read the precautions on the back before filling this page }

A7 B7 Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (14) The device is separately installed from the second loss increaser and is coupled to the fourth power supply line to withstand the second power supply potential. For example, the semiconductor device with the scope of patent application No. 7 is in the device with the scope of patent application No. 6. The buffer circuit is formed in the field of semiconductor substrates, and a bias power line is further provided. The bias power line is A total of two are coupled to the first loss reducer, and since then the i-th gainer has been subjected to the i-th electric green potential. For example, the semiconductor device in the 8th scope of the patent application is in the patent scope of Rushenshe, and the 5th device further includes: a capacitor, which is cut into the phase of the loss increaser of the first power supply line. Part i of the coupling and the node of the second part coupled to the internal circuit and the second supply line; and the bias source line, which is coupled to the semiconductor substrate field where the snubber circuit is formed, Between the two parts, the i-th power supply potential on the second part is transmitted to the semiconductor substrate field. For example, the semiconductor device for which the scope of the patent application is item 9 is in the device of any one of the scope of the scope of the application, such as the scope of the application, in the semiconductor substrate: field J-shaped = punch circuit; and more equipped: a wave deleter; and The bias power supply and the spring are provided separately from the third power supply line to connect the first! The power supply potential is transmitted to the semiconductor substrate field via the low-pass filter. The semiconductor device of the patent scope of item 10 is a low-pass device such as the device of the patent application No. 9, including a capacitor connected between the bias power source and the fourth power supply line of the spring. The semiconductor device of item 11 in the scope of the patent application is in the device of item 9 of Rushenshebei: Weiwei. The bias power line is a loss increaser that is commonly coupled to the third power line of the Haier. And the low-pass data packet = 17 (please read the precautions on the back before filling out this page). Installation-,? Τ line · ', 豕 Paper size is suitable for A4 size (21〇297mm) A7 ~ ----- ^ B7 V. Invention 15) ~ --- ~~ A capacitor connected between the bias power line and the second electrical pull, ^ ^ electric threat and supply line. For example, if the scope of the patent application is 12th, the museum + conductor device is attached to the device of the scope of the patent application, and the bias voltage &gt; 1 green system is electrically connected to the phase of the first power supply line. The connected filter; and the low-pass filter includes a capacitor lightly connected between the bias power line and the second electric green supply line. For example, the semiconductor device with the scope of patent application No. 13 is in the device with the scope of patent application No. 9 and is equipped with a destructor that is lightly connected to the third power supply line and the fourth power supply line. It is provided separately and accepts the bias power-increasing device of the second power supply potential; the low-pass wave filter &amp; includes a capacitor coupled between the bias power line and the bias power-increasing device. For example, the semiconductor device in the scope of patent application No. 14 is in the device in the scope of patent application No. U. The K2 is provided separately from the third power supply line and is electrically coupled to the third power supply line. For example, the semiconductor device with the scope of patent application No. 15 is in the device with the scope of patent application No. 13 and the bias power supply line is coupled to the respective power supply line and the second power supply line. The booster is separately provided and is used to receive the first power potential on the booster. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs i. 丨, I--I ---- ί Pack --- ',,.' C Please read the notes on the back before filling out this page} The 16-semiconductor device belongs to the device of any one of items 1 to 6 of the patent application scope. The buffer circuit is formed in the field of semiconductor substrates, and the third power supply line is also lightly fitted here. . For example, the semiconductor device in the scope of patent application No. 17 is a device such as the device in any of the scope of patent applications No. 1 to 6, and there is a low-pass device provided in the third power supply line and the fourth power supply line. Wave device. This low-pass data sheet is compatible with the Chinese National Standard (CNS) A4 specification (2 10 × 297 mm) A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (16) Contains: A first resistance element connected to the third power supply line; a capacitor coupled between the third power supply line and the * th power supply line; and a second resistance element interposed between the fourth power supply line. For example, the semiconductor device under the scope of patent application No. 18 is provided with: a buffer circuit 'formed in the semiconductor substrate collar, and the buffered signal is outputted after being fed; a low-pass filter; and a substrate bias generating mechanism for A bias voltage to be applied to the semiconductor substrate field is generated and applied to the semiconductor substrate field through the low-pass filter. For example, a semiconductor device with a scope of 19 in the patent application is a device with a scope of 18 in the patent application, and an internal circuit is formed in the second semiconductor substrate field separately from the semiconductor substrate field to process the feed. The 彳 & number feeds a signal indicating the result of the processing to the buffer circuit. The bias voltage from the substrate bias generating mechanism before being processed by the low-pass filter is applied to the second semiconductor substrate field. For example, the semiconductor device in the scope of patent application No. 20 is in the device in the scope of patent application No. 18, and further includes: an internal circuit formed in the second semiconductor substrate field separately from the semiconductor substrate field For processing a fed-in signal, feeding a signal representing the processing result to the buffer circuit; and a substrate bias generating mechanism, which are respectively 'set' with the substrate bias generating mechanism for generating the same voltage as the bias voltage A bias voltage of a voltage level is repeatedly applied to the second semiconductor substrate field. For example, a semiconductor device in the scope of patent application No. 21 is in the device in any of the scope of patent applications in Nos. 6 to 17, the buffer circuit is formed in the field of the semiconductor substrate, and丨 Power supply 19 The paper size is applicable to China National Standards (CNS) (21 () &gt; &lt; 297 male sauce (please read the precautions on the back before filling this page)-binding ^ &quot; .CI. .I -II— I— I n ^ i Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7 • 丨 丨 _ B * 7 Five, m ^ TTr &quot; --- In the field of the bias voltage of different bits. If applied The semiconductor device of the scope of the patent No. 22 is a device as in any of the scope of the patent application of the terms of 6 to 17, the buffer circuit is formed in the field of the semiconductor substrate 'and has a bias different from that of the i-th power source potential Piezoelectric potential is supplied to the field of semiconductor substrates. For example, a semiconductor device with a scope of 23 in the patent application is a device in any of the categories 1 to 20 of the patent application, and it also includes a majority arranged in a matrix. Storage unit; the internal circuit contains storage orders from the majority Wuzhong selects a storage unit and reads out the memory data of the selected storage unit; the buffer circuit includes a wheel-out circuit that outputs the data read by the internal circuit to a wheel-out circuit outside the device. By eliminating the effective capacitive coupling (AC-type coupling) between the power supply lines provided in the buffer circuit, it is possible to prevent voltage noise on one power supply line from being transmitted to the other power supply line, thereby enabling The voltage on these power supply lines is stabilized. This buffer can be made by coupling a bias power line for transmitting the first power potential to the area of the substrate on which the buffer circuit is formed via a low-pass filter. The potential of the substrate area of the circuit is stabilized, so that noise generated by changes in the first power supply line can be prevented from being transmitted to other internal circuits through this substrate area. Also, 'the substrate bias voltage is passed through a low-pass filter. And applied to the substrate collar city 'or by using a different circuit from the internal circuit to generate such a substrate bias and electricity, which can prevent the buffer circuit. Noise-induced bias voltage piezoelectric bit of a change to other internal circuitry of the wheel (Please read the notes on the back of this page and then fill in) h -. _ Set loaded line Shu Γ.

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This paper is printed from Shicaiguan A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (18)-[Implementation Mode of the Invention] (Overall Structure) Figure 1 is a schematic view showing a semiconductor device according to the present invention. The overall composition of the scheme. In the figure, the semiconductor device 100 includes: internal power supply, which performs a predetermined process in accordance with the input signal IN; and an output circuit ι04, which buffers the signal fed by the circuit 102, and The rotation signal (the data signal) D is rotated. The internal circuit includes: the instrument storage list 102a, which has most of the storage units arranged in rows and columns, and the peripheral circuits. The storage unit, which is selected based on the signal IN input from the outside, stores the selected storage unit. The data is read out, and the power is fed to the wheel = HM feed. This 'this-rank peripheral circuit' includes address decoding circuit, data input circuit, precharge / equalization circuit for storage unit rank 102a, and internal readout circuit. (Preamp) and so on. Therefore, the output circuit U) 4 constitutes an output buffer circuit for amplifying the internal read data signal and outputting it to the outside, and more preferably constitutes the final stage of the output buffer circuit. Fig. 2 is a diagram schematically showing the overall configuration of a modified example of a semiconductor device according to the present invention. In FIG. 2, the semiconductor device U0 includes a punch circuit _ 'used to buffer the input signal IN fed from the outside' to generate an internal signal; the internal circuit ⑽, the input buffer circuit n0a K buffer circuit Apply the predetermined processing and buffer circuit]] Oc applies the clock signal to the output signal of the internal circuit uOb, and the internal circuit nod 'applies the predetermined "processing" to the output signal of the buffer circuit 11oc. And the output buffer circuit li〇e, which will feed 21 from the internal circuit no.

---;-: ---- ^ —— (Please read the notes on the back before filling this page),? Τ •-n t —I. Line! Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. The description of the invention (19) The signal input is buffered and generated outside the wheel device. This semiconductor device 11 () performs two logical steps: == turns out to 110b and ii〇d, respectively. The purpose of the buffer circuit is to find the internal signal line of a large capacitor in the semiconductor. 1 Smart Drive Compared with the present invention, this picture can also be applied to this picture! The buffer circuit Uoc and the output buffer circuit U2 shown in Figure 2 are as follows: However, in the following description, for convenience of explanation, the output circuit for outputting signals to the outside of the device will be described. FIG. 3 is a diagram showing an example of the configuration of the circuit in the turn-out. In the figure = circuit 104, n-channel transistor 113 is connected between the power node Ula and output node 112, and the internal driving signal Φ〇 is received; and n-channel MOS transistor 114 is connected to the output node. μ and, between the ground node ⑽, receive the driving signal 〇 between them. In the substrate area of the transistors 113 and 114, a negative bias voltage is applied. The structure of this output circuit 104 is substantially the same as the structure of the final stage of the round-out signal shown in the figure. In the round-out buffer circuit, only the final stage of the MOS circuit with a large current driving force is provided. Crystal. Therefore, the influence of power noise during the operation of the MOS transistors 110 and 114 in this final stage can be prevented. Figures 4A to C are diagrams showing an example of the planar layout and cross-sectional structure of the output circuit shown in Figure In FIG. 4A, an impurity region 117 where a negative substrate bias voltage vBB is applied is formed and surrounds an active region of the MOS transistor 113 (p ^ ii3a and an active region of the MOS transistor 114. In the impurity region n7 22 paper Standard Standard (CNS) Frame (

A7 A7 Printed by the Consumers 'Cooperative of the Central Bureau of Benzene Department V. Invention Description (20) The outer periphery' forms the applied absorption noise 118, and surrounds this impurity area 117. The voltage application leads to the]] miscellaneous! . The power supply voltage VCC1 is fed through the low-resistance body 113 &lt; wiring (the same symbol as the node ft table $). This power cord No. ^ 仃! 1 2, ^ 1 & has a branch cut on the active area 113a to form a &lt; dentate portion. The signal line 113b used in the negative field of true Dm operation is provided with a toothed portion on the # 113 / ring line 113U. This 俨, extends to activity, a. No., Izumi 1131 :) The tooth-shaped part becomes 扈 M〇 日 体 113_ 间 极. The output of forming a toothed portion having an extension adjacent to the gate electrode layer is believed to be in the eyes of a woman, line a 115. This round of output signal line ⑴ also has a tooth-shaped portion cut through the extension of the MOS transistor 114 by k. The ground line (a and the ground node are represented by the same symbol) a has a toothed portion extending across the MOS electric solar body 114 &lt; active field 活性. A signal line 114b is formed to have a toothed portion adjacent to the toothed portion of the ground line 11b. The driving signal ^ is transmitted here: 114b. Now, in this configuration, the configuration is configured in order to convey the driving signal ㈣ toothed part, the song-shaped Deng points used to communicate the power voltage VCC1 (ground power IGND), and to convey the wheel-out signal ⑽ρ or d _ Or internal output signal). By alternately arranging this tooth-shaped portion, the active areas 113a and 114a &lt; the direction perpendicular to the drawing &lt; length can be shortened to form a MOS transistor with a larger idler width. That is, a Mos transistor with a large Wei (inter electrode width / inter electrode length) and a large current driving force is formed. 23 This paper is sized ^

f% first read the notes on the back #Fill this FC .------ Order I — β / .11 »—1—« I in A7 B7 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs .. ......................... ni V. INTRODUCTION TO THE INVENTION (21) Fig. 4B is a diagram showing a cross-sectional structure taken along line AA in Fig. 4A . In FIG. 4B, the 'MOS transistors 113 and 114 are formed in an n-type # 52118 formed on the surface of the P-type semiconductor substrate 120. Is applied within this N-type #field 118. An N-type impurity region 119 is formed on the surface of the P-type # 113d in the n-type # 118. A gate electrode layer 113b is formed on P # 113a between the impurity regions 119. The impurity region 119 is alternately connected to the electrode layer 111a and a signal line 115 for inputting a driving signal. The substrate bias voltage VBB is applied to this p # 113d via the P-type impurity region 117. The other internal circuits are formed in P # 130 which is formed separately from this n # 118. The substrate bias voltage VBB is applied to this P # 130 via the P + impurity field 132. By setting N # 118 first, the noise generated in P # ll3d can be absorbed, preventing the noise from being transmitted to other internal circuits. Of p # 13〇. Fig. 4C shows another configuration of the cross-sectional structure taken along the line A-A of Fig. 4A. In FIG. 4C, the MOS transistors 113d and 114 are formed in p # n3a formed on the surface of the p-type semiconductor substrate 120. On this p # n3d surface, N-type impurity regions 119 are formed spaced apart from each other. These impurity regions 119 are connected to the signal line 1Ua and the output signal line 115 alternately, respectively. A gate electrode layer is formed on the surface of P # 113 in the heterogeneous region 119. The substrate bias voltage VBB is applied to the surface of this P # 113a via the P + impurity region 117. Along the periphery of this impurity region 117, an N-type impurity region 118 is formed in P # 113d. It is a positive voltage, and a negative substrate bias voltage vbb is biased to P # 113 through the impurity region 117. When noise occurs in P # 113d, it is caused by the junction formed between p # 113d and the impurity field Π8 24 丨 Zhangzhong ^ ~ National Standard (J) M Specification (210 &gt; &lt; 297 mm) —-— --- (Please read the precautions on the back before filling out this page) -Installed. Vs. β Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 -------_ I. V. Invention 5 (22) ^ ~~~ Capacitive noise generated by the internal circuit in this P #. In the P # U3d where MOS transistors 113 and 114 are formed, absorption noise is applied to the outer periphery of the P # U3d. The method of bias voltage VCC2 can be used to generate noise generated by the internal circuit in P # formed by other internal circuits (by the capacitor, the noise transmitted from the impurity field 119 toward P # li3d). The MOS transistor 114 is separated from the MOS transistor 113 shown in FIGS. 4B and c through a field insulating film (not shown) and is formed in the same p # U3a.

Inside. The active region 113a shown in FIG. 4A is a region in which the impurity region 119 shown in FIG. 4B or 4C is formed. In particular, in the case of the structure shown in FIG. 4C, when a loss-increasing device is provided near the output circuit, the power field noise of the internal circuit can be reliably used by the loss-increasing device 118 through the impurity field 118, thereby preventing the influence of the power-supply noise. It is transmitted to other internal circuits formed in P # 130. In the following description, the 'output circuit may have a cross-sectional structure of any of Figs. 4B and 4c. [Embodiment 丨] Fig. 5 is a diagram showing the structure of a main part of a semiconductor device raised according to the present invention. In FIG. 5, the internal circuit 102 is self-coupled to the power line M2a of the loss increaser 14a that receives the power supply voltage Vcc, and bears one side operation power voltage; and is self-coupled to the loss increaser 144a that receives the ground voltage GND. The ground wire 146a bears the operating power voltage on the other side. A capacitor C1 having an effective capacitance 値 (about several hundreds pF) is connected between the power supply line 142a and the ground line 146a. The output circuit 104 is installed separately from the loss increaser 14〇a and can withstand the power supply 25. This paper is suitable for paper size} ----- (Please read the precautions on the back before filling this page) Printed by employee consumer cooperatives A7 ---------- B7 V. Description of the invention (23) ~~~~ ~ ----- The loss increaser of voltage Vcc belongs to the action power voltage on one side through the power cord ㈣ And the q-losser 144b, which is provided separately from the loss increaser, and which bears the ground voltage GND, bears the action power of the other side via the ground wire. The node VCC1 of the operating power supply voltage for charging and discharging the output node of the output circuit 104 of Chengwen (the node is represented by the same symbol and the voltage fed to it) is the node VCC2 of the bias voltage used by Chengwen to absorb noise. Commonly connected to 14 holes of the power cord. Between the power source, the spring 142b and the ground line 146b, no capacitor having an effective capacitance 値 is provided, and only a drift capacitance &amp; This drift capacitor has a capacitance of about PF, and the power line is difficult to be grounded. Table 146b is separated by the sense current method. Since the potential change due to capacitive coupling is proportional to the capacitance of the capacitor, it is known in the meter of the drift capacitor Cs that even the one of the power supply line 142b and the ground line 146b is miscellaneous. The amount of noise transmitted to another is also very small. The state in which the capacitance is only light-weighted by this -drift capacitor is called "the AC method is separated". In the configuration shown in FIG. 5, the output circuit 104 operates and uses the current on the power supply line 142b. Even if the power supply of the power supply line 142b is repeatedly reduced (including both the voltages VCC1 and VCC2), this potential reduction does not Will be transmitted to the ground line 146b, the ground line 146b is a ground voltage GND which is stably maintained at a fixed voltage level. Therefore, the source voltage of the M0S transistor that discharges the output node of the output circuit 104 to the ground voltage level will not change. Its gate voltage is the same as the display voltage. The crystal 114 is turned on. 26 This paper size applies the Chinese national standard (CNS τΐϋ; grid (training for 7 meals (please read the precautions on the back before filling out this page). Packing-

'II line Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs

J description (24) ... When the CM0S transistor constitutes the wheel circuit, even if I1 = the grounding voltage is the discharge current when the wheel is discharged at the node, the voltage on the power source and the spring 142b can be maintained-constant voltage Level. Because 'may: stop here—p channel for charging the drive signal = the situation where the current is supplied to the input point that should be discharged, and can be: two =' point is driven to a low level. Also, at that time, you can By suppressing the through current flowing from the node W 3 point 1113) to the ground node GND (the node Ulb in FIG. 3), the current consumption can be reduced. 'When the circuit 1 () 2 &lt; operates, the recording circuit ⑽ is compared, the load of the internal node to be driven by the internal circuit 102 is much smaller, so the amount of noise on the power line 142a and the ground line 1463 It is very small and the change is gentle. Its power noise can be absorbed by capacitors and finches. 'FIG. 6 is a diagram showing a quick connection form of a loss increaser and a plug terminal (lead frame). In FIG. 6A, the power supply loss increaser 1501 of the internal circuit 102 is electrically connected to the plug terminal 152 via the bonding wire 151a. In addition, a power supply for the output circuit 104 is provided to the attenuator] and is electrically connected to the same plug terminal 152 via a bonding wire. Here, the power supply loss increasers 15a and 150b indicate one of the power supply voltage Vcc or the ground voltage. In the following description, when the power supply voltage Vcc and the ground voltage GND are collectively indicated, the term "power supply" is used. In the structure shown in this figure, a common plug terminal is used to feed the power supply voltage to the internal circuit 102 and the output circuit 104. During the operation of the output circuit 104, even if a power noise is generated, and the power noise is transmitted to the power supply via the bonding wire 152, the plug terminal 152, and the bonding wire 151a, the power supply is increased by 27 CNS. )

B7 ----- V. Description of the invention (25 For the loss increaser and C1, the internal circuit of this power source is a miscellaneous stone, and the operation of the valley is not good. _ The movement of the 102 and its miscellaneous power = The line resistance and the drift capacitance of the wiring can slow down the circuit power supply and the dramatic changes. However, the internal change of the capacitor is used: the connection form of the 1 π power supply loss increaser and the plug terminal = 1. Figure 6 " The electric green supply loss increaser 增 and ㈣ α ^ spring 15U and 151b are connected to the respective plugs ^ 152b ° in the salt-connected form, the ^ recording line for the output circuit 104 and the internal circuit 1 (^ power supply) The supply line is reliably cut off. When the circuit 1G4 operates, the generated power noise can be prevented from being read on the internal circuit and the source supply line. Figures 7A and B show the The layout of the attenuator is shown in FIG. 7A along the outer periphery of the device main body forming portion 162 of the semiconductor wafer 160. The attenuator ⑽ is arranged along the periphery of the device. The loss increaser PD of the semiconductor crystal # 16〇, but the loss increaser PD can also be configured all This—the i-th power source potential outer periphery. Appropriate loss increasers in the loss increaser PD can be used as power supply loss increasers. In FIG. 7B, an increase is arranged at the central portion of the semiconductor wafer 160 in the horizontal direction. Loss device PD, semiconductor devices are arranged on both sides of the loss || PD column, and there are main body forming areas 162a and 162b. By placing the loss increaser pD in the central portion of the semiconductor wafer 160, the loss increaser can be occupied The area is more reduced than that shown in Figure 7A. (The loss increasers are arranged in a 28-sheet format, which is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) —.1 ”-II n ί I—- I. (Please read the notes on the back before filling this page)

-II The central standard of the Ministry of Economic Affairs is printed for employees 'cooperatives ----------------- A7 V. The central consumerism cooperative of the Central Standards Bureau of the Ministry of Economic Affairs prints B7 Invention Description (26) 歹!)' And The area of the wafer 160 is reduced. In the gain | loss configuration shown in FIG. 7B, a suitable gain increaser in the reducer PD is also utilized as an electric noise supply gain increaser. Usually, a power supply booster for the output circuit is arranged near the output circuit, and for the internal circuit, the power supply booster for the internal circuit is prevented from applying a power supply voltage to the internal circuit. In the following description, the configuration of the loss increaser and the connection of the loss increaser and the plug terminal can use these Figures 6A and B and Figures 7A and B and any combination thereof. FIG. 8 is a diagram showing an example of a specific configuration of the capacitor C1. In FIG. 8A, the capacitor sci is composed of a MOS (Insulated Gate-type Electric Field Effect) transistor having a gate connected to the power line, a source connected to the ground line 146a, and a drain. By forming the capacitor C1 with an M0S transistor, a capacitor having a low occupation area and a large capacitance can be realized. Fig. 8B is a view showing a planar layout of the MOS transistor shown in Fig. 8A. 8C is a diagram schematically showing a cross-sectional structure taken along the line B-B shown in FIG. 8B. In Fig. 8B, the power supply line 142a and the ground line 146a are arranged parallel to each other. These power supply lines 142a and 146b are formed of, for example, a second-layer wiring layer. A gate electrode layer 170a of a MOS capacitor is formed below the power supply line 142a. The hafnium electrode layer 170a is connected to an intermediate layer ma made of a first aluminum wiring layer through a contact hole 172a. This intermediate layer 171a is connected to the power line 142a through the contact hole 173a. The high-concentration impurity region (source and drain) in the outer periphery of the gate electrode layer 170a is immediately after the first aluminum wiring layer n5a through the contact hole 174a. This wiring layer n5a extends to the lower portion of the ground line 146a, and is connected to the ground line 146a through a contact hole i76a. By forming a MOS transistor, it can be viewed from the plan view with a power source. 29 Good paper size is applicable to Chinese National Standard (CNS) A4 specification (210X29 * 7 mm). Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economy. Note (27) The method of overlapping the lines 142a can reduce the area used to form the capacitor. In FIG. 8C, the MOS capacitor includes high-concentration N-type impurity regions 178a and 178b formed on the surface of the semiconductor substrate field (semiconductor substrate or #field) 177a, and these impurities are formed through a gate insulating film (not shown) The gate electrode layer 170a on the substrate region 177a between the regions 178a and 178b. The gate electrode layer 170a is connected to the intermediate layer 171a through a contact material formed in the contact hole 172a, and the intermediate layer 171a is connected to the power line 142a through a contact material formed in the contact hole 173a. The impurity regions 178a and 178b are connected to the wiring layer 175a via a contact material formed in the contact hole 174. In the arrangement shown in FIG. 8B, a contact hole 174a is formed to surround the gate electrode layer 170a. Therefore, the impurity collars 178a and 178b are shown connected to the periphery of the gate electrode layer and formed. These impurity regions 178a and 178b can also be separated from each other. FIG. 9 is a diagram showing the structure of a power line 142b, a ground line 146b, and a ground line 146b for an output circuit. As shown in FIG. 9A, the MOS capacitor is also formed for the power supply line 142b and the ground line 146b for the output circuit. The source and drain regions of the MOS capacitor (also the impurity regions formed around the gate electrode layer) are connected to the ground line 146b. However, the gate electrode layer of this MOS capacitor is not connected to the power line 142b, and the gate electrode layer is in an electrical drift state. Thereby, no capacitive coupling between the power line 142b and the ground line 146b is formed. FIG. 9B shows the planar layout of the MOS capacitor shown in FIG. 9A. Fig. 9C schematically shows a cross-sectional structure taken along a line C-C in Fig. 9B. This arrangement shown in Figure 9B, except for the reference symbol attached at the end with b instead of a and 30 medium paper sizes applicable to China National Standards (CNS) A4 specifications (210X297 mm) (Please read the note on the back first (Fill in this page again)

-IT Α7 Β7 Printed by the central government of the Ministry of Economic Affairs. Printed by the Consumer Cooperatives of the Bureau of Standards. 5. Description of the invention (28) There is no contact between the interlayer 171b and the power line 142b, and they are all arranged in the same plane as the MOS capacitor shown in Figure 8B. the same. The cross-sectional structure shown in FIG. 9C is also the same as the cross-sectional structure shown in FIG. 8C, except that the reference symbol attached to the end is replaced by b and there is no conductive material formed by a contact hole between the intermediate layer Π lb and the power line 142b. Other than that, it is the same. By forming the MOS capacitor method for the power supply line 142b and the ground line 146b for the output circuit, it is possible to use the conventional semiconductor device to form an arrangement of the capacitors for the power supply line for the output circuit. Only in the manufacturing step, the contact portion between the gate electrode layer of the MOS capacitor and the power supply line 142b is not formed. Therefore, the manufacturing steps for conventional semiconductor devices need not be significantly changed to realize the structure of the increase of one. In the MOS capacitor shown in Figs. 8 and 9, an n-channel MOS transistor is used. A p-channel MOS transistor can also be used as a MOS capacitor. When this P-channel MOS transistor is used, the gate electrode layer is connected to the ground line, and the impurity area (source / drain area) is connected to the power line (for the capacitors of the internal circuit; for the output Circuit, the power supply line is separated from the impurity field. "As mentioned above, according to the invention, the power supply line of the output circuit and the ground line signal form an AC-coupled state, which prevents the power supply when the output circuit is operating. Noise is transmitted to the power supply line on the other side of this output circuit, so that the output circuit can be operated stably. [Embodiment] FIG. 10 is a diagram showing the configuration of the main part of a semiconductor device according to Embodiment 2 of the present invention. For this semiconductor device shown in Figure 10, except for 31 (please read the precautions on the back before filling this page) h. The line paper is from the applicable Chinese National Standard (CNS) (210X297 ^ 7 Central Ministry of Economic Affairs) Printed by the Consumer Bureau of Standards Bureau A7 —_____ — B7 V. Description of the Invention (29)-The internal circuit 102 and the output circuit 104 are commonly provided with a power supply increaser 140 and a ground increaser 144 彳, the others are the same as the semiconductor dress shown in _ 5. Even the power supply for internal circuits, wires, and power supply circuits for power-out circuits 142b are commonly connected to this power loss increaser 14 〇, and the internal When the circuit ground wire 146a and the output circuit ground wire _ are commonly connected to the ground attenuator 144, the electric green wire 142b and the ground wire _ are separated from each other by the parent stream method, so the circuit 104 operates in turn. In this case, it is also possible to prevent the power line noise on one side of the power line U2b and the ground line 146b from being transmitted to the other side. At this time, it may be considered that the power noise generated by the power line 14 is transmitted to the booster 140 to the The situation of the power line 142a of the internal circuit 102. However, by the wiring resistance and wiring drift capacitance of the power supply line 14 holes, the attenuator 14o, and the power line 142a, this power supply noise can be reduced, and the The change speed is gentle, and the power supply noise is absorbed by the capacitor C1 coupled between the power supply line and the ground line 146b. When the turn-out circuit 104 operates, the power supply noise on the power supply line 1421) is the power supply voltage <potential reduction 'And the electricity on the ground wire 146b The source noise is that the ground voltage GND &lt; potential material rises, and only noise which can be compensated by the capacitor is generated. As described above, according to Embodiment 2, even in the turn-out circuit and the internal circuit, both are provided in common. In the case of power supply gain and ground loss increaser, it is also possible to prevent the output circuit from being installed in the output circuit by not providing a capacitor between the power supply line 142b and the ground line 14 接地 for the output circuit (the AC method is separated). &lt; Power noise generated during operation has a loud effect on internal circuit 102. Silicon 32 n-rl-li— I In un ——I y (Please read the precautions on the back before filling this page)-Order ---line-

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HI I Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (30) [Embodiment 3] Figure 11 is a diagram showing the structure of the main parts of a semiconductor device according to Embodiment 3 of the present invention. In FIG. U, a power source, a gain increaser 140a, and a ground gain increaser 144a are provided for the internal circuit ι02, and a power supply gain increaser and a ground gain increaser ⑽ are provided for the turn-out circuit 104. The internal circuit is moved from its power supply destructor 140a to the power supply voltage Vcc via the power line, and it is self-grounded to the increaser! 44a via ground wire! The wheel bears grounding electricity, ㈣. A capacitor C1 is connected between the power supply line 142a and the ground core. The output circuit 104 is provided with a power supply gain booster i 分别 separately from the power supply gain booster, and bears the power supply voltage VeC at its operating power node vcci via the power line 142b; and it is connected to the ground gain gain booster U4a separately. The device M4b bears the X ground voltage GND at its ground node and point via the ground wire. The output circuit 104 is connected to an internal circuit bias power supply line 142 for noise absorption of the power supply gain booster UOa. The bias voltage Vr2 (sleeve voltage VCC2 for receiving noise) is separated from the power line 142b and the ground line 146b, and no capacitor is provided. Even if the output circuit 104 operates, the potential of the power line U2b decreases, « Bias and noise-biased power supply lines_ are connected to different gain reducers 丨 Yang and 14 () a, respectively, and the noise-absorbing bias voltage VCC2 is kept stable at a certain voltage level The voltage VCC2 for noise absorption is applied around the output circuit as shown in Figure 4C or 4C. Therefore, it is possible to prevent the bias and the source voltage VCC2 from changing when power noise is generated. However, this power noise is difficult to be transmitted to the internal circuit via the P-type semiconductor substrate (refer to FIGS. 4B and 4C).

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (31) When the circuit 104 is activated, noise from the power supply will affect the internal circuit 102. In addition, it is possible to suppress variations in the bias power supply voltage VCC2 and variations in the bias voltage VBB, thereby causing variations in the substrate bias voltage VBB applied to the P # formed in the internal circuit, and preventing malfunction of the internal circuit 102. Also, as in the previous embodiment, since the power supply line 142b and the ground line 146b of the output circuit 104 are separated by an AC method, the influence of the power supply noise internal circuit 102 of this output circuit 104 can be suppressed. In addition, this bias power line 142c may not be coupled to the attenuator 140a, but may be a part of the power line 142a connected between the internal circuit 102 and the capacitor C1. That is, when the power loss increasers 140a and 140b are connected to the same plug terminal, and the power noise is not transmitted to the power line for the internal circuit by the plug terminal as an internal circuit, this power noise is also absorbed by the capacitor C1. The bias power supply voltage VCC2 can be stably supplied without being affected by power supply noise. As described above, according to Embodiment 3 of the present invention, the bias power supply line that transmits the bias voltage for noise absorption of the output circuit 104 is transmitted. The power supply gain increaser for the internal circuit, which is separately coupled to the power supply gain increaser for the output circuit, is not affected by the power noise during the output circuit operation, and is supplied stably, which can prevent this bias for noise absorption. The influence of the change in the voltage VCC2 on the internal circuit 102 can further suppress the influence of power noise on the internal circuit 102 when the output circuit 104 operates. In addition, since the power lines 142b and 146b are separated from the output circuit 104 in an AC manner, even when the output circuit 104 is operating, the power supply is miscellaneous 34 (please read the precautions on the back before filling this page). Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (32) '一' —-~ The news occurred on the side of the power supply line In this case, this power noise can be prevented from being transmitted to the power supply line on the other side. [Embodiment 4] FIG. 12 is a diagram showing the main components of the semiconductor device according to Embodiment 4 of the present invention. In the configuration shown in FIG. 12, a power supply gain increaser 接地 and a ground gain increaser 144 are provided in common for the internal circuit 102 and the input A circuit 1G4. The internal circuit 102 is powered by the power line, and the power supply phase device M0 receives the power supply voltage Vcc as one side of the power supply. ^ Self-grounded gain increaser] 44 receives the ground voltage via the ground line 146a as the other side of the operation. voltage. The output circuit 104 receives the power supply voltage ν "from the power supply booster 14 through the electric switch 142b as the action power supply voltage vccl on one side, and the ground gain increaser 144 receives the ground voltage GND as the other side through the power cord i Power supply voltage. The power supply line 1423 of the internal circuit 102 is divided by the connection node NA of one of the side electrodes of the capacitor ci, which is divided into the first part 142aa connected to the power supply destructor 140 and the internal circuit 102 Part 2 l42ab. The bias power line 142e used to convey the bias voltage used to absorb noise to the output circuit M # is provided separately from the power line ⑽, and the second part of the power line 142a connected to this internal circuit 142 仏. The power line 142b is separated from the ground line 146b in an AC mode. When the output circuit 104 operates and the power line 142b generates power noise, this—power noise may be transmitted through the gain increaser 142. To the power line 142a, the first! Part 142aa. However, the power noise transmitted to this part i M can be added to the capacitor 0 for the internal circuit 102. _ 35 paper ruler __T ^ TT4i (21Gx.2 ^ y ---, -------- loaded __% (Read the back of the precautions to fill out this page) A7 set by the Central Bureau of Standards Μ workers elimination f Lloyd PRINTED

B / Description of the invention (33) Absorption. Therefore, it is possible to prevent electric noise generated when the output circuit 104 is operated from being transmitted to the bias power line 142c, and the bias voltage VCC2 can be kept at a certain voltage level satisfactorily. It can prevent the influence of the internal circuit of power noise generated during the turn-out circuit 104: operation. As described above, according to the fourth embodiment of the present invention, in the case where a power loss increaser is provided in common to the internal circuit and the output circuit, the power supply line for supplying the output circuit (the operating power voltage and the bias power line for absorbing noise) are used. Separately set, and connect this bias power line to the second part of the internal circuit power line, so the power noise generated during the output circuit operation will be absorbed by the capacitor of the internal circuit to prevent power The influence of noise on the bias voltage can stably supply the bias voltage. In addition, since the power supply line and the ground line of the output circuit are separated by an AC method, the same effect as that of the second embodiment can be obtained. [Embodiment 5] Fig. 13 is a diagram showing the main configuration of a semiconductor device according to Embodiment 5 of the present invention. In FIG. 13, an electrotherapy loss increaser 14a and a ground loss increaser 144a are provided for the internal circuit 102, and a power loss increaser is separately provided for the wheel-out circuit ^ separately from these loss increasers 140a and 144a. 4 〇bf ground loss increaser 144b. The internal circuit 102 is the same as the previous step up to 4. It receives the power supply voltage Vcc from 40 as the power supply voltage via the power supply line 142a via the power supply booster 142a, and receives the ground voltage from the ground booster 144 through the ground line 146a. GND is used as the operating power voltage on the other side. A capacitor cj is connected between the electric green line 142a and the ground line 146a. The turn-out circuit 104 is installed from the power loss increaser 140 through the power cord 14 沘 36 --------------- Γ 丨-one '(please read the precautions on the back first and fill in different Original order) Order ---- -line ----- 111 m · Paper-like ^ Applicable to cns Α4 »(ηοχΊ ^^ γ A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (34) The power loss increaser 140b receives the operating power supply voltage VCC1 on one side, and the self-ground loss increaser 144b accepts the ground voltage GND as the other operation power supply #. This-output circuit 104 is further provided by a bias provided separately from the power line ⑽. The power supply line 142c is pressed, and the power supply voltage Vcc received from the rib of the power supply attenuator 14 is a bias voltage vcc2 for absorbing noise. The noise absorption power supply line 142c and the power supply node VCC2 are interposed therebetween. Resistance =, and is connected between the bias power line 42c and the ground line 1, the container C3. By a resistor R3 and the capacitor ^ to form a low-pass wave filter, the power noise on the bias power line 142c, It is absorbed by a low-pass wave filter composed of this resistance scale and capacitor C3. Power supply noise is caused by a sharp current The high-frequency component is generated and filtered by a low-pass chirp. The resistor is composed of, for example, polycrystalline seconds, and is electrically connected to the wiring layer constituting the bias power line 142c. The resistor R has, for example, several K Up to several tens of KΩ &lt; resistance 电容器. Capacitor C3 is composed of the M⑽ capacitor described in the previous embodiment, and its capacitance has a size of hundreds of pF. The capacitance of this capacitor C3 is the same as for the internal circuit. The capacitor C1 set at 10 has a size of approximately 4 JS]. Therefore, power noise during the operation of the output circuit 104 can be absorbed by this capacitor C3. The operation of the output circuit 104 When power noise is generated on the power line l42b, and this power noise is transmitted to the bias power line 142c, the power noise can be mixed with a low-pass filter formed by a resistor R and a capacitor C3. The filtering process can prevent the power noise from being transmitted to the bias voltage supply node ν (χ2 of the output circuit 104. Therefore, it can be suppressed in the turn-out. Please read “I read I 1” first | II | II [事 II r Fill II gutter 37 paper ruler面面 家 髀 (V. Description of the invention (35 in Circuit 104) The 1 piezoelectric MCC2 during the operation of the output circuit 104 affects the internal circuit movement. ^ This system = electricity: implementation Form 5, because the power circuit is set for the circuit board / feeding branch, and the low-voltage data line is installed on the power supply line, it can prevent the output circuit from moving: J = power supply, noise and bias lightning It can affect the output ㈣η, and can supply the bias voltage stably to the two IS shadows: This is a bias circuit. The circuit device and the ground loss increaser are each connected to the internal circuit and miscellaneous circuits. The power noise during the inspection ^ circuit operation is transmitted to the internal circuit. [Embodiment 6] Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs = 4 is a semiconductor device showing Embodiment 6 according to this issue. Invention &lt; In the sixth embodiment, when the output circuit is operating in the same phase as in the fifth embodiment, even if it is switched on, it can be expected to have low pass money. —Set the &lt; voltage level, and can prevent the electrical transmission generated during the operation of the circuit:

[Embodiment 7J] Fig. 15 is a diagram showing the configuration of essential parts of a semiconductor device according to a seventh embodiment of the present invention. In the configuration shown in FIG. 15, a power gain increaser and a ground gain increaser ⑷a are provided for the internal circuit = 2, and these gain increasers 140a and 144a are separately provided for the turn-out circuit 104. It is difficult to provide a power loss increaser 140b and a ground loss increaser. In the same manner as the configuration shown in Fig. 13, the internal circuit 102 receives the power supply voltage Vce from the power supply attenuator 140a via the power supply line 142a as the -side operating power supply voltage. The self-grounded gain 144a bears the ground voltage GND as the power supply voltage on the other side. The turn-out circuit 104 is a self-power loss increaser 14b, and the power supply Vcc is received through the power cord 14 hole as one side. GND is used as the operating power supply voltage of another it. The output circuit 104 is provided with a bias power line 42c that transmits the power supply voltage Vcc as a bias voltage for noise absorption. The bias power line 142c is provided with a low-pass filter in the same manner as that shown in Fig. 13, for example. This low-pass filter includes a resistor R interposed in the bias power line M2c, and is connected between the bias power line 142c and the internal circuit i02 39. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) II-^ ---- ίβ ----- '(Please read the precautions on the back before filling out this page) mnm ί. Line -----------

I— I I I HI n · • I— «! — A7 B7 V. Capacitor C3 between the ground wire 146a (or the ground booster 144a) of the invention description (37). When the output circuit 104 operates and a power noise is generated on the power line 142b, the power noise is absorbed by a filtering process using a low-pass filter formed by the resistor R and the capacitor C3, and the bias voltage vcc2 remains fixed. Voltage level. During the operation of the output circuit 104, even if power supply noise is generated on the ground line 146b, the ground level of the ground line 14 讣 is repeatedly &lt; the potential level is increased. In this case, because the ground is increased and the ground is damaged The devices 144a are provided separately, and it is possible to prevent the power supply noise generated on the ground line 14 from being fed back to the bias power line 142c through the capacitor c3 constituting the low-pass filter. Therefore, even when power supply noise is generated in any of the power line 142b and the ground line 146b during the operation of the circuit ι04, a low-pass data wave receiver (resistance R and capacitor ⑼, for The power supply noise is filtered and absorbed, and the bias voltage can be kept at a certain voltage level stably. In addition, because the power supply, the line 142b and the ground line are separated by the AC method, this output circuit can be prevented. The power noise during the 104 operation is transmitted between the power line l42b and the ground line i46b. As described above, according to Embodiment 7 of the present invention, it is printed out for the internal circuit and the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The circuit is provided with a power gain reducer and a ground gain reducer respectively, and a low-pass chirp is provided on the bias power line that transmits the bias voltage to the output circuit, and the capacitor of this-low-pass wave filter is connected to Between the bias power line and the ground wire for the internal circuit, even if the power noise occurs when the output circuit is operating on the ground line, it can prevent this power noise from affecting the bias electric mill. Zhang Applicable to China National Standard (CNS) M specification 210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 ----- B7 V. Description of the invention (38) In addition, because the power line and grounding line of the output circuit Since it is separated by the communication method, the same effect as that of the first embodiment can be obtained. &gt; [Embodiment 8] Fig. 16 is a diagram showing the structure of a main part of a semiconductor package according to Embodiment 8 of the present invention. In the configuration shown in FIG. 16, a power supply gain booster 14 and a ground gain booster i 44 are provided in common to the = circuit 102 and the output circuit 104. The internal circuit i 02 is connected to the power supply voltage Vcc ′ via the power supply line and the line power source 140, and to the ground voltage GND via the grounding line loss 144 via the ground line. The wheel-out circuit 104 receives the power supply voltage Vcc from the power loss increaser 140 through the two holes of the power line, and acts as 1 vcc as the operating power voltage vcc, and receives the ground voltage GND from the ground loss increaser 144 as the other side via the ground line 146b. Operating power supply voltage. A bias power line μ for transmitting a bias voltage for noise absorption of the output circuit 104. This is the case-the power cord 142b is provided separately. ^ The structure shown in FIG. 16 is different from the structure shown in FIG. 14. The capacitor constituting the low-pass filter provided on the bias power line 142 c is connected to the gain increase connected to the ground gain increaser M4. The resistor and bias power K 电源 M # are provided with a resistor R. A capacitor C3 constituting a low-pass filter is connected to the ground attenuator 144 and a ground attenuator 144 for supplying a ground voltage GND as another side operating power voltage, and a random ground attenuator 144c and a bias power line 142c are provided. In this way, in the ground line 146b, a power signal is generated during the operation of the wheel-out circuit 104, and the voltage level of the ground voltage GND is raised. This capacitor is not affected by the power noise, so it can be Prevent miscellaneous electricity from flowing through this grounding wire (please read the precautions on the back before filling out this page). Pei 'Ding,-° wire Φ 41 Wood paper dimensions are applicable to China National Standard (CNS) A4 specifications A7 B7 V. Description of the invention (39) The source noise acts on the output circuit just after the voltage vcc becomes the output circuit PD), and Yu Chengru sounds at the dummy ^ ^ ^ ^ It can be absorbed by the low formed by capacitor C3 and resistor R ', which can also suppress the influence of power noise on the bias voltage VCC2.蚵 The bias voltage is therefore implemented in accordance with the condition „8, which is in addition to the effect of the configuration shown in FIG. 14 as shown in FIG. 14 and has a low pass separately from the loss increaser for the operation power supply. A special loss-increasing device for the wave device connects the low-pass k-wave electric transformer—the dedicated loss-increasing device and the bias power line, so it can also be used in the case of power noise on the ground line. Keep the out-of-circuit circuit absorbing noise and receiving the bias voltage stable at-constant voltage level; even if any power line and ground wire generate power noise during the operation of the out-of-circuit circuit, the bias voltage can also be set. Voltage loss 2 | The ground is kept at a certain voltage level, which can prevent the power supply noise generated during the output circuit from affecting the internal circuit. [Embodiment 9] FIG. 17 shows the main parts of the semiconductor device of the present invention. Structure diagram. In the structure shown in FIG. 17, the power amplifier 140a and the ground amplifier 144a for the internal circuit 102 are separately provided, and the power amplifier 140b and the ground amplifier for the output circuit 104 are separately provided. Damager 14. The internal circuit 102 is The power supply line 142a has been subjected to the power supply voltage Vcc as the operating power supply voltage on one side; and the ground gain 144a has been subjected to the grounding voltage gnD as the operating power supply voltage on the other side through the ground line 146a. Between the power line 142a and the ground line 146a 42 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) t I n ^ i-f — ^ — -1 / y! I —--(^ lf-: 1 (Please read the notes on the back before filling this page)-*-11 ^: 1 · -ι ~ ·· *. — 'βτ ------ ^ —— Staff of Central Bureau of Standards, Ministry of Economic Affairs Printed by the Consumer Cooperative-I II ί Hr Α7 Β7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (40) Quick-connect capacitor C1. The wheel-out circuit 104 receives power from the power amplifier 140b via the power cable 142b. The voltage Vcc is used as the operating power supply voltage VCC1 on one side, and the self-grounding attenuator 144b receives the ground voltage GND as the operating power supply voltage at the other side through the ground line 146b. The output circuit 104 is also a bias power line connected to the power attenuator 140a l42c, withstand the power supply voltage Vcc via a low-pass filter The bias voltage VCC2 for absorbing noise. The low-pass filter includes a resistor R inserted in the bias power line 142c, and a capacitor C3 connected between the bias power line 142c and the ground line 146a. Ink bias power line 142c It is completely separated from the power supply gain 140b and the ground gain 14 which are used to supply the operating power voltage of the output circuit 104. Therefore, even if the output circuit 104 operates, a power supply noise is generated in the power line 14 hole or the ground line 146b. It is not affected by this bias power line 142 ^, but can be kept at a certain voltage level stably. In addition, by setting a low-pass filter on the bias power line 142c, the following applies to the case where the voltage of the power loss increaser 14 generates noise: It absorbs and can stably supply a bias voltage VCC2 of a certain voltage level to the output circuit. Embodiment 9 of the second invention, because the power supply of the bias power line is provided to the loss increaser, it can be free from the influence of power transmission and transmission, and the bias electrical noise can be stabilized to the "electricity monitoring material". --- 43 (Please read the precautions on the back before filling out this page). Installation · ， 1Τ 1-It

Description of the invention (41 Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs [Embodiment Mode 10] FIG. 18 is a diagram showing the essential structure of a semiconductor device according to Embodiment 10 of the present invention. FIG. 18 is shown here. The structure shown is different from that shown in Figure ㈣. In order to power the I-line 142, a power supply gain and ground loss increaser 144e are provided exclusively. The capacitor C3 constituting the low-wave converter matches the power loss of the dedicated power supply. Device C and ground gain increaser 144c &lt; other components are not the same as those in FIG. 17, and the same reference numbers are attached to the corresponding parts. Here, «18 does not have the same structure, the bias power line &lt; The power supply booster UOc and the ground booster ⑽, such as the power gain booster for the internal circuit 触 touching the ground booster 与, and the «gain booster belongs to ground power loss booster for the power output of the wheel = 〇4 1440_set .: When the electric r and the internal circuit operate at 1 ° 2 ', even if the electric: voltage Vee or the ground voltage GND changes, it will not be affected by this, and it will be able to supply the -definite bias voltage vcc2. Until the turn out, even when the power noise is passed here—the power loss increaser is 14%, scaring The resistor R and the capacitor are used to apply wave processing to the noise of the power supply. ^ The sharp change of the low-pass wave can stably maintain the bias voltage. The bias voltage body is as described above, according to Embodiment 1 of the present invention. The noise absorption of Γ104 is biased, and a loss increaser and a ground loss increaser are set, so it can be suppressed in the wheel :: 4 original noises are used for the shadow caused by this bias voltage &lt; the power source is- The bias voltage VCC2 is transmitted to the inside and the noise can be suppressed. 44 This paper is suitable for mid-range home cleaning (CNS)

Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (42) '-[Embodiment Mode 11] Figure 19 is a diagram showing the structure of the main part of a semiconductor device according to Embodiment 1 of the invention; [ . In FIG. 19, the internal circuit 102 receives the power supply voltage Vcc as the one-side operating power supply voltage from the power supply booster 14a via the power line 142a; and the ground booster 144 &amp; receives the ground voltage GND as the ground voltage via the ground line 146a. Operating power supply voltage on the other side. Capacitor. It is connected between the power supply line 142a and the ground line 146a. The output circuit 104 is a power supply gain H 140b which is provided separately from the power supply gain increaser 14 through the power supply and the line 142b to withstand the power supply repeatedly-as one side operation power supply voltage VCC1 and noise suppression bias voltage VCC2, and If the ground attenuator 144c and the ground attenuator 14 are separately provided, they bear the ground voltage gnd as the power supply voltage of the other side via the ground line_. A capacitor C4 is connected between the node nb of the power line 142b and the ground node NC. A resistor R1 'is interposed between the node and the power supply booster] 40b, and a resistor R2 is connected between the node and the ground booster ⑽. The resistors IU and R2 each have a number ⑶ 疋 resistance 値. The capacitor HC4 has a capacitor 数百 of several hundred rushes. In the case read in FIG. 19, for the low-pass oscillating device transmitting the power noise from the power line, the capacitor C4 and the resistor R2 are used; and the container 4 and the resistor R2 function as The ground line 146b is a low-pass filter that transmits &lt; power noise. When the output circuit 104 "is in operation, when the potential of the power line is reduced," this-the node NB &lt; sister lowering shirt is transmitted to the money increaser shock. Here — the potential reduction of node_ is applied to China through the capacitor C4 towards the node j W scale. -------------- ^ ---. (Please read the precautions on the back before filling this page) . 丨 Line-I -1--j--I-I «II 11 A7 B7 Printed by the Consumer Cooperatives of the Central Commission of the Ministry of Economic Affairs. 5. Outline of Invention (43) ~~ NC was conveyed to the occasion by using capacitors. In the low-pass filter formed by c4 and resistor R2, this potential reduction is subjected to filtering processing and will not be transmitted to the ground attenuator 144c. When the output circuit 104 performs a discharge operation and the potential level of the ground voltage GND of the ground line 146b rises, the potential rise of the node Nc is not filtered by a low-pass filter formed by the capacitor C4 and the resistor R2. Conveyed to ground attenuator 1 44c. In addition, even if the potential of the node NB rises with the rise of the potential of this node because of the capacitor crying, it is possible to suppress the increase of the noise of this power supply to the power supply by the low-pass wave filter formed by the resistor R1 and the capacitor C4. The loss device 14b communicates. Therefore, the power noise received by this output circuit 104 when it is operated is transmitted to the power gain contactor touching the ground gain booster, and it can prevent the circuit from becoming a material. Special collection. By means of the circuit, the loss reducer 140 &amp; and 144a and the output circuit 104 gain increaser are set to prevent the power noise generated during the operation of this output circuit 104 from being transmitted to The power supply of the internal circuit 102 is supplied to the booster. As stated, according to the embodiment of the present invention, since a power supply gain increaser is separately provided for the output circuit and the internal circuit, and a low-pass data wave is provided between the loser and the power supply node of the output circuit. The power noise generated by the output circuit can prevent the power noise from being transmitted to the power supply line of the internal circuit during the turn-out operation. Circuit operation [Embodiment 12] ° Figure 2G shows the structure of the main part of the real family form 12 according to the present correction: t diagram. This—as shown in Fig. 2G, the structure of ㈣ 衣 ㈣ &;, except for the power loss increaser 46 Α specifications (2〗 〇〇; 297 mm)

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (44). 140 and ground gain increaser 144 are the same as those shown in FIG. 19 except that the internal circuit 102 and the output circuit 104 are provided in common, and the same reference numbers are attached to corresponding parts. As shown in FIG. 20, when the power supply gain increaser 140 and the ground gain increaser 144 are provided in common for the internal circuit 102 and the output circuit 104, low-pass filters are provided on the power supply line 142b and the ground line 146b, respectively. In this way, during the operation of the output circuit 104, the power noise generated by the power line 142b or the ground line 146b can be absorbed by this low-pass filter, and it can be suppressed from passing through the gain increasers 140 and 144 to the internal circuit. The power line 142a or the ground line 146a of 102 transmits the internal circuit 102 to operate stably. [Embodiment Π] Fig. 21 is a diagram schematically showing the structure of a semiconductor device according to Embodiment 13 of the present invention. In Fig. 21, a VBB generating circuit 200 for applying a bias voltage VBB to the substrate area is provided in common to the internal circuit 102 and the output circuit 104. The VBB generating circuit 200 includes: an oscillator 200a, which can generate a clock signal that changes between a high level (the power supply voltage Vcc level) and a low level (the ground voltage GND); the feed pump capacitance 200b, according to the oscillator 200a The output clock signal performs a chest action to change the potential of the node ND. The n-channel MOS transistor 200c is fixed to fix the high level of the potential of the node ND to the threshold voltage Vth level. The n-channel is used for the output. The MOS transistor 200d transmits the bias voltage VBB to the internal circuit 102 via the bias voltage transmission line 201a according to the potential of the node ND; and the n-channel MOS transistor 200e for output uses the bias according to the potential of the node ND The voltage transmission line 201b will have a negative bias voltage VBB 47. This paper size applies the Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page). / Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 ~ -------._ B7 V. Description of the invention (45) ~ _ Conveyed to the rotation circuit 104. The MOS transistor 200C is connected to the gate and one side of the conduction terminal at the% point NB ′ and the other side of the conduction terminal is manually connected to the ground node. The MOS transistor 200d for wheel output is connected to the bias voltage transmission line 20ia with its gate and one conduction node on one side, and the conduction node on the other side is connected to the bias voltage transmission line 201b, and the conduction on the other side The terminal is connected to the node ND. When the clock signal output from the oscillator 200a is at a high level, the potential of the node ND becomes a high level due to the capacitance of the feed pump. Once this node] ^] [) becomes a high level, the M0s transistor 200 c is turned on, and the potential of the node nd decreases to the voltage level of the threshold voltage vth of the MOS transistor 200c. The potential of the node ND is a positive potential level, so that the Mos transistor 200d and 200e become a reverse biased state and become an 0FF state. Once the clock signal output from the oscillator 200a becomes a low level, the potential of the node ND of the feed pump capacitor 200b decreases to the level of Vth_Vcc. In response to the reduction of the potential of this node ND, the Mos transistor 200d and 200Oe are turned on, and the difference between the potential of each of the bias voltage transmission lines 20la and 20lb and the potential of the node ND reaches once The MOS transistors 200d and 200 are below the threshold voltage Vth, and the MOS transistors 200d and 200e are in an OFF state. By repeating this operation, the potentials of the bias voltage transmission lines 201a and 201b will eventually decrease to a potential level of 2 · Vth-Vcc. In the configuration shown in FIG. 21, a bias voltage transmission line 20ib for transmitting the bias voltage VBB of the output circuit 104 is a bias voltage for transmitting a substrate bias voltage VBB of the internal circuit 102. Dust transmission line 2〇ja 48 This paper size is applicable to China National Standard (CNS) A4 (21〇 × 297mm) (Please read the precautions on the back before filling this page) • Binding and binding --- i in A7 ------------- Β7 V. Description of the Invention (46) ~~ — Individual settings. Therefore, the output voltage VBB of the output circuit 1 () 4 has changed. In this round, the bias and change of the bias call-out circuit 104 will not be transmitted to the internal circuit voltage VBB circuit 102, which can maintain the internal The bias voltage VBB is stable. 1 Circuit 102 As described above, according to Embodiment 13 of the present invention, since the transmission line and the output circuit are provided with bias transmission lines, respectively, it is rotated. Even if the substrate bias of the output circuit changes frequently, it can also suppress j Influence of the bias voltage of the internal circuit. [Embodiment 14] FIG. 22 is a diagram showing the overall configuration of a semiconductor device according to Embodiment u of the present invention. In FIG. 22, the secondary side generates a substrate bias voltage VBB through the low-pass detector 21 () to the output circuit 104. The low-pass filter 210 is provided near the output circuit 104. The substrate bias voltage from the VBB generating circuit 2000 is repeatedly vbb, and is fed directly to the internal circuit 102 via the bias voltage transmission line 201 without the low-pass filter 210. The low-pass filter 210 includes a series-connected resistor The components 21 oa and 21 ob ′ and a capacitor 21 oc connected between a connection node of the resistors 21 oa and 21 ob and a power supply node. The power supply voltage supplied to one side electrode of the capacitor 210c may also be the power supply voltage Vcc, and may be the ground voltage GND. In addition, the bias voltage transmission line 201 may be a single wiring, and as shown in FIG. 21, the output circuit 104 and the internal circuit 102 may be separately provided. When the output circuit 104 is operating and power noise occurs, 'Because of P 丼 and impurities in the substrate collar (Figure 4B and C impurities 49 books ^ Zhang Ruler> A4 specifications (2 丨 0X 297 mm) Please read Note. Please fill in the gutter on this page again. Printed by A7 __B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (47) Capacitive coupling between field 119 and P 丼 113d), the substrate potential changes. However, in this output circuit 104, even if the substrate potential changes and the bias voltage VBB changes, it can be filtered by the low-pass filter 21 to prevent the change in the bias voltage from being transmitted. To internal circuit 102. Furthermore, by supplying the substrate bias voltage from the VBB generating circuit 200 to the wheel-out circuit 104 via the low-pass filter 210, the substrate bias voltage can be stably supplied to the substrate of the wheel-out circuit 104. field. Therefore, the power supply noise generated during the operation of this output circuit 104 is absorbed by the substrate bias voltage VBB supplied in a stable manner, and the variation of the substrate potential in the wheel-out circuit 104 can be suppressed. In this way, it is possible to prevent the potential change in the substrate area of the output circuit 104 from being transmitted to the substrate area where the internal circuit 102 is formed via the semiconductor substrate 120 (refer to FIGS. 4B and C), thereby preventing the output circuit 1 The power supply Λ generated during the operation of 4 will affect the internal circuit 102. In addition, even if noise is generated in the bias voltage transmission line ^, the low-pass filter 21 can be used for filtering, so the noise is not transmitted to the wheel-out circuit 104, and the output can be constantly and stably maintained. The substrate bias voltage VBB of the circuit 104 is at a predetermined potential level. This is used to prevent noise from being transmitted to the substrate area of the output circuit 104, and printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and to suppress the power supply potential of the output circuit 104 from changing due to this noise. In addition, this structure shown in FIG. 22 can be used in combination with any of the previous embodiments i to 13, as long as a low pass is provided near the output circuit 104 to stabilize the substrate bias voltage VBB. The filter 21 is sufficient. This paper is suitable for A7 B7. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (48) As mentioned above, according to Embodiment 14 of the present invention, since a low-pass filter is provided near the output circuit 104, When the output circuit 104 operates, even if noise is generated in the substrate area, it is possible to prevent this noise from being transmitted to the substrate area of the internal circuit 102. In addition, with the arrangement of a low-pass filter, the bias voltage can be stably supplied to the substrate area of the output circuit. Therefore, even when power supply noise occurs during the output circuit operation, the potential in the substrate area can be stably maintained at a predetermined potential level, and this power noise is prevented from being transmitted to the internal circuit through the substrate area. [Embodiment 15] FIG. 23 is a diagram schematically showing the overall configuration of a semiconductor device according to Embodiment 15 of the present invention. In the configuration shown in Fig. 23, a VBB generating circuit 202a is provided for the output circuit 104, a VBB generating circuit 202a is provided for the internal circuit 102, and a VBB generating circuit 202b is provided for the internal circuit 102. As shown in FIG. 23, by setting the VBB generating circuits 202a and 202b to the output circuit 104 and the internal circuit 102, respectively, the substrate bias voltage of the output circuit 104 can be stabilized. Even if a power noise is generated during the operation of the output circuit 104, the potential of the substrate area of the output circuit 104 can be suppressed. Therefore, it is possible to prevent noise from being transmitted from the output circuit 104 to the internal circuit 102 through the substrate area of the semiconductor device. It is possible to prevent power noise from affecting the internal circuit 102 during the operation of the output circuit 104. In addition, it is assumed that when the output circuit 104 operates, noise is generated in the base circuit of the substrate. This noise can also be absorbed by the VBB generating circuit 202a provided for the output circuit 104. Therefore, in this output circuit 104, even if noise is generated in the substrate bias voltage VBB, it can also prevent 51 (please read the precautions on the back before filling this page), -5

This paper size applies to China National Standard (CNS) A4 (210X297 mm). Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7. 5. Description of the invention (49) This noise is transmitted to the substrate of internal circuit 102. field. As described above, according to the embodiment 15 of the present invention, since the VBB generating circuit is provided in the internal circuit and the output circuit, the substrate bias voltage of the wheel-out circuit can be stabilized, and it can be prevented from occurring during the operation of the output circuit. The power noise has an impact on the internal circuit. [Embodiment 16] FIG. 24 is a diagram schematically showing a configuration of a main part of a semiconductor device according to an embodiment of the present invention. The structure shown in Fig. 24 is the same as the structure shown in Fig. 23 except that a low-pass filter 212 is provided between the output circuit 104 and the VBB generating circuit 202a. This low-pass filter 212 filters and processes the substrate bias voltage generated by the circuit 202a produced by the ^ 8 production circuit, and then transmits it to the circuit 104. Therefore, even if noise is generated from the VBb generation circuit 202a, the low-pass filter 212 can be subjected to filtering processing to prevent this noise from being transmitted to the substrate area of the wheel-out circuit 104. With this, it is possible to stably maintain the substrate potential of the wheel-out circuit 104, absorb the variation of the substrate potential caused by the power supply noise during the operation of the output circuit 104, and prevent this power supply noise from passing through the semiconductor substrate. Circuit 1 affects. In addition, the low-pass filter 2 丨 2 can prevent the substrate bias voltage (due to the influence of noise) of the substrate area of the output circuit 104 from changing drastically, so it can suppress the variation of a substrate bias voltage. As a result, noise is transmitted to the internal circuit 102 via the semiconductor substrate. As described above, according to Embodiment 16 of the present invention, since a low-pass filter is provided at the output portion of the VBB generating circuit provided exclusively for the output circuit, the substrate bias voltage of the wheel-out circuit can be stabilized. 1〇4 action 52 National Standards (CNS) of the eighty-four husbands and daughters (executive chat chat director) &quot; ----- 7a ---, ----- 丨 installed --.---- order- ---- Line ----- 1, '* -Μ * f Please read the notes on the back before filling out this page}. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A 7 B7 V. Invention Description (50 ) When power noise is absorbed in the field of the substrate, it can prevent power noise from affecting the internal circuit. "In the structure shown in Figure 21 and Figure 24, when the present invention is applied to the internal buffer, it can also be Instead of VBB generation circuit, use a circuit that generates internal high voltage VPP (a higher voltage level than the internal operating power supply voltage) (where the internal buffer has a CMOS structure and high voltage is applied to its substrate collar). FIG. 25 is a diagram showing a configuration of a modified example of an output circuit in a case. Fig. 25A is a diagram showing a cross-sectional structure of this output circuit, and Fig. 25B is a diagram showing its electrical equalization circuit. In FIG. 25A, the output circuit is formed in P 丼 302 formed on the upper portion of the P-type semiconductor substrate 300. On the surface of P 丼 302, N 丼 303 is further formed. P + impurity regions 305a and 305b are formed on the N 丼 303 surface at a distance from each other. Between these impurity collars 305a and 305b, a gate electrode layer 306 is formed via a gate insulating film (not shown). N 丼 303 receives the bias voltage VCC2 through the N + impurity region 304. The P + impurity collar 305a withstands the power supply voltage VCC1. On the surface of P 丼 302, N + impurity regions 307a and 307b are formed apart from each other. A gate electrode layer 308 is formed on P 丼 302 between these impurity regions 307a and 307b via a gate insulating film (not shown). P 丼 302 is further subjected to a substrate bias voltage VBB through a P + impurity region 309 formed around the P 丼 302. The N + impurity region 307a is subjected to a ground voltage GND. The P + impurity collar 305b and the N + impurity region 307b are connected to each other. 53 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Binding and binding line Φ A7 __ 5. Description of the invention (51) This figure is shown in Figure 25A As shown in FIG. 25B, the π wheel-out circuit is provided with a CMOS structure composed of a P-channel MOS transistor PQ and an n-channel Mos transistor Nq. As shown in FIG. 25B, the source of the p-channel Mos transistor PQ is subjected to the power supply voltage VCC1, and the substrate region thereof is subjected to the bias voltage VCC2. The source of the MOS transistor NQ is subjected to the ground voltage gnd, and the substrate area is subjected to the substrate bias voltage VBB. In the case of the CMOS structure shown in Figs. 25A and 25B, the structures of the previous embodiments 1 to 16 can also be used. At this time, in FIG. 25A, in the boundary area of P 丼 302 and P-type semiconductor substrate 300, as shown in FIG. 4B or FIG. 4C, it is possible to form a useful structure to absorb noise &lt; N + Lingcheng (impurity Field or chirped field), and the bias voltage VCC2 is applied to the composition of the field for noise absorption. [Specific Example of Semiconductor Device] Fig. 26 is a view showing a specific configuration of a semiconductor device according to the present invention. This semiconductor device shown in FIG. 26 is composed of a logic circuit LSI that performs logic processing and a system LSI that is formed on the same chip as a memory LSI that stores data. Printed by the Consumer Affairs Cooperative of the Central Government Office of the Ministry of Economic Affairs In Figure 26, the semiconductor device includes a logic processing unit and a memory unit. The logic processing unit and the memory unit are provided with an input / output buffer circuit 400 for performing input and output of data and signals external to the device. The logic processing unit includes a logic circuit 402 that receives data and / or signals from the input / output buffer circuit 400 and a memory unit described later, and executes predetermined processing. The Billion Unit includes: storage unit rank 406, which has dynamic storage units arranged in rows and rows; DRAM control circuit 404, which controls the rank of this storage unit. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards, Ministry of Standards, A7 ____-____ B7 V. Description of the Invention (52) ~~~~~ '——— Access to 406; the character line driver is completely under the control of the dram circuit. The line (字) can be driven toward the selection state; and the amplifier 410 is used to sense and lock the data of the storage unit connected to the selected line in the reserve unit rank 406 and lock it. The logic circuit 402 applies predetermined logic processing only to the data read from the storage unit rank 406 or the data to be written. The 0-code control circuit 404 may be configured to control the storage unit selection operation of the storage unit rank 406 in accordance with the control signal and the address signal fed through the wheel-in / out buffer circuit 400. In addition, instead of adopting this, the logic circuit technology can be used as follows, that is, according to the data and control statements that are fed in through the round-out buffer circuit 400, and the data is given a predetermined treatment. , And write data to the storage unit rank 406 according to the control signal, and control the operation of the DRAM control circuit 404 according to the control signal. The DRAM control circuit 404, the word line driver 408, and the sense amplifier 41 ° correspond to the rank peripheral circuit 102b shown in FIG. J, and the DRAM control circuit 400 is based on the self-input buffer circuit 400 or logic. The circuit 402 feeds data and control signals and address signals to perform a storage unit selection operation. The amplifier 410 includes a sense amplifier circuit corresponding to each column (bit line pair) of the memory cell in the memory cell row 406. This sense amplifier circuit is provided with a lock-type sense amplifier, which is composed of a cross-light MOS transistor for amplifying the potential of a corresponding column (bit line pair) in a differential manner. For the logic circuit 402, the DRAM control circuit 404, and the word line driver 408, a power loss increaser I46d is provided in common, and the Chinese national standard (CNS) M specification (21〇 &gt; &lt; 297) is applied to the paper standard of the logic circuit. (Mm) (Please read the precautions on the back before filling in this page} Equipment, 1T_ €), A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (53) 402, DRAM control circuit 404 common formula A ground loss increaser 144d is provided. The logic circuit 402 receives a power supply voltage Vcc from one side via a main power line 142d and a sub power line 142da, and the ground voltage increaser 144d receives a ground voltage GND through a ground line 146fa. The DRAM control circuit 404 receives the power supply voltage Vcc from the power supply booster 140d via the main power supply line 142d and the sub power supply line 142ab, and receives the ground voltage GND from the ground booster 144d through the ground line 146fb. The word line driver 408 receives the power supply voltage Vcc from the power supply booster 140d through the main power supply line 142d and the sub power supply line 142dc, and receives the negative bias voltage VBB through the substrate bias voltage transmission line 201c. By using the external power supply voltage Vcc (2.5 V) as an operating power supply voltage, the logic circuit 402 and the DRAM control circuit 404 are operated, so that these circuits can operate at high speed. In addition, when the sense amplifier 410 has a time-sharing sense amplifier and is arranged between the bit line pairs, the DRAM control circuit 404 generates bit lines for separating the non-selected bit line pairs. signal. The high level of this one-bit line separation signal is higher than the high level in the memory cell rank 406 (in order to eliminate the critical 値 voltage loss of the separation transistor). Therefore, the DRAM control circuit 404 uses the power supply voltage Vcc. The word line driver 408 drives the selected word line in the memory cell rank 406 to a boosted voltage level (in order to eliminate the influence of the threshold voltage of the memory cell transistor). To generate such a boosted voltage, the power supply voltage Vcc is fed to the word line driver 408. The word line driver 408 accepts the negative bias voltage Vbb as the operating power supply voltage on the other side, and its purpose is to prevent the bit position from increasing due to the capacitive coupling of the non-selected word line in the memory cell rank 406, so that the non-selected Storage 56 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297mm) —J ------ IK —Packing ------ Order ------ Line (Please read the back first Please pay attention to this page, please fill in this page) 5. Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and the invention description (54) The transistor is turned on, causing memory charge to flow out.… For the sense amplifier 410, a power supply Loss device 14 and grounding phase increaser 144e. House drop circuit 412 will be lightly connected to this power loss increaser wo. The power line of it will be turned on and off to generate internal voltage Vd (L8V). Is supplied to the sense amplifier via the sense amplifier power supply line 143. Between the sense amplifier power supply line 143 and the power supply line, a switch 导 sw which is turned on in response to the control signal φ is provided. When power is applied to the semiconductor device ' Let this—the switching element be turned on In order to increase the internal reduced voltage Vd at a high speed, and before the operation of the sense amplifier, the switch element SW is turned on, so that the voltage level of the "supply voltage Vd on the sense amplifier power line 143 is reduced, and reading is suppressed. When the power supply voltage Vd decreases when the device is in operation, the readout operation is performed at a high speed. The power supply voltage on the other side of the amplifier 41 is fed from the ground attenuator 144e through the ground wire. Therefore, the sense amplifier drives the potential on the corresponding bit line pair) to the voltage level of the ground voltage GND and the internal step-down voltage Vd during operation. The voltage vd that has been internally reduced is used as the power supply voltage on one side of the sense amplifier 41, thereby 'comparing with the large area capacity of the storage unit ㈣4G6, so that the storage unit is miniaturized, and the storage unit transistor Insulation withstand voltage characteristics. For this-electricity '142d and 142e, separate devices C5 and C6 are provided, respectively. For the wheel in / out buffer ㈣400, the 4 sites are provided with a power supply, a reducer I40f, and a ground 増 @ H4f. The input and output buffer circuits are Gamma, which is from 谙 k.

I loading line 57 This paper size is applicable to the Chinese national standard (magic mm)

Printed by the Employees ’Cooperative of the Ministry of Economic Affairs, Central Government, and V. Description of the Invention (55) The power supply booster 104f is supplied with the power supply voltage Vcc via the power line 142f, and the self-ground booster 144f is supplied with the ground voltage GND via the ground line 146f . No capacitor for decoupling is provided for the power line U2f. The input / output buffer circuit 400 uses the power supply voltage Vcc from the power supply attenuator 140f and the ground voltage GND from the ground attenuator 144f as the operating power supply voltage. The bias voltage (VCC2) for noise absorption described in the previous embodiment may be any one as long as it can use the structure of any of the previous embodiments. It is particularly preferable that the input / output buffer circuit 400 includes only the output circuit connected to the final stage of the external plug terminal as described in the previous embodiment, and the primary wheel-in circuit coupled to the external wheel-in terminal. In the case of input / output data signals, this circuit 400 may also include a part which operates in response to the input / output signals of the control data. In the system LSI as described above, an input / output buffer circuit 400 is provided separately from a gain increaser of the internal circuit, especially a power supply booster U and a ground gain increaser for the turn-out circuit. The line is set back, and a capacitor is used. In this way, it can prevent this—the output noise from the buffer circuit (especially the output circuit) of the power supply from affecting the internal circuit. ⑶. As described above, according to the present invention, power supply noise generated during the operation of the output circuit and the internal buffer circuit can be prevented from affecting other internal circuits. (Brief description of the drawings) Figure 1 is a schematic showing the overall paper size of the semiconductor device to which the present invention is applied (please read the precautions on the back before filling this page). Installation--Threading ---- 逦 • 111 I 1 · 58 Printed paper A7 by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs --------- --B7 V. Description of the invention (56) ~ '~~ &quot;:-~~~- formula. Fig. 2 is a view showing another configuration of a semiconductor device to which the present invention is applied. FIG. 3 is a diagram showing a specific structure of a turn-out circuit shown in FIG. 1. — FIG. 4A is a plan view showing the layout of the turn-out circuit shown in FIG. 3, and FIG. 4B is a diagram showing a cross-sectional structure of π along the line of FIG. 4A &lt; A-A. Fig. 4C is a diagram showing a modification example of the cross-sectional structure taken along the line A-A in Fig. 4A. Fig. 5 is a diagram showing the structure of a main part of a semiconductor dress according to a real family form of the present invention. Fig. 6 is a diagram showing a connection form of a loss increaser of a semiconductor device according to the present invention and an external plug terminal. Fig. 7 is a diagram showing a configuration of a loss increaser of a semiconductor device according to the present invention. Fig. 8 is a diagram showing an electrical equalization circuit, a plane decoration and a cross-sectional structure of the capacitor shown in Fig. 5. Snow 々 9 is a diagram of the "equivalent circuit, planar layout, and cross-section structure" between the power line and the ground line of the 5 ^ turn-out circuit in Figure 5. = 1G shows the implementation according to the present invention Figure 2 shows the structure of the semiconductor device &lt; = 11 is a diagram showing the structure of the semiconductor device according to the third embodiment of the present invention.: 12 is the figure showing the requirements of the semiconductor device according to the fourth embodiment of the present invention. % &lt; Structure diagram. Fig. 13 shows the application of the main dimensions of a semiconductor device according to the fifth embodiment of the present invention--IT ------ κ \-n I · .'... (Please read the back first (Notes for filling in this page)

(1T line €) 59 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Illustration of the structure of the (57) Department of Invention. Fig. 14 is a diagram showing the configuration of main parts of a semiconductor device according to a sixth embodiment of the present invention. Fig. 15 is a diagram showing the configuration of main parts of a semiconductor device according to a seventh embodiment of the present invention. Fig. 16 is a diagram showing the configuration of main parts of a semiconductor device according to an eighth embodiment of the present invention. Fig. 17 is a diagram showing the configuration of main parts of a semiconductor device according to a ninth embodiment of the present invention. Fig. 18 is a diagram showing a configuration of a main part of a semiconductor device according to a tenth embodiment of the present invention. Fig. 19 is a diagram showing a configuration of a main part of a semiconductor device according to an eleventh embodiment of the present invention. Fig. 20 is a diagram showing a configuration of a main part of a semiconductor device according to a twelfth embodiment of the present invention. -Fig. 21 is a diagram showing a configuration of a main part of a semiconductor device according to a thirteenth embodiment of the present invention. Fig. 22 is a diagram showing a configuration of a main part of a semiconductor device according to a fourteenth embodiment of the present invention. Fig. 23 is a diagram showing a configuration of a main part of a semiconductor device according to a fifteenth embodiment of the present invention. Fig. 24 is a diagram showing a configuration of a main part of a semiconductor device according to a sixteenth embodiment of the present invention. Figure 25 is a cross-section 60 showing a modified example of the snubber circuit to which the present invention is applied (please read the precautions on the back before filling out this page)-Packing. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7-. ~~ ___! 7 V. Description of the Invention (58) &quot; ~~ --- Diagram of the structure and electrical equivalent circuit. Fig. 26 is a view showing a specific example of a semiconductor device according to the present invention. FIG. 27 is a diagram showing the structure of a conventional read-out circuit. FIG. 28 is a waveform diagram showing the operation of a conventional output buffer circuit. Fig. 29 is a diagram showing a power supply line of a conventional semiconductor device. FIG. 30 is a diagram for explaining a problem of the configuration shown in FIG. 29. FIG. 31 is a diagram showing a modified example of a conventional semiconductor device. FIG. 32 is a diagram for explaining a problem of the semiconductor device shown in FIG. 31. FIG. * FIG. 33 is a diagram for explaining specific problems of a conventional semiconductor device. FIG. 34 is a diagram showing a modified example of a conventional output buffer circuit. Fig. 35 is a diagram showing a cross-sectional structure of a main part of a semiconductor memory device provided with a wheel-out buffer circuit shown in Fig. 34; FIG. 36 is a diagram for explaining a problem of the semiconductor device shown in FIG. 35. FIG. (Symbol description) 100 to semiconductor devices, 102 to internal circuits, 104 to output circuits, 110 to semiconductor devices, 110c to snubber circuits, 110e to output snubber circuits, 140, 140a to 140f, power supply amplifiers, 142a, 142b, 142d soil 142f ~ power line 'i42c ~ bias power line, 144, 144a soil 144f ~ ground gain increaser, 146a, 146b, 146d to 146f ~ connect 61 1 This paper size applies to Chinese National Standard 1CNS) 4Specifications ⑺〇 &gt; &lt; 297 Gong ^ ------ (Please read the precautions on the back and fill in this page first). Binding. —----- €) A7 ___________B7 V. Description of the invention (59 ) Ground wire, 162, 162a, 162b ~ Semiconductor device circuit, Cl, C3 ~ Capacitor, R, Rl, R2 ~ Resistor, 200, 202a, 202b ~ VBB generating circuit, 201, 201a, 201b ~ substrate bias voltage transmission Line, 210, 212 ~ low-pass filter, 300 ~ semiconductor substrate, 302 ~ P 丼, 303 ~ N 丼, 120 ~ semiconductor substrate, 118 ~ bias voltage application area for noise absorption (N 丼 or N + impurities Field), H7 ~ p + impurity field, 119 ~ N + impurity field. ------------ π ------. ^ (Please read the notes on the back before filling this page)

Printed by the Employees' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 62

Claims (1)

The scope of the application is called the patent scope. The member of the Central Bureau of the Ministry of Economic Affairs x acts on the power supply voltage. The signal of the internal circuit is applied to a 2 · semiconductor device including: a first power supply line for transmitting a first power supply potential; a second power supply line for transmitting a second power supply potential; an internal circuit, Make the first! The first power supply line] The second power supply potential of the second power supply line of the power supply is operated as a side and another driver operating power voltage. The signal fed to the person is processed to output a capacitor with a discharge. The ^ power supply is used for multiple purposes: Slow I An I-type semiconductor device includes: a first source supply line for transmitting a first power supply potential; a supply line for transmitting a second power supply potential; an internal circuit that causes Zimin 'the second power supply supply line; The supply line &lt; the first power supply potential operates with the operating power supply and voltage, and the capacitors on the C-side and the other-side are connected to each other for processing and output; between; 2 The power supply line is set to pass == the line, and the power supply line is set separately to obtain the first power supply potential; the supply line is set separately from the second power supply line to convey the second power supply; Non-combination in accordance with the method of communication 'using the order of the 3 electric county to the line source potential 4 the fourth power supply line pan action-Λ 2nd potential as one side and the other 63 paper size Between the scope of patent application and the second power supply line; the third consumer power supply line printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is used to communicate the first power supply potential; the first power supply line is set separately, and the The 4 power supply line is used to convey the second power supply line. The 2 power supply line is separately provided, and the buffer circuit is now the first power supply potential of the second line on the fourth electrotherapy supply line, the operating power supply, and the voltage. Action, two, the potential is rotated out as -side and other-side processing; 'the internal circuit's turn-out signal is buffered in the third power supply line and has a substantially effective capacitance to the line &lt; There are only the third electric green supply line and the fourth electric generating capacitor, which are to be placed. 'Home supply line to be capacitively coupled 3.—A semiconductor device equipped with: a feed line' to communicate the potential of the first wire; ^ Electrogen supply line to communicate the second electric potential; 郅 Circuit, order The first! The power supply, Mo, and ωω are calculated by the first power supply potential and the second. The second line operates on the supply line &lt; 2_ action electric voltage, and acts as the feed-in side and the other. L 谫 入 谫The 加以 number is processed and output; there is an effective capacitance mosquito capacitor between _ and the second power supply and the supply line; the first power supply is supplied to the third power supply line, and the first snow, and take # U after the n first Electricity, the original power supply line is used for opening, and the first power supply potential is transmitted. The fourth power supply line is separated from the second power supply and power supply line. Install, J install {Please read the precautions on the back before filling in this Page} Binding and binding paper size _ 6. The scope of the patent application is used to communicate the second power supply potential. The buffering circuit is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, so that the third power supply and the fourth power supply line will be &lt; the first power supply potential and the operation. The power supply and the voltage are operated, and the inner port: the two sides and the other, are processed and rotated out; and the circuit (rounded out signal) buffers between 0 supply lines with effective capacitance 値 and the fourth power supply line. &quot; ~ The third power supply 4.-semiconductor device is provided with: a source supply line for transmitting the potential of the first power supply; an electric green supply line for transmitting the potential of the second power supply. Internal circuit 'order The first! Power supply: the second electric potential of the second electric line acts as the first voltage, and processes the fed-in signal to rotate out; the first insulated gate-type electric field effect is to go to the "Juhuan fruit electric egg" Including: The first and second guides are both combined in the "i" supply 2. I and H of the electrotherapy supply line! 3 power supply line 'is set separately from the first power supply line, use 乂The first power supply potential is communicated; the 7th cotton power supply line 4 is provided separately from the second power supply line to communicate the second power supply potential; the Γ buffer circuit enables the first power supply potential on the third power supply line The second potential of the fourth power supply line and the second power source on Tibet are operated as the operating voltage t on one side and the other side, and the output signal family from the internal circuit is buffered; and 65 paper money sauce) --1- ------- ^ —- * 装 __ (Please read the precautions on the back before filling out this page) Order Α8 Β8 C8 D8 Scope of patent application for printing by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Type electric field effect transistor, including: first and second guidance notice points, Do not combine it with the third power supply line; and a gate electrode that is electrically separated from the fourth power supply line. The semiconductor device claimed in the patent scope No. 1, 2, 3 or 4 is further equipped with: And a third power supply line, a, for receiving the first! Power supply potential from the external feed; and 0, the third power loss device, and the second and fourth power supply lines in common. It is used to connect the second potential of the power supply from the outside. There are 4 semiconductor devices with patent No. 1, 2, 3, or 4 in the patent. From: 1 damager, combined with the i-th power supply line, The second from the outside! Power supply potential, change = 2 gains 'and the second power supply line combined with the second power supply potential from the outside; the third third gain' and the first! Device points: The combination of source supply lines is used to receive the first from the outside, electrotherapy = 3, the sundial is, the second increase in the loss of the knife-called 莰 set, and the blood power supply line is combined to receive from The second external power = 7. If the patent application scope is the sixth financial semiconductor μ, _. The money red circuit is formed in the field of semiconductor substrates; Biasing power supply line, which based on common _ engaged and the engagement of the second supply source _ loss is increased, and from the increase of the loss accepts! Employees of the Central Bureau of Standards of the Ministry of Economic Affairs printed the potentials' to the semiconductor substrates. 8 · If you apply for the fifth material and half of the device, the buffer circuit is formed in the field of semiconductor substrates, and the capacitor has a side electrode that is divided into the first part and the second part. One part is connected to the first power supply line, and the second part is coupled to the internal circuit; and a bias power line is provided, which is lightly connected to the second power supply line of the first power and supply line. Between the semiconductor substrate field, the third source potential on the second part is transmitted to the semiconductor substrate field. 9. If the semiconductor device according to claim 2, 3, or 4 of the patent application scope, the buffer circuit is formed in the field of semiconductor substrates; and further includes: a low-pass filter; and a bias power line with the third power source The supply lines are provided separately to communicate the i-th power source potential to the semiconductor substrate field via the low-pass data wave device. &quot; 10. The semiconductor device according to item 9 of the patent application scope, wherein the low-pass filter includes a gate coupled to the bias power line and the fourth power supply line 11. The semiconductor device according to item 9 of the patent application scope Wherein, the preferred power line is commonly coupled to a loss increaser coupled to the third power supply line; and the low-pass filter includes a power supply line connected between the reference bias power line and the ^ 2 power supply line. Capacitor. Π. If the semiconductor device of the scope of application for the patent No. 9 item, wherein the bias power line is electrically connected to the office connected to the first power supply line ^ 67 This paper size applies to Chinese national standards. (CNS) Α4 Specifications (210X29.7mm) J 1--------: κ,--i -Λ-(Please read the precautions on the back before filling this page)-Order 6. The scope of the patent application; and the low-pass chirp includes a capacitor lightly connected between the bias power line and the first power supply line. 13. The semiconductor device according to item 9 of the scope of patent application, wherein the private power supply is separately provided from the third power supply line and the fourth power supply line, and the gain increaser is separately provided, and the bias of the second power supply potential is accepted. Picker = Low-pass filter includes the bias power line and the capacitor. The only benefit is 14. If the semiconductor device of the patent application No. 13 of the patent application, the bias power line is separately provided from the third power supply line, and the electrical property = the increase or loss coupled to the third power supply line Device. Connection 15. For example, the conductor device on page 13J of the scope of the patent application, and the bias power line are coupled to the i-th power supply line and the second electric green line: separate loss increasers are provided and used for Connect, —, 'on the loss increaser. In turn, the first electric potential 16. If the scope of patent application is No. r, 2, 3 or Dao, wherein the buffer circuit is formed in the field of semiconductor substrates: Guide: the third electric relay is mounted on the material conductor wire Material: Yuan Lei Fu. Shout No. 1 17. If you apply for a full-time perimeter item 1, 2, 3, or 4, which includes a low-feeder installed on the third power supply line and the first body supply line, the low itm 'includes: a first resistance element interposed between the source for the Γ supply line, a capacitor coupled between the third power supply: the second power supply line, and a second resistance element interposed between the = lines. Electricity, supply 68 Patent application scope 18. A8 B8 C8 D8 semiconductor devices with buffer circuits printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, formed in the field of semiconductor substrates, / buffered input signals and output; low-pass A filter; and a substrate bias generating mechanism for generating a bias voltage to be applied to the semiconductor substrate field and applied to the semiconductor substrate field through the low-pass filter. 19. If the semiconductor device of the patent application No. 18 is applied, it further includes: an internal circuit formed in the second semiconductor substrate field separate from the semiconductor substrate field. The signal used to process the signal will be displayed. The signal of the processing result is transmitted to the buffer circuit; the second semiconductor substrate field receives power noise from the substrate bias generating mechanism before the low-pass filter performs filtering processing. 20. The semiconductor device according to item 18 of the scope of patent application, further comprising: an internal circuit formed in a second semiconductor substrate field separated from the semiconductor substrate field, and used to process the input signal, which indicates the processing. The resulting signal is fed to the buffer circuit; and a substrate bias generating mechanism is provided separately from the substrate bias generating mechanism to generate a bias voltage at the same voltage level as the bias voltage, and is applied to the second semiconductor. Substrate field. 21. The semiconductor device according to item 7 of the scope of patent application, wherein the ~ circuit is formed in the semiconductor substrate collar and is formed in a region &lt; that is supplied with a bias voltage different from the first power supply potential . Please read the note first. Matters to mention 69 69 This paper size adopts the Chinese national standard. (CNS) A4 size (210X297 mm) Six A8 B8 C8 D8 Patent scope 22. If the scope of patent application is the seventh The semiconductor semiconductor circuit is formed in the semiconductor device. It is also formed by the edge of the star, in the + conductive substrate collar ', and the semiconductor substrate collar is biased to a voltage different from the first power supply potential. . 23. If the scope of the patent application is No. 1, 2, 3, .4, 18, 19, or 20 = conductor device, the semiconductor device includes memory cells arranged in rows and columns; the internal circuit includes memory cells from the majority = Select a storage unit, and use the selected storage order as a memory data circuit; the buffer circuit includes an output buffer circuit that rotates the lean stems read out by the internal circuit to the outside of the device. 24. The semiconductor device according to item 9 of the patent application park, wherein the buffer circuit is formed in the field of the semiconductor substrate and formed in a well field receiving a bias voltage different from the first power supply potential. 25. The semiconductor device according to item 9 of the scope of patent application, wherein the slow = road: formed in the semiconductor substrate field 'and the semiconductor substrate collar system is biased to a bias voltage different from the first power source potential 26. For the semiconductor device according to item 16 of the patent application scope, wherein the buffer circuit surface is formed in a field of a material conductor, and a field of a bias voltage having a potential different from that of the first power source. 27. The semiconductor device according to item 16 of the application, wherein the buffer circuit is formed in the field of the semiconductor substrate, and the semiconductor system is biased to a bias voltage different from the first power supply potential. Telegraph 114 70 {Read the precautions on the back before filling in this page j. Install and print the Chinese National Standard. (CNS) A4 size (210X297 mm) by the Consumer Consumption Cooperative of the Bureau of Standards and Loss of the Ministry of Economic Affairs.