KR960008309B1 - Semiconductor memory device having a triple well - Google Patents

Semiconductor memory device having a triple well Download PDF

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KR960008309B1
KR960008309B1 KR1019920000095A KR920000095A KR960008309B1 KR 960008309 B1 KR960008309 B1 KR 960008309B1 KR 1019920000095 A KR1019920000095 A KR 1019920000095A KR 920000095 A KR920000095 A KR 920000095A KR 960008309 B1 KR960008309 B1 KR 960008309B1
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well
bias
memory device
semiconductor memory
conductive
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KR930017168A (en
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이재형
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김광호
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

a p-substrate (21) which is biased first; a n-well (22) which is fabricated in the p-substrate (21) and is biased second; a first p-well (23) which is fabricated in the n-well (22) and is biased first or third; a second p-well (24) which is fabricated in the n-well (22) and is biased first; a MOS transistor which the first p-well (23) and the second p-well (24) are separated each other and are formed in the n-well (22).

Description

트리플웰을 가지는 반도체 메모리 장치Semiconductor memory device with triple well

제1도는 종래의 트리플웰구조도.1 is a conventional triple well structure diagram.

제2도는 본 발명에 따른 트리플웰구조도.2 is a triple well structure diagram according to the present invention.

제3도는 본 발명을 트윈웰구조에 적용한 예.3 is an example of applying the present invention to a twin well structure.

본 발명은 반도체 메모리장치에 관한 것으로, 특히 트리플웰 구조를 가지는 반도체 메모리 장치에 관한 것이다.The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a triple well structure.

일반적으로 고집적 메모리장치를 구성할 때 몸체효과(body effect)에 의한 특성악화를 방지하기 위하여 주변회로 영역에서 음전압 바이어스 대신에 접지전압 Vss를 사용한다. 상기 몸체효과는 고집적 반도체 메모리장치에 있어서 단소채널(short channel)효과를 억제하기 위하여 웰 또는 기판의 농도를 증가시킴에 따라 몸체효과가 일어날 확률이 높아진다. 이와 같은 몸체효과를 방지하기 위하여 종래에 트리플웰 구조가 도시바(주)에 의하여 제안된 바 있다(IEEE Journal of Solid-State Circuits, Aug.1989, pp.1170-1174를 보라). 그러나, 상기 제안된 트리플웰 구조는 전원간의 잡음을 감소시키고, 칩의 크기를 줄이는데 한계가 있다.In general, when constructing a highly integrated memory device, a ground voltage Vss is used in place of a negative voltage bias in a peripheral circuit area to prevent deterioration of characteristics due to a body effect. The body effect increases the probability of a body effect by increasing the concentration of a well or a substrate in order to suppress a short channel effect in a highly integrated semiconductor memory device. In order to prevent such a body effect, a conventional triple well structure has been proposed by Toshiba Corporation (see IEEE Journal of Solid-State Circuits, Aug. 1989, pp. 1170-1174). However, the proposed triple well structure has a limitation in reducing noise between power supplies and reducing chip size.

제1도에는 종래의 트리플웰 구조를 가지는 반도체 메모리 장치의 단면구조가 도시되어 있다. 제1도에서는 메모리셀 어레이와 주변회로의 각 영역에서 구비된 웰단면 구조와 웰들에 인가되는 웰바이어스의 상태를 보여준다. 제1도를 참조하면, 제1피형웰(13)의 웰바이어스인 음전압(또는 백게이트전압) VBB1과 제1엔형웰(11)의 웰바이어스인 전원전압 Vcc3 사이에 존재하는 기생캐패시터 C1과, 상기 전원전압 Vcc3와 기판(10)의 바이어스인 접지전압 Vcc4 사이에 존재하는 기생캐패시터 C2에 의하여, 전원잡음이 감소된다. 전원전압 Vcc3의 입장에서, 기생캐패시터 C1 및 C2에 의하여 Vcc3에 의한 전원잡음이 발생할 때 상기 제1피형웰(13)에 인가되는 음전압과 기판바이어스인 접지전압이 동일한 전위를 유지한다면, 전원전압 Vcc3에 의한 잡음을 감소시키게 된다. 한편, 접지전압 Vcc4의 측면에서도 상기 기생캐패시티 C2에 의하여 전원전압 Vcc3가 같은 레벨을 유지한다면 접지전압의 잡음을 줄일 수 있다. 실제적으로, 전원전압과 접지전압의 잡음원으로서 가장 큰 원인은, 메모리셀의 데이타를 센싱할 때, 접지전압의 잡음을 유발하는 엔모오스트랜지스터에 의한 센싱동작(비트라인의 전위를 접지전압으로 풀다운하는 동작)과 전원전압의 잡음을 유발하는 피모오스트랜지스터에 의한 센싱동작(비트라인의 전위를 전원전압으로 풀엎시키는 동작)에서 발생된다.1 shows a cross-sectional structure of a semiconductor memory device having a conventional triple well structure. FIG. 1 shows a well sectional structure provided in each region of a memory cell array and a peripheral circuit and a state of a well bias applied to wells. Referring to FIG. 1, a parasitic capacitor C1 existing between a negative voltage (or back gate voltage) V BB1 , which is a well bias of the first well 13, and a power supply voltage Vcc3, which is a well bias of the first N type well 11. Power supply noise is reduced by the parasitic capacitor C2 existing between the power supply voltage Vcc3 and the ground voltage Vcc4 which is the bias of the substrate 10. From the standpoint of the power supply voltage Vcc3, when the power supply noise caused by the parasitic capacitors C1 and C2 causes Vcc3, the negative voltage applied to the first well 13 and the ground voltage which is the substrate bias maintain the same potential. The noise caused by Vcc3 is reduced. On the other hand, in the aspect of the ground voltage Vcc4, the noise of the ground voltage can be reduced if the power supply voltage Vcc3 is maintained at the same level by the parasitic capacitance C2. In practice, the main source of noise of the power supply voltage and the ground voltage is the sensing operation by the Enmo transistor which causes noise of the ground voltage when sensing the data of the memory cell (pull down the potential of the bit line to the ground voltage). Operation) and a sensing operation by the PIO transistor causing noise of the power supply voltage (the operation of pulling down the potential of the bit line to the power supply voltage).

상기 풀다운 동작에 의한 접지전압의 잡음유발과 풀엎동작에 의한 전원전압의 잡음유발은 시간적으로 어긋나 있기는 하지만, 상기 기생캐패시터 C1이 C2에 비하여 큰 용량을 가지기 때문에, 전원전압의 잡음감소가 접지전압의 잡음감소보다 크게 되는 단점이 있다.Although noise induction of the ground voltage by the pull-down operation and noise induction of the power supply voltage by the pull-down operation are shifted in time, since the parasitic capacitor C1 has a larger capacity than that of C2, the noise reduction of the power voltage is caused by the ground voltage. The disadvantage is that it is larger than the noise reduction.

한편, 메모리셀 어레이에 존재하는 제1엔형웰(11)과 주변회로에 존재하는 제2엔형웰(12)사이에는 어느정도의 거리가 존재하여야 하므로, 고집적 반도체 메모리장치를 구성할때 칩의 크기가 증가되는 문제가 있다.Meanwhile, since a certain distance must exist between the first N well 11 present in the memory cell array and the second N well 12 present in the peripheral circuit, the chip size of the highly integrated semiconductor memory device is increased. There is an increasing problem.

따라서 본 발명의 목적은 트리플웰 구조를 가지는 고집적 반도체 메모리장치에 있어서 전원잡음을 억제할 수 있는 장치를 제공함에 있다.Accordingly, an object of the present invention is to provide a device capable of suppressing power noise in a highly integrated semiconductor memory device having a triple well structure.

본 발명의 다른 목적은 칩의 사이즈를 증가시키지 않고도 고집적의 트리플웰 구조를 실현할 수 있는 반도체 메모리장치를 제공함에 있다.Another object of the present invention is to provide a semiconductor memory device capable of realizing a highly integrated triple well structure without increasing the size of the chip.

상기 본 발명의 목적을 달성하기 위하여, 본 발명은 씨모오스트랜지스터로 구성된 메모리셀 어레이와 주변회로를 가지는 반도체 메모리장치에 있어서, 제1바이어스가 인가되는 제1도전형의 기판과, 상기 기판내에 형성되고 제2바이어스가 인가되는 제2도전형의 웰과, 상기 제2도전형의 웰내에 형성되고 제3바이어스가 인가되며 서로 이격된 제1 및 제2의 제1도전형의 웰을 구비하고, 상기 제1 및 제2의 제1도전형의 웰이 각각 제2도전형의 모오스트랜지스터를 가짐을 특징으로 한다. 또한 본 발명은, 씨모오스트랜지스터로 구성된 메모리셀 어레이와 주변회로를 가지는 반도체 메모리장치에 있어서, 제1바이어스가 인가되는 제1도전형의 기판과, 상기 기판내에 형성되고 제2바이어스가 인가되며 제1도전형의 모오스트랜지스터가 형성된 제1의 제2도전형의 웰과, 상기 기판내에서 상기 제1의 제2도전형웰과는 이격되어 제3바이어스가 인가되며 제1도전형의 모오스트랜지스터가 형성된 제2의 제2도전형의 웰을 구비함을 특징으로 한다.In order to achieve the object of the present invention, the present invention is a semiconductor memory device having a memory cell array consisting of a CMOS transistor and a peripheral circuit, the first conductive type substrate to which a first bias is applied, and formed in the substrate And a well of a second conductive type to which a second bias is applied, and wells of the first and second first conductive types formed in the well of the second conductive type, to which a third bias is applied, and spaced apart from each other, The wells of the first and second first conductivity types each have a MOS transistor of the second conductivity type. In addition, the present invention relates to a semiconductor memory device having a memory cell array composed of CMOS transistors and a peripheral circuit, comprising: a first conductive substrate to which a first bias is applied, a second bias formed in the substrate, and a second bias applied thereto; The first second conductive well in which the first conductive MOS transistor is formed is separated from the first second conductive well in the substrate, and a third bias is applied, and the first conductive MOS transistor is formed. And a second second conductive well.

이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다. 제2도를 참조하면, 본 발명의 트리플웰 구조는, 메모리셀 어레이에서 사용되는 제1피형웰(23)과 코아 및 주변회로에서 사용되는 제2피형웰(24)가 하나의 엔형웰(22)내에 형성되어 있다. 상기 제1피형웰(23)에는 음전압 VBB1가 웰바이어스(또는 트랜지스터의 백게이트전압)로 인가되고, 상기 제2피형웰(24)에는 접지전압 Vss2가 웰바이어스로서 인가되며, 상기 엔형웰(22)의 웰바이어스는 전원전압 Vcc3이 된다. 기판(21)에는 접지전압 Vss4가 인가된다. 상기 엔형웰(22)과 기판(21)사이에서 형성되는 기생캐패시터 C4가 제1도의 C2에 비하여 더 큰 용량을 가지므로(이는 상기 엔형웰(22)의 면적이 제1도의 제2엔형웰(12)에 비해 크기 때문임), 접지전압 Vss의 잡음을 제1도에 비하여 더 감소시킬 수 있음을 알 수 있다. 즉, 제1도의 종래의 구조에서 설명한 바와 같이, 기생캐패시터 C1과 C2의 용량차이에 따른 전원전압 잡음 감소량과 접지전압 잡음 감소량의 상대적인 차이에 의한 접지전압 잡음 감소를 면적이 큰 엔형웰(22)에 의하여 극복한 것이다. 또한 하나의 엔형웰(22)을 사용함으로써 분리된 엔형웰사이의 이격거리가 필요 없으므로 칩사이즈가 증가되지 않음을 알 수 있다. 상기 제2도에서 각 웰 예를 들어 메모리셀 어레이에 존재하는 제1피형웰(23)에 형성된 엔모오스트랜지스터는 메모리셀의 패스트랜지스터에 해당되며, 코아 및 주변회로에 존재하는 제2피형웰(24)내에 형성된 엔모오스트랜지스터는 엔형센스앰프의 트랜지스터, 로우 및 컬럼디코더의 트랜지스터, 드라이버 또는 데이타버퍼등에 사용되는 트랜지스터에 해당하는 것임을 알아두기 바란다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 2, in the triple well structure of the present invention, a first well 23 used in an array of memory cells and a second well 24 used in cores and peripheral circuits include one en-well 22. It is formed inside). A negative voltage V BB1 is applied to the first well as 23 as a well bias (or a back gate voltage of a transistor), and a ground voltage Vss2 is applied to the second well as 24 as a well bias. The well bias at 22 is the power supply voltage Vcc3. The ground voltage Vss4 is applied to the substrate 21. Since the parasitic capacitor C4 formed between the n-well 22 and the substrate 21 has a larger capacity than that of C2 in FIG. 1 (the area of the n-well 22 is larger than that of the second N-well in FIG. 12), it can be seen that the noise of the ground voltage Vss can be further reduced compared to FIG. That is, as described in the conventional structure of FIG. 1, the n-well 22 having a large area of the ground voltage noise reduction due to the relative difference between the reduction of the supply voltage noise and the ground voltage noise reduction according to the capacitance difference between the parasitic capacitors C1 and C2. It is overcome by. In addition, it can be seen that the chip size is not increased by using a single n-well 22 because the separation distance between the separate n-wells is not necessary. In FIG. 2, the enmotransistors formed in each well, for example, the first peg well 23 present in the memory cell array, correspond to the fast transistors of the memory cell, and the second p wells present in the core and peripheral circuits. Note that the MOS transistor formed in 24) corresponds to a transistor used in a transistor of an n-type sense amplifier, a transistor of a row and column decoder, a driver, or a data buffer.

제3도는 본 발명을 엔형의 기판에 적용한 실시예를 보여준다. 제3도의 실시예는 제2도에서 엔형웰(22)을 엔형기판(31)으로 사용한 것과 동일하다고 보면 된다. 엔형기판(31)의 바이어스인 전원전압 Vcc와 제1피형웰(32)의 웰바이어스인 음전압 VBB사이에 형성되는 기생캐패시터 C5와, 전원전입 Vcc와 제2피형웰(33)의 웰바이어스안 접지전압 Vss사이에 형성되는 기생캐패시터 C6에 의하여 전원전압 잡음 및 접지전압 잡음이 각각 감소된다.3 shows an embodiment in which the present invention is applied to an en-type substrate. The embodiment of FIG. 3 can be regarded as the same as that of using the n-well 22 as the n-type substrate 31 in FIG. Well bias of enhyeong substrate 31, the bias of the power source voltage Vcc and the first to-be-hyeongwel 32-well bias of a negative voltage V parasitic capacitor C5, and a power transfer Vcc and the second to-be-hyeongwel 33 formed between the BB's of The parasitic capacitor C6 formed between the safety ground voltage Vss reduces the power supply voltage noise and the ground voltage noise, respectively.

상술한 바와 같이, 본 발명은 트리플웰 구조의 반도체 메모리장치에 있어서 전원에 의한 잡음을 감소시키는 효과가 있다.As described above, the present invention has an effect of reducing noise caused by a power source in a semiconductor memory device having a triple well structure.

또한 본 발명은 트리플웰 구조의 고집적 반도체 메모리장치의 칩사이즈를 줄이는 이점이 있다.In addition, the present invention has the advantage of reducing the chip size of the triple-well high-density semiconductor memory device.

Claims (3)

씨모오스트랜지스터로 구성된 메모리셀 어레이와 주변회로를 가지는 반도체 메모리장치에 있어서, 제1바이어스가 인가되는 제1도전형의 기판과, 상기 기판내에 형성되고 제2바이어스가 인가되는 제2도전형의 웰과, 상기 제2도전형의 웰내에 형성되고 제1 내지 제3바이어스가 각각 인가되는 제1의 제1도전형웰과, 상기 제2도전형의 웰내에 형성되고 상기 제1바이어스가 인가되는 제2의 제1도전형웰과, 상기 제1 및 제2의 제1도전형의 웰이 서로 이격되어 있으며, 상기 제1 및 제2의 제1도전형의 웰이 각각 제2도전형의 모오스트랜지스터를 가짐을 특징으로 하는 반도체 메모리장치.A semiconductor memory device having a memory cell array consisting of a CMOS transistor and a peripheral circuit, comprising: a first conductive type substrate to which a first bias is applied, and a second conductive type well formed on the substrate and to which a second bias is applied; And a first first well formed in the well of the second conductivity type and to which first to third vias are applied, and a second formed in the well of the second conductivity type and to which the first bias is applied. The first conductive wells of the first and second wells of the first conductive type and the second conductive wells are spaced apart from each other, the wells of the first and second first conductive type have a second transistor type MOS transistor, respectively A semiconductor memory device, characterized in that. 제1항에 있어서, 상기 제1바이어스가 접지전압이고, 상기 제2바이어스가 전원전압이며, 상기 제3바이어스가 소정레벨의 음전압임을 특징으로 하는 반도체 메모리장치.The semiconductor memory device of claim 1, wherein the first bias is a ground voltage, the second bias is a power supply voltage, and the third bias is a negative voltage having a predetermined level. 제2항에 있어서, 상기 제1의 제1도전형웰내에 형성된 모오스트랜지스터가 상기 메모리셀의 패스트랜지스터이고, 상기 제2의 제1도전형웰내에 형성된 모오스트랜지스터가 상기 주변회로에서 사용되는 트랜지스터임을 특징으로 하는 반도체 메모리장치.3. The transistor of claim 2, wherein the MOS transistor formed in the first conductive well is a fast transistor of the memory cell, and the MOS transistor formed in the second conductive well is a transistor used in the peripheral circuit. A semiconductor memory device.
KR1019920000095A 1992-01-07 1992-01-07 Semiconductor memory device having a triple well KR960008309B1 (en)

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US8487383B2 (en) 2009-12-15 2013-07-16 Samsung Electronics Co., Ltd. Flash memory device having triple well structure

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KR100275725B1 (en) * 1997-12-27 2000-12-15 윤종용 Semiconductor memory device with triple well structure and manufacturing method therefor
KR101585616B1 (en) 2009-12-16 2016-01-15 삼성전자주식회사 Semiconductor device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8487383B2 (en) 2009-12-15 2013-07-16 Samsung Electronics Co., Ltd. Flash memory device having triple well structure

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