KR970060478A - Semiconductor device - Google Patents

Abstract

The present invention relates to a configuration for reducing the influence of power supply noise during the operation of the buffer circuit. In order to prevent the power supply noise generated during the operation of the buffer circuit from affecting other internal circuits, the internal circuit 102 and the output are output. The power supply lines 142a and 142b and the ground lines 146a and 146b were separately provided for the circuit 104, and a stabilizing capacitor CI was provided only between the power supply line and the ground line of the internal circuit. With this arrangement, there is no capacitive coupling between the power line and the ground line of the output circuit, so that power noise occurs during the operation of the output circuit, so that even if the power supply voltage decreases, the ground voltage does not decrease and the constant voltage level can be maintained. do.

Description

Semiconductor device

Since this is an open matter, no full text was included.

1 is a cross-sectional view schematically showing the overall configuration of a semiconductor device to which the present invention is applied.

Claims (25)

First power supply lines 142a (142d and 142e) for transmitting a first power potential, second power supply lines (146a: 146fb, 146fa, and 146e) for transmitting a second power potential, and the first on the first power supply line Internal circuits 102: 110b, 110c: 402, 404, 408, 406, 410 that operate the power potential and the second power potential on the second power supply line as one and the other operating power potential, respectively, and process and output an applied signal. capacitor (C1: C5, C6) coupled between the first power supply line and the second power supply line, and provided separately from the first power supply line to transfer the first power potential. Third power supply lines 142b and 142f are provided separately from the second power supply line and are in a non-coupled state substantially alternating with the third power supply line. A fourth power supply line (146b; 146f) for transmitting a second power potential; A buffer circuit for operating the first power potential on the third power supply line and the second power potential on the fourth power supply line as one and the other operating power potential, respectively, and buffering and outputting the output signal of the internal circuit; A semiconductor device. In the first power supply line, only the parasitic capacitance Cs having a capacitance smaller than the significant capacitance is between the third power supply line 142b and 142f and the fourth power supply line 146b and 146f. And the fourth power supply line as means for capacitively coupling each other. 2. The semiconductor device of claim 1, wherein the number of capacitors coupled between the third power supply line (142b; 142f) and the fourth power supply line (146b; 146f) and having the significant capacitance value is zero. 2. The capacitor of claim 1, wherein the capacitors C1, C4, and C5 have first and second conductive nodes coupled to the second power supply line 146b, and gates coupled to the first power supply line 142a. A first insulated gate field effect transistor (170a, 178a, 177a), and the semiconductor device includes first and second conductive nodes coupled to the fourth power supply line (146b) and the fourth power supply line (142b). And a second insulated gate field effect transistor (171b, 177b, 178b) having a gate electrically separated from each other. According to claim 1, wherein the first and the third power supply line is commonly coupled and the first pad 140 receives a first power potential applied from the outside, and the second and fourth power supply line is commonly coupled And a second pad (144) receiving a second power potential applied from the outside. The method of claim 1, wherein the first power supply line (142; 142d; 142e) is coupled to the first pad (140a; 140d, 140c) receiving a first power potential applied from the outside, the second power supply line is coupled And second pads (144a; 144d and 144e) receiving second power potentials applied from the outside, provided separately from the first pads, and coupled to the third power supply lines (142b and 142f) and applied from the outside. Third pads 140b and 140f receiving a first power potential and fourth pads 144b and 144f provided separately from the second pad and coupled to the fourth power supply line and receiving a second power potential applied from the outside. A semiconductor device further comprising). The semiconductor device of claim 6, wherein the buffer circuit 104 is formed on the semiconductor substrate regions 118 and 113d, and the semiconductor device is commonly coupled to a pad to which the first power supply line 142a is coupled. And a bias power line (142d) for receiving the first power potential from a pad and transferring it to the semiconductor substrate region. 5. The buffer circuit (104) of claim 5, wherein the buffer circuit (104) is formed on the semiconductor substrate regions (118 and 113d), and the capacitor (CI) is coupled to the pad and the first portion (142aa) and the internal circuit (102). Has one electrode coupled to a node NA divided into a second portion 142ab coupled to the semiconductor device, the semiconductor device is coupled between the second portion of the first power supply line and the semiconductor substrate region, And a bias power line (142c) for transferring said first power potential on said second portion to said semiconductor substrate region. The semiconductor device of claim 1, wherein the buffer circuit 104 is formed on the semiconductor substrate regions 118 and 113d, and the semiconductor device includes a low pass filter (R, C3; R1, C4) and the third power supply line 142b. And a bias power supply line (142c) for providing the first power supply potential to the semiconductor substrate region through the low pass filter. 10. The semiconductor device of claim 9, wherein the low pass filter (R, C3) includes a capacitor (C3; C4) coupled between the bias power line (142c) and the fourth power supply line (146b). The method of claim 9, wherein the bias power line 142c is commonly coupled to the pads 140 and 140b to which the third power supply line 142b is coupled, and the low pass filters R and C3 are biased. And a capacitor (C3) coupled between a power line and the second power supply line (146i). The bias power supply line 142c is electrically connected to a pad 140a to which the first power supply line 142b is connected, and the low pass filters C3 and R are connected to the bias power supply line. A semiconductor device comprising a capacitor (C3) coupled between the second power supply line (146a). 10. The method of claim 9, wherein the third power supply line 146a and the fourth power supply line 140b are respectively provided separately from the pads 140, 144; 140a, 140b, 144a, and 144b to be coupled and receive the second power potential. And a bias pad (144c), wherein the low pass filter (R, C3) includes a capacitor (C3) coupled between the bias power line (142c) and the bias pad. The semiconductor device according to claim 13, wherein the bias power line (142c) is provided separately from the third power supply line (146b) and electrically connected to a pad (140) to which the third power supply line is coupled. The pad of claim 13, wherein the bias power line 142c is provided separately from the pads 140a and 140b to which the first and third power supply lines 146a and 142b are coupled and receives the first power potential. A semiconductor device coupled to 140c). The semiconductor device of claim 1, wherein the buffer circuit 104 is formed on the semiconductor substrate regions 118 and 113d, and the third power supply line 142b supplies the first power potential to the semiconductor substrate region. Device. The method of claim 16, further comprising a low pass filter (C4, R1, R2) provided in the third power supply line (146b) and the fourth power supply line (146b), the low pass filter is the third power source And a first resistor element R1 inserted into a supply line, a capacitor C4 coupled between the third power supply line and the fourth power supply line, and a second resistor element R2 inserted into the fourth power supply line. Semiconductor device. A buffer circuit 104, a low pass filter 210; 212, and a bias potential to be applied to the semiconductor substrate region are generated by buffering and outputting a signal formed in the semiconductor substrate region and passing through the low pass filter. A semiconductor device comprising substrate bias generating means (200; 202a, 202b) applied to a substrate region. 19. An internal circuit (102) according to claim 18, further comprising: an internal circuit (102) for processing a signal formed in and applied to a second semiconductor substrate region (130) formed separately from said semiconductor substrate region to transfer a signal representing the processing result to said buffer circuit; 110b and 110d, wherein the second semiconductor substrate region receives a bias potential before the filter process by the low pass filter from the substrate bias generating means (200; 202b). 19. The signal according to claim 18, wherein a signal formed in the second semiconductor substrate region 130 formed separately from the semiconductor substrate regions 118, 113d, and 302 is applied to process the applied signal to the buffer circuit. The substrate bias generating means 202b, which is provided separately from the internal circuit 102 and the substrate bias generating means 202a to apply, generates a bias potential having the same potential level as the bias potential and applies it to the second semiconductor substrate region. A semiconductor device further comprising. The semiconductor substrate region of claim 1, wherein the buffer circuit 104 is formed on a semiconductor substrate region 118 and is formed in a well region 117 to which a bias potential different from the first power source potential is supplied. The semiconductor device is supplied with the first power potential. The semiconductor device according to claim 1, wherein the buffer circuit 104 is formed in the semiconductor substrate region 113d and the semiconductor substrate region is biased with a bias potential different from the first power potential and is supplied with the first power potential. A semiconductor device comprising 118. The memory device of claim 1, further comprising a plurality of memory cells (102a; 406) arranged in a row shape, wherein the internal circuits (102; 404, 408, 410) select a memory cell from the plurality of memory cells and select the selected memory cell. A circuit (102b; 404) for reading the stored data of the buffer circuit; and the buffer circuit (104; 400) includes an output buffer circuit (104; 400) for outputting data read by the internal circuit to the outside of the apparatus. Semiconductor device. 22. The semiconductor device of claim 21, further comprising means (200; 202b) for generating the bias potential and supplying the bias potential to the well region (117) via a low pass filter (210; 212). 23. The semiconductor device of claim 22, further comprising means (200; 202b) for generating the bias potential and supplying the bias potential to the semiconductor substrate region (113d) via a low pass filter (210; 212). ※ Note: The disclosure is based on the initial application.