KR0170914B1 - Power transfer circuit - Google Patents

Abstract

In the power transmission circuit of the present invention, a capacitor is inserted between a power line for supplying a power voltage and a power line for supplying a ground voltage to remove high frequency components included in the power voltage, and the memory block corresponds to 1/2 of the plurality of memory blocks. The silver is supplied with a drive current through a resistor, thereby preventing the generation of large energy inside the device, thereby improving the stability of the device.

Description

Power transmission circuit

1 is a circuit diagram of a power transmission circuit of a conventional DRAM.

2 is a layout diagram of a conventional bit line sense amplifier driver and a power pad.

3 is an operation timing diagram for each part of the circuit shown in FIG.

4 is a circuit diagram of a power transmission circuit according to an embodiment of the present invention.

5 is a layout diagram between a bit line sense amplifier driver power pad according to an embodiment of the present invention.

FIG. 6 is an operation timing diagram for each part of the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

10,20,30,40: Power line B0, B1, B2, B3: Memory block

C1, C2, C3, C4: Capacitor Q1, Q2, Q3, Q4: Transistor

50,60: bit line detection amplifier

The present invention relates to a power transfer circuit of a DRAM in a semiconductor memory device, and more particularly, to remove a high frequency component generated from a power pad and drive current to a memory block corresponding to 1/2 of a plurality of memory blocks. The present invention relates to a power transmission circuit that delays the transmission and improves the stability of the device.

FIG. 1 is a circuit diagram of a conventional power transmission circuit of a DRAM, and includes a first power supply line 10 for transmitting a ground voltage on a first power supply pad Vss1 to the memory block B0 and the memory block B3, and a second power supply circuit. The second power supply line 20 for transmitting the power supply voltage on the power supply pad Vcc1 to the memory block B0 and the memory block B3, and the power supply voltage on the third power supply pad Vcc2 and the memory block B1 and the memory. And a third power supply line 30 for transmitting to the block B2, and a fourth power supply line 40 for transferring the power supply voltage on the fourth power supply pad Vss2 to the memory block B1 and the memory block B2. do.

The amount of current consumed when driving the bit line sense amplifier included in the memory block accounts for a large portion of the memory block.

Here, the connection relationship between the power pads and the bit line sense amplifiers included in the memory blocks B0 and B1 of FIG. 1 will be described with reference to FIG.

The memory block B0 includes a bit line sensing amplifier 50 for sensing and amplifying data from a memory cell, and a PMOS transistor for driving a power voltage from the second power pad Vcc1. Q1) and an MOS transistor Q2 for driving a ground voltage from the first power pad Vss1.

The bit line sense amplifier 10 receives the power voltage from the second power pad Vcc1 according to the selection signal SE on the input line 11 via the inverter 12. The NMOS transistor Q2 supplies the ground voltage from the first power pad Vss1 to the bit line sense amplifier 50 according to a selection signal SE from the outside.

The memory block B1 may include a bit line sensing amplifier 60 for sensing and amplifying data from a memory cell, and a PMOS transistor Q3 for driving a power voltage from the third power pad Vcc2. And an MOS transistor Q4 for driving the ground voltage from the fourth power pad Vss2.

The memory block B1 drives power from the third power pad Vcc2 and the fourth power pad Vss2 instead of the first power pad Vss1 and the second power pad Vcc1. Has the same configuration as the above B0 and detailed description thereof will be omitted.

However, there is a problem in that the power transmission circuit cannot remove noise generated in the memory blocks and guarantee the stability of the device. This will be described in detail with reference to FIG. 3, which is a timing diagram showing the waveform of the signal related to FIG.

The maximum value of the current supplied to the sensing amplifier 10 by the second power pad Vcc1 (hereinafter, referred to as Icc1) and the current supplied to the sensing amplifier 20 by the third power pad Vcc2. Since the time at which the maximum value of Icc2 occurs is the same, a large amount of current flows into the system in a short time. This is because all memory blocks perform the same sensing operation, and the faster the data processing speed and the higher the degree of integration, the more serious the problem.

Accordingly, it is an object of the present invention to provide a power transmission circuit capable of eliminating instantaneous small noise components and reducing large energy components flowing through a semiconductor device at a specific time to eliminate noise and ensure device stability. have.

In order to achieve the above object, the power transmission circuit of the present invention includes a first memory block to a fourth memory block including a plurality of memory cell arrays having a plurality of bit lines, and a first power supply voltage for inputting a first power supply voltage from an external source. A first power pad, a second power pad for inputting a second power voltage from the outside, a third power pad for inputting a second power voltage from the outside, and a first power pad from the first power pad A first power supply line for transmitting a voltage to the first and second memory blocks, a second power supply line for transmitting the second power supply voltage from the second power pad to the first and second memory blocks, and the second power supply line; A third power line for transmitting the first power voltage from the first power pad to the third and fourth memory blocks; and the third and fourth memory blocks receiving the second power voltage from the third power pad. 4th power line transmitting to A first noise signal having a large high frequency component connected in parallel between the first power line and the second power line and applied to the first and second power pads when the first and second memory blocks are driven; Two or more capacitors for delaying time, resistance means connected between the first power supply pad and the third power supply line, the first and second memory blocks connected in parallel between the third power supply line and the fourth power supply line; And at least two capacitors for delaying a large amplitude high frequency noise signal applied to the first and third power source pads by a second predetermined time different from the first predetermined time when they are driven.

Hereinafter, with reference to the drawings related to the present invention will be described in detail.

FIG. 4 is a circuit diagram illustrating a power transmission circuit according to an exemplary embodiment of the present invention, and includes a first power line 10 for supplying a ground voltage on the first power pad Vss1 to the memory block B0 and the memory block B3. ), A second power supply line 20 for supplying a power supply voltage on the second power supply pad Vcc1 to the memory block B0 and the memory block B3, and a node N1 on the first power supply line 10. And capacitors C1 and C3 connected between the node N2 on the second power line 20 to maintain the precharge state at Vcc in the standby state, and the power supply voltage on the third power pad to the memory block B1 and A third power supply line 30 for supplying to the memory block B2, a fourth power supply line 40 for supplying a power supply voltage on the fourth power supply pad Vss2 to the memory block B1 and the memory block B2; And a cache connected between the node N3 on the third power line 30 and the node N4 on the fourth power line 40 to maintain a precharge state at Vcc in a standby state. It comprises a sheeter (C2, C4) and a resistor (R) connected to a node (N3) on the second power supply pad (Vcc1) and a third power supply line (30).

FIG. 5 is a layout diagram illustrating a connection relationship between arbitrary bit line sense amplifiers included in the memory block B0 and the memory block B1 of the bit line sense amplifier driver of FIG. 4 and each power pad.

The memory block B0 includes a bit line sensing amplifier 50 for sensing and amplifying data from a memory cell, and a PMOS transistor for driving a power voltage from the second power pad Vcc1. Q1) and an MOS transistor Q2 for driving a ground voltage from the first power pad Vss1.

The PMOS transistor Q1 supplies the power supply voltage from the second power pad Vcc1 to the sensing amplifier 10 according to the selection signal SE on the input line 11 via the inverter 12. In addition, the NMOS transistor Q2 supplies a ground voltage from the first power pad Vss1 to the sensing amplifier 50 in response to a selection signal SE from the outside.

The memory block B1 includes a bit line sensing amplifier 60 for sensing and amplifying data from a memory cell, a PMOS transistor Q3 for driving a power voltage from a third power pad, and An enMOS transistor Q4 for driving the ground voltage from the fourth power supply pad Vss2 is provided.

The PMOS transistor Q3 receives the voltage from the second power supply pad Vcc1 via the resistor R according to the selection signal SE on the input line 21 via the inverter 22. The NMOS transistor Q4 supplies a line sense amplifier 60 to the line sense amplifier 60 by supplying a ground voltage from the fourth power pad Vss2 to the line sense amplifier 60. 60).

Here, a detailed description of the bit line detection amplifiers 50 and 60 will be omitted.

The role of the resistor R and the capacitor C1 will be described.

When the bit line sense amplifier performs an operation, a current flows from the gate node N2 of the capacitor C1 precharged to Vcc toward the bit line BL, / BL precharged to (Vcc / 2). As a result, the voltage level of the gate node N2 of the capacitor C1 drops. In order to recover this, the capacitor C1 receives current from the first and second power pads Vss1 and Vcc1.

Here, when the voltage (hereinafter, referred to as V ″) required by the capacitor C1 is obtained, the capacitance of each bit line BL or BL to be charged is set to Cb, and the gate voltage or the bit line of the capacitor after voltage distribution. If the voltage on (BL, / BL) is defined as V ', the following equation 1 is established.

As shown in Equation 1, V ″ is inversely proportional to the capacitor C1. In addition, V ″ is proportional to the maximum current value (hereinafter, Icc1) supplied by the second power supply pad Vcc1 to the memory block B0, and thus C1 and Icc1 may be inversely proportional to each other. Therefore, to decrease the maximum current value, increase C1. Therefore, the role of the capacitor C1 is to eliminate noise generated in the device by removing a large amplitude positive current value, that is, a high frequency component, which occurs momentarily.

Since the capacitor C2 also plays the same role as the capacitor C1, a detailed description thereof will be omitted.

In addition, the memory block B1 receives power from the second power pad Vcc1 via the resistor R, so that a maximum sensing current (hereinafter, referred to as Icc2) occurs later than Icc1. .

Therefore, the role of the resistor R is to increase the stability of the device by delaying and supplying energy corresponding to 1/2 of the largest energy generated in the semiconductor device.

Referring to FIG. 6, the operation of the capacitors C1, C2, and the resistor R will be described again.

From the current supplied to the memory block B0 by the second power pad Vcc1 (hereinafter referred to as Icc1) and the second power pad Vcc1 via the resistor R to the memory block B1. Since the supplied current Icc2 is different in time having a maximum value, the sum of the maximum sense currents of each memory block is reduced.

Accordingly, the capacitors C1 and C2 reduce the maximum sensing current of each memory block, and the resistor R is the remaining time of generating the maximum sensing current of the memory block corresponding to 1/2 of the plurality of memory blocks. By varying the memory blocks, the sum of the maximum sense currents of all memory blocks is reduced.

As described above, the power transmission circuit of the present invention implements a low pass filter by inserting a capacitor between the first power line and the power line for transmitting the second power voltage.

Thus, high frequency components included in the first and second power supply voltages are removed. In addition, the memory block corresponding to 1/2 of the plurality of memory blocks is supplied with a driving current through the resistor R, thereby preventing the generation of large energy inside the device, thereby improving the stability of the device.

Claims (1)

First to fourth memory blocks comprising a plurality of memory cell arrays having a plurality of bit lines, a first power pad for inputting a first power voltage from the outside, and a second power voltage from the outside A second power pad for input, a third power pad for inputting a second power voltage from the outside, and transmitting the first power voltage from the first power pad to the first and second memory blocks A first power line; a second power line for transferring the second power voltage from the second power pad to the first and second memory blocks; and the first power voltage from the first power pad. A third power line for transmitting to the third and fourth memory blocks, a fourth power line for transmitting the second power voltage from the third power pad to the third and fourth memory blocks, the first power line and Connected in parallel between the second power lines, and Two or more capacitors for delaying a high frequency component noise signal applied to the first and second power pads for a first predetermined time when the first and second memory blocks are driven, and the first power pad and the third power pad. Resistance means connected between a power supply line and the third power supply line and a fourth power supply line connected in parallel, and applied to the first and third power supply pads when the first and second memory blocks are driven. And at least two capacitors for delaying a high amplitude noise signal of a high frequency component by a second predetermined time different from the first predetermined time.