CN115001456A

CN115001456A - Dynamic latch, data operation unit, chip, computing force board and computing equipment

Info

Publication number: CN115001456A
Application number: CN202210829030.8A
Authority: CN
Inventors: 陈双文; 李智; 张楠赓
Original assignee: Shanghai Canaan Jiesi Information Technology Co ltd
Current assignee: Shanghai Canaan Jiesi Information Technology Co ltd
Priority date: 2022-07-14
Filing date: 2022-07-14
Publication date: 2022-09-02

Abstract

The invention provides a dynamic latch. The data transmission unit and the data output unit are sequentially connected in series between the input end and the output end, a node is arranged between the data transmission unit and the data output unit, and data input by the input end and data output by the output end are in reverse phase; the voltage compensation unit is used for providing a compensation voltage for the node and comprises a first end and a second end, wherein the first end is electrically connected to the node, and the second end is electrically connected to the first clock signal or the second clock signal. The voltage compensation can be performed on the dynamic node by increasing the coupling effect in the selected direction, and the holding time of the data latched by the dynamic node is increased.

Description

Dynamic latch, data operation unit, chip, computing force board and computing equipment

Technical Field

The present invention relates to a clocked memory device, and more particularly, to a dynamic latch, a data operation unit, a chip, an algorithm board, and a computing device, which are applied to a large-scale data operation device.

Background

Dynamic latches are widely used and can be used for registering digital signals. In the conventional dynamic latch, the transferred data is usually temporarily stored in the parasitic capacitance generated by the transistor constituting the latch unit. However, as the operation frequency is gradually increased, the temporarily stored data is prone to generate dynamic leakage, which results in insufficient data retention time, and further results in data loss and reduced operation accuracy. The current compensation, or increasing the capacitance at the dynamic node, is common. Current compensation or increased capacitance can affect the access speed of the dynamic latch.

Therefore, how to effectively increase the holding time of data in the dynamic latch is a problem to be solved.

Disclosure of Invention

In order to solve the above problems, the present invention provides a dynamic latch, which can effectively increase the data retention time and improve the data security and accuracy.

In order to achieve the above object, the present invention provides a dynamic latch, including an input terminal for inputting a first data; an output end for outputting a second data; a clock signal terminal for providing clock signals, wherein the clock signals comprise a first clock signal and a second clock signal; a data transmission unit for transmitting the first data under the control of the first clock signal and the second clock signal; the data output unit is used for outputting the data transmitted by the data transmission unit; the data transmission unit and the data output unit are sequentially connected in series between the input end and the output end, and a node is arranged between the data transmission unit and the data output unit; the voltage compensation unit is used for providing a compensation voltage for the node and comprises a first end and a second end, wherein the first end is electrically connected to the node, and the second end is electrically connected to the first clock signal or the second clock signal.

In the above dynamic latch, the compensation voltage is a positive compensation voltage or a negative compensation voltage.

In the above dynamic latch, the voltage compensation unit includes a PMOS transistor having a source terminal, a drain terminal and a gate terminal.

In the above dynamic latch, a source terminal and a drain terminal of the PMOS transistor are electrically connected to the node, and a gate terminal of the PMOS transistor is electrically connected to the first clock signal.

In the above dynamic latch, a source terminal and a drain terminal of the PMOS transistor are electrically connected to the node, and a gate terminal of the PMOS transistor is electrically connected to the second clock signal.

In the above dynamic latch, a source terminal and a drain terminal of the PMOS transistor are electrically connected to the first clock signal, and a gate terminal of the PMOS transistor is electrically connected to the node.

In the above dynamic latch, the source terminal and the drain terminal of the PMOS transistor are electrically connected to the second clock signal, and the gate terminal of the PMOS transistor is electrically connected to the node.

In an embodiment, the voltage compensation unit includes an NMOS transistor having a source terminal, a drain terminal and a gate terminal.

In the above dynamic latch, the source terminal and the drain terminal of the NMOS transistor are electrically connected to the node, and the gate terminal of the NMOS transistor is electrically connected to the first clock signal.

In the above dynamic latch, the source terminal and the drain terminal of the NMOS transistor are electrically connected to the node, and the gate terminal of the NMOS transistor is electrically connected to the second clock signal.

In the above dynamic latch, a source terminal and a drain terminal of the NMOS transistor are electrically connected to the first clock signal, and a gate terminal of the NMOS transistor is electrically connected to the node.

In the above dynamic latch, a source terminal and a drain terminal of the NMOS transistor are electrically connected to the second clock signal, and a gate terminal of the NMOS transistor is electrically connected to the node.

In the above dynamic latch, the data transmission unit is a transmission gate.

In the above dynamic latch, the transmission gate includes a plurality of PMOS transistors and a plurality of NMOS transistors, and the PMOS transistors and the NMOS transistors are respectively connected in parallel.

In the above dynamic latch, the data output unit is an inverter.

The dynamic latch of the invention can effectively increase the holding time of data and improve the safety and accuracy of the data.

In order to better achieve the above object, the present invention further provides a data operation unit, which includes a control circuit, an operation circuit, and a plurality of dynamic latches that are connected in series and/or in parallel; wherein the plurality of dynamic latches are any one of the above dynamic latches.

In order to better achieve the above object, the present invention further provides a chip, wherein at least one data operation unit as described above is included.

To better address the above-mentioned objectives, the present invention also provides an computing force board for a computing device, characterized by comprising at least one chip as described above.

In order to better achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink and a plurality of computing boards, wherein the control board is connected to the computing boards through the connecting board, the heat sink is disposed around the computing boards, the power board is used for providing power to the connecting board, the control board, the heat sink and the computing boards, and the computing boards are the computing boards as described above.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1A is a schematic diagram of a circuit structure of a dynamic latch according to an embodiment of the present invention;

FIG. 1B is a schematic diagram of a circuit structure of a dynamic latch according to an alternative embodiment of the present invention;

FIG. 2A is a schematic diagram of a dynamic latch according to another embodiment of the present invention;

FIG. 2B is a schematic diagram of a dynamic latch according to another alternative embodiment of the present invention;

FIG. 3A is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

FIG. 3B is a schematic diagram of a dynamic latch according to another alternative embodiment of the present invention;

FIG. 4A is a schematic diagram of a dynamic latch according to another embodiment of the present invention;

FIG. 4B is a schematic diagram of a dynamic latch according to still another alternative embodiment of the present invention;

FIG. 5 is a schematic diagram of a data operation unit according to the present invention;

FIG. 6 is a schematic diagram of a chip according to the present invention;

FIG. 7 is a schematic view of the force computing plate of the present invention;

FIG. 8 is a schematic diagram of a computing device according to the present invention.

Wherein, the reference numbers:

100: dynamic latch

101: data transmission unit

102: data output unit

103: voltage compensation unit

103P: PMOS transistor

103N: NMOS transistor

800: data arithmetic unit

801: control circuit

802: arithmetic circuit

900: chip and method for manufacturing the same

901: control unit

1000: force calculating board

1100: computing device

1101: connecting plate

1102: control panel

1103: heat radiator

1104: power panel

D: input terminal

Q: output end

CLK 1: first clock signal terminal

CLK 2: second clock signal terminal

CKP: first clock signal

CKN: second clock signal

S: node point

VDD: power supply

VSS: ground

Detailed Description

The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:

certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

The first embodiment is as follows:

fig. 1A is a schematic circuit diagram of a dynamic latch according to an embodiment of the present invention. As shown in FIG. 1A, the dynamic latch 100 of the present invention includes an input terminal D, an output terminal Q, a first clock signal terminal CLK1, a second clock signal terminal CLK2, a data transmission unit 101, and a data output unit 102. The data transmission unit 101 and the data output unit 102 are sequentially connected in series between the input end D and the output end Q, and a node S is formed between the data transmission unit 101 and the data output unit 102. The input end D of the dynamic latch 100 is used for inputting first data to be transmitted from the outside to the dynamic latch 100, the output end Q is used for outputting second data to be transmitted from the dynamic latch 100 to the outside, the first clock signal end CLK1 and the second clock signal end CLK2 are used for providing clock control signals to the dynamic latch 100, and the clock control signals include a first clock signal CKP and a second clock signal CKN to control the data transmission unit 101 to be turned on and turned off. The first clock signal CKP and the second clock signal CKN are inverted clock signals, and the second data output by the output terminal Q and the first data input by the input terminal are inverted data signals.

When a PMOS tube and an NMOS tube are connected in parallel, a transmission gate can be formed, wherein the source electrodes of the two tubes are connected as an input end, the drain electrodes of the two tubes are connected as an output end, and the grid electrodes of the two tubes are used as control ends. Specifically, as shown in fig. 1A, the data transmission unit 101 of the dynamic latch 100 has a transmission gate structure, and the data transmission unit 101 includes a PMOS transistor and an NMOS transistor connected in parallel. One end of the data transmission unit 101 is electrically connected to the input end D, and the other end of the data transmission unit 101 is electrically connected to the node S. The gate terminal of the NMOS transistor of the data transmission unit 101 is electrically connected to the second clock signal CKN, and the gate terminal of the PMOS transistor is electrically connected to the first clock signal CKP. When the first clock signal CKP is at a low level, the second clock signal CKN is at a rising edge, the PMOS transistor and the NMOS transistor of the data transmission unit 101 are both in a conducting state, and the input terminal D transmits the data to be transmitted to the node S through the data transmission unit 101. When the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, the PMOS transistor and the NMOS transistor of the data transmission unit 101 are both in a non-conductive state, the data at the input end D cannot be transmitted to the node S through the data transmission unit 101, and the data transmission unit 101 latches the data transmitted to the node S in the previous time period. In this embodiment, the data transmission unit 101 is exemplified by a transmission gate structure, but of course, other types of analog switch units may be used, such as a tri-state inverter, a transmission gate and an inverter connected in series, and the like, as long as the switch function can be realized under the control of the clock signal, and the invention is not limited thereto.

In order to increase the transmission speed, the data transmission unit 101 of the present invention may further include a plurality of PMOS transistors and a plurality of NMOS transistors, and the plurality of PMOS transistors and the plurality of NMOS transistors are respectively connected in parallel.

As shown in fig. 1A, the data output unit 102 of the dynamic latch 100 of the present invention is an inverter structure, inverts and outputs data received from the data transmission unit 101 to form data of an opposite phase to data of the input terminal D, and outputs the data through the output terminal Q. Meanwhile, the data output unit 102 can also improve the driving capability of data.

Dynamic latch 100 also includes a voltage compensation unit 103. In the present embodiment, the voltage compensation unit 103 includes a PMOS transistor 103P, and the PMOS transistor 103P is electrically connected to the node S. Specifically, the source terminal and the drain terminal of the PMOS transistor 103P are connected in parallel and electrically connected to the node S, and the gate terminal of the PMOS transistor 103P is electrically connected to the first clock signal CKP.

When the first clock signal CKP rises from a low level to a high level, the data transmission unit 101 changes from an on state to an off state, the data transmitted from the input terminal D is latched at the node S, where the voltage at the node S is Vs, which is the same as the power supply voltage Vdd when the latched data is "1", and which is the same as the ground voltage Vss when the latched data is "0". Since the gate terminal of the PMOS transistor 103P in the voltage compensation unit 103 is electrically connected to the first clock signal CKP, and the first clock signal CKP is at the rising edge, the voltage compensation unit 103 provides the positive compensation voltage Δ V to the node S, and the voltage at the node S should be Vs + Δ V after compensation. Therefore, the voltage compensation unit 103 provides a positive compensation voltage to the node S, so that the high-level data retention time can be prolonged, the stability of data storage can be improved, and the safety and accuracy of data can be enhanced.

When the first clock signal CKP goes from high level to low level, the data transmission unit 101 changes from off state to on state, the data latched at the node S will be overwritten by the data transmitted from the input terminal D, and the dynamic latch 100 is in normal operation.

Fig. 1B is a schematic circuit diagram of a dynamic latch according to a modified embodiment of the present invention. The difference from the embodiment shown in fig. 1A is in the specific connection manner of the PMOS transistor 103P in the voltage compensation unit 103. As shown in fig. 1B, in the present embodiment, the source terminal and the drain terminal of the PMOS transistor 103P are connected in parallel and electrically connected to the node S, and the gate terminal of the PMOS transistor 103P is electrically connected to the second clock signal CKN.

Similarly, when the first clock signal CKP rises from a low level to a high level, the second clock signal CKN falls from a high level to a low level, the data transmission unit 101 changes from an on state to an off state, the data transmitted from the input terminal D is latched at the node S where the voltage at the node S is Vs, and when the latched data is "1", Vs is the same as the power supply voltage Vdd, and when the latched data is "0", Vs is the same as the ground voltage Vss. Since the gate terminal of the PMOS transistor 103P in the voltage compensation unit 103 is electrically connected to the second clock signal CKN, and the second clock signal CKN is at the falling edge, the voltage compensation unit 103 provides the negative compensation voltage Δ V to the node S, and the voltage at the node S should be Vs- Δ V after compensation. Therefore, the voltage compensation unit 103 provides a negative compensation voltage to the node S, so that the low-level data retention time can be prolonged, the stability of data storage can be improved, and the safety and accuracy of data can be further enhanced.

When the first clock signal CKP is lowered from a high level to a low level, the second clock signal CKN is raised from a low level to a high level, the data transmission unit 101 is turned from an off state to an on state, the data latched at the node S is overwritten by the data transmitted from the input terminal D, and the dynamic latch 100 is in a normal operation state.

Fig. 2A is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention. The difference from the embodiment shown in fig. 1A is that the voltage compensation unit 103 includes an NMOS transistor 103N, and the NMOS transistor 103N is electrically connected to the node S. Specifically, the source terminal and the drain terminal of the NMOS transistor 103N are connected in parallel and electrically connected to the node S, and the gate terminal of the NMOS transistor 103N is electrically connected to the second clock signal CKN.

Similarly, when the first clock signal CKP rises from a low level to a high level, the second clock signal CKN falls from a high level to a low level, the data transmission unit 101 changes from an on state to an off state, the data transmitted from the input terminal D is latched at the node S where the voltage at the node S is Vs, and when the latched data is "1", Vs is the same as the power supply voltage Vdd, and when the latched data is "0", Vs is the same as the ground voltage Vss. Since the gate terminal of the NMOS transistor 103N in the voltage compensation unit 103 is electrically connected to the second clock signal CKN, and the second clock signal CKN is at the falling edge, the voltage compensation unit 103 provides the negative compensation voltage Δ V to the node S, and the voltage at the node S should be Vs- Δ V after compensation. Therefore, the voltage compensation unit 103 provides a negative compensation voltage to the node S, so that the low-level data retention time can be prolonged, the stability of data storage can be improved, and the safety and accuracy of data can be further enhanced.

When the first clock signal CKP is lowered from high level to low level, the second clock signal CKN is raised from low level to high level, the data transmission unit 101 is turned from off state to on state, the data latched at the node S is rewritten by the data transmitted from the input terminal D, and the dynamic latch 100 is in a normal operation state.

Fig. 2B is a schematic circuit diagram of a dynamic latch according to another modified embodiment of the present invention. The difference from the embodiment shown in fig. 2A is that the specific connection manner of the NMOS transistor 103N in the voltage compensation unit 103 is different. As shown in fig. 2B, in the present embodiment, the source terminal and the drain terminal of the NMOS transistor 103N are connected in parallel and electrically connected to the node S, and the gate terminal of the NMOS transistor 103N is electrically connected to the first clock signal CKP.

Similarly, when the first clock signal CKP rises from a low level to a high level, the second clock signal CKN falls from a high level to a low level, the data transmission unit 101 changes from an on state to an off state, the data transmitted from the input terminal D is latched at the node S where the voltage at the node S is Vs, and when the latched data is "1", Vs is the same as the power supply voltage Vdd, and when the latched data is "0", Vs is the same as the ground voltage Vss. Since the gate terminal of the NMOS transistor 103N in the voltage compensation unit 103 is electrically connected to the first clock signal CKP, and the first clock signal CKP is at the rising edge, the voltage compensation unit 103 provides the positive compensation voltage Δ V to the node S, and the voltage at the node S should be Vs + Δ V after compensation. Therefore, the voltage compensation unit 103 provides a positive compensation voltage to the node S, so that the high-level data retention time can be prolonged, the stability of data storage can be improved, and the safety and accuracy of data can be enhanced.

Fig. 3A is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention, and fig. 3B is a schematic circuit diagram of a dynamic latch according to another modified embodiment of the present invention. The dynamic latch shown in fig. 3A and 3B corresponds to the dynamic latch shown in fig. 1A and 1B, respectively, and only differs in the specific connection manner of the PMOS transistor 103P in the voltage compensation unit 103. Refer to the drawings specifically, and are not described in detail herein.

Fig. 4A is a schematic circuit diagram of a dynamic latch according to still another embodiment of the present invention, and fig. 4B is a schematic circuit diagram of a dynamic latch according to still another modified embodiment of the present invention. The dynamic latch shown in fig. 4A and 4B corresponds to the dynamic latch shown in fig. 2A and 2B, respectively, and only differs in the specific connection manner of the NMOS transistor 103N in the voltage compensation unit 103. Refer to the drawings specifically, and are not described in detail herein.

In the above embodiments, a connection manner of the PMOS transistor and the NMOS transistor is taken as an illustration, wherein the source and the drain of the PMOS transistor and the drain of the NMOS transistor can be interchanged, and the invention is not limited thereto.

The invention also provides a data operation unit, and fig. 5 is a schematic structural diagram of the data operation unit of the invention. As shown in fig. 5, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of dynamic latches 100, and the plurality of dynamic latches 100 are connected in series or in parallel. The control circuit 801 refreshes data in the dynamic latch 100 and reads the data from the dynamic latch 100, and the arithmetic circuit 802 performs arithmetic on the read data and outputs the arithmetic result from the control circuit 801.

The invention also provides a chip, and fig. 6 is a schematic structural diagram of the chip of the invention. As shown in fig. 6, the chip 900 includes a control unit 901, and one or more data operation units 800. The control unit 901 inputs data to the data operation unit 800 and processes the data output by the data operation unit 800.

The invention also provides a force calculating board, and fig. 7 is a schematic structural diagram of the force calculating board. As shown in fig. 7, each computation board 1000 includes one or more chips 900 thereon for performing large-scale computation on the working data sent by the computing device.

The invention also provides a computing device, which is preferably used for the operation of mining the virtual digital currency, but can be used for any other massive operation. FIG. 8 is a schematic diagram of a computing device according to the present invention. As shown in fig. 8, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power board 1104, and one or more computing boards 1000. The control board 1102 is connected to the force computing board 1000 through a connection board 1101, and a heat sink 1103 is provided around the force computing board 1000. The power board 1104 is used to supply power to the connection board 1101, the control board 1102, the heat sink 1103, and the computing power board 1000.

It should be noted that in the description of the present invention, the terms "transverse", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, which are merely for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

In other words, the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it is intended that all such changes and modifications be considered as within the spirit and scope of the appended claims.

Claims

1. A dynamic latch, comprising:

an input end for inputting a first data;

the output end is used for outputting second data;

a clock signal terminal for providing clock signals, wherein the clock signals comprise a first clock signal and a second clock signal;

a data transmission unit for transmitting the first data under the control of the first clock signal and the second clock signal;

the data output unit is used for outputting the data transmitted by the data transmission unit;

the data transmission unit and the data output unit are sequentially connected in series between the input end and the output end, and a node is arranged between the data transmission unit and the data output unit;

the voltage compensation unit is used for providing a compensation voltage for the node and comprises a first end and a second end, wherein the first end is electrically connected to the node, and the second end is electrically connected to the first clock signal or the second clock signal.

2. The dynamic latch of claim 1, wherein: the compensation voltage is a positive compensation voltage or a negative compensation voltage.

3. The dynamic latch of claim 1, wherein: the voltage compensation unit comprises a PMOS transistor which is provided with a source end, a drain end and a grid end.

4. The dynamic latch of claim 3, wherein: the source terminal and the drain terminal of the PMOS transistor are electrically connected to the node, and the gate terminal of the PMOS transistor is electrically connected to the first clock signal.

5. The dynamic latch of claim 3, wherein: the source terminal and the drain terminal of the PMOS transistor are electrically connected to the node, and the gate terminal of the PMOS transistor is electrically connected to the second clock signal.

6. The dynamic latch of claim 3, wherein: the source terminal and the drain terminal of the PMOS transistor are electrically connected to the first clock signal, and the gate terminal of the PMOS transistor is electrically connected to the node.

7. The dynamic latch of claim 3, wherein: the source terminal and the drain terminal of the PMOS transistor are electrically connected to the second clock signal, and the gate terminal of the PMOS transistor is electrically connected to the node.

8. The dynamic latch of claim 1, wherein: the voltage compensation unit comprises an NMOS transistor, and the NMOS transistor is provided with a source end, a drain end and a grid end.

9. The dynamic latch of claim 8, wherein: the source terminal and the drain terminal of the NMOS transistor are electrically connected to the node, and the gate terminal of the NMOS transistor is electrically connected to the first clock signal.

10. The dynamic latch of claim 8, wherein: the source terminal and the drain terminal of the NMOS transistor are electrically connected to the node, and the gate terminal of the NMOS transistor is electrically connected to the second clock signal.

11. The dynamic latch of claim 8, wherein: the source terminal and the drain terminal of the NMOS transistor are electrically connected to the first clock signal, and the gate terminal of the NMOS transistor is electrically connected to the node.

12. The dynamic latch of claim 8, wherein: the source terminal and the drain terminal of the NMOS transistor are electrically connected to the second clock signal, and the gate terminal of the NMOS transistor is electrically connected to the node.

13. The dynamic latch of claim 1, wherein: the data transmission unit is a transmission gate.

14. The dynamic latch of claim 13, wherein: the transmission gate comprises a plurality of PMOS transistors and a plurality of NMOS transistors, and the PMOS transistors and the NMOS transistors are respectively connected in parallel.

15. The dynamic latch of claim 1, wherein: the data output unit is an inverter.

16. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of dynamic latches which are connected in an interconnecting way, wherein the plurality of dynamic latches are connected in series and/or in parallel; the method is characterized in that: the plurality of dynamic latches are as claimed in any one of claims 1 to 15.

17. A chip comprising at least one data arithmetic unit as claimed in claim 16.

18. An computing force board for a computing device comprising at least one chip as recited in claim 17.

19. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force computing board is as claimed in claim 18.