CN210899130U - Dynamic latch, data operation unit, chip, force calculation board and computing equipment - Google Patents

Abstract

The utility model provides a dynamic latch, data arithmetic unit, chip, calculation power board and computational equipment. The dynamic latch comprises an input end and a control end, wherein the input end is used for inputting data; an output terminal for outputting the data; a clock signal terminal for providing a clock signal; a data latch unit for latching the data under the control of the clock signal; a data holding unit for holding the data transmitted by the data latch unit; the data latch unit and the data holding unit are connected in series between the input end and the output end, and a node is arranged between the data latch unit and the data holding unit; the leakage compensation unit is electrically connected between the input end and the node. The dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

Description

Dynamic latch, data operation unit, chip, force calculation board and computing equipment

Technical Field

The utility model relates to a by clock control's storage device, especially relate to a dynamic latch, data arithmetic element, chip, calculation power board and the computational device who uses in extensive data arithmetic device.

Background

Dynamic latches are widely used and can be used for registering digital signals. Fig. 1 is a circuit configuration diagram of a conventional dynamic latch. As shown in fig. 1, the dynamic latch 100 includes a tri-state inverter 101 and an inverter 102 connected in series between an input terminal D and an output terminal Q. A node S0 is formed between the tristate inverter 101 and the inverter 102, the tristate inverter 101 is controlled by two inverted clock signals CKN and CKP, when CKP is '0', CKN is '1', the tristate inverter 101 is conducted, and the data of the input end D is transmitted to the output end through the tristate inverter 101 and the inverter 102; when CKN is "0", CKP is "1", tristate inverter 101 is not turned on, the data at input terminal D cannot pass through tristate inverter 101, and the data at node S0 is temporarily stored through the parasitic capacitance of the transistor in inverter 102. In the off state of the tri-state inverter 101, when the data at the input terminal D changes, the data at the node S0 is prone to generate dynamic leakage, resulting in the temporary data loss.

Therefore, how to effectively reduce the dynamic leakage of the dynamic latch is a problem to be solved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a dynamic latch is provided, the dynamic leakage current of node can effectively be compensated, the security and the exactness of data are improved.

In order to achieve the above object, the present invention provides a dynamic latch, comprising an input terminal for inputting a data; an output terminal for outputting the data; a clock signal terminal for providing a clock signal; a data latch unit for latching the data under the control of the clock signal; a data holding unit for holding the data transmitted by the data latch unit; the data latch unit and the data holding unit are connected in series between the input end and the output end, and a node is arranged between the data latch unit and the data holding unit; the leakage compensation unit is electrically connected between the input end and the node.

In the above dynamic latch, the leakage compensation unit has a first end, a second end and a control end, the first end is electrically connected to the input end, and the second end is electrically connected to the node.

In the above dynamic latch, the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the input terminal and the node.

In the above dynamic latch, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the node, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the input terminal.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the input terminal.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

In the above dynamic latch, the leakage compensation unit includes an NMOS transistor having a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the node, the source terminal is electrically connected to the input terminal, and the gate terminal is electrically connected to a ground.

In the above dynamic latch, the leakage compensation unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the node, the drain terminal of the PMOS transistor is electrically connected to the input terminal, and the gate terminal of the PMOS transistor is electrically connected to a power supply.

In the above dynamic latch, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are inverted.

In the above dynamic latch, the data latch unit is a tri-state inverter.

In the above dynamic latch, the data holding unit is an inverter.

Use the utility model discloses a dynamic latch can follow input feedback leakage current to node, and the dynamic leakage current of compensation node improves data storage's stability, and then strengthens the security and the exactness of data.

In order to better achieve the above object, the present invention further provides a data operation unit, which comprises a control circuit, an operation circuit, and a plurality of dynamic latches connected in series and/or in parallel; wherein the plurality of dynamic latches are any one of the dynamic latches described above.

In order to better achieve the above object, the present invention further provides a chip, wherein the chip comprises at least one data operation unit.

To better achieve the above objects, the present invention also provides a computing board for a computing device, wherein at least one chip as described above is included.

In order to better achieve the above object, the utility model also provides a computing device, including power strip, control panel, connecting plate, radiator and a plurality of power strip, the control panel passes through the connecting plate with power strip connects, the radiator sets up around power strip, the power strip be used for to the connecting plate the control panel the radiator and power strip provides the power, wherein, power strip is foretell power strip.

The utility model has the beneficial effects that: the dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

The present invention will be described in detail with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.

Drawings

FIG. 1 is a schematic diagram of a conventional dynamic latch circuit;

fig. 2 is a schematic circuit diagram of a dynamic latch according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a dynamic latch according to yet another embodiment of the present invention;

fig. 6 is a schematic circuit structure diagram of a dynamic latch according to an expanded embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of the data operation unit of the present invention;

fig. 9 is a schematic structural diagram of the chip of the present invention;

fig. 10 is a schematic structural view of the force calculating plate of the present invention;

fig. 11 is a schematic structural diagram of the computing device of the present invention.

Wherein, the reference numbers:

100. 200: dynamic latch

101: three-state inverter

102: inverter with a capacitor having a capacitor element

201: data latch unit

202: data holding unit

203: leakage compensation unit

201P1, 201P2, 203P: PMOS transistor

201N1, 201N2, 203N: NMOS transistor

800: data arithmetic unit

801: control circuit

802: arithmetic circuit

900: chip and method for manufacturing the same

901: control unit

1000: force calculating board

1100: computing device

1101: connecting plate

1102: control panel

1103: heat radiator

1104: power panel

D: input terminal

Q: output end

CKP, CKN: clock signal

S0, S1: node point

Detailed Description

The following describes the structural and operational principles of the present invention in detail with reference to the accompanying drawings:

certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

The first embodiment is as follows:

fig. 2 is a schematic circuit diagram of a dynamic latch according to an embodiment of the present invention. As shown in fig. 2, the dynamic latch 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a data latch unit 201, a data holding unit 202, and a leakage compensation unit 203. The data latch unit 201 and the data holding unit 202 are connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the data latch unit 201 and the data holding unit 202. The leakage compensation unit 203 is electrically connected between the node S0 and the input terminal D. The input end D is used for inputting data, the output end Q is used for outputting data input by the input end D, the clock signal end CKN and the clock signal end CKP are used for providing a clock signal CKN and a clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

Specifically, as shown in fig. 2, the data latch unit 201 of the dynamic latch 200 is a tri-state inverter structure, and the data latch unit 201 includes PMOS transistors 201P1, 201P2 and NMOS transistors 201N1, 201N2 connected in series between a power supply VDD and ground VSS. The gate terminals of the PMOS transistor 201P1 and the NMOS transistor 201N2 are connected together to form an input terminal of the data latch unit 201. The drain terminals of the PMOS transistor 201P2 and the NMOS transistor 201N1 are connected together to form an output terminal of the data latch unit 201. The source terminal of PMOS transistor 201P1 is connected to power VDD, and the source terminal of NMOS transistor 201N2 is connected to ground VSS. The source terminal of PMOS transistor 201P2 is connected to the drain terminal of PMOS transistor 201P1, and the source terminal of NMOS transistor 201N1 is connected to the drain terminal of NMOS transistor 201N 2.

In the present embodiment, the gate terminal of the PMOS transistor 201P2 is controlled by the clock signal CKP, and the gate terminal of the NMOS transistor 201N1 is controlled by the clock signal CKN as the clock control terminal of the data latch unit 201. Of course, the gate terminal of the PMOS transistor 201P1 may be controlled by the clock signal CKP, and the gate terminal of the NMOS transistor 201N2 may be controlled by the clock signal CKN, which is not limited by the present invention.

When CKP is low, CKN is high, both the PMOS transistor 201P2 and the NMOS transistor 201N1 are turned on, and the data latch unit 201 inverts the data from the input terminal D and transmits the inverted data to the data holding unit 202, i.e. writes the data from the input terminal D into the node S0.

When CKP is high, CKN is low, both PMOS transistor 201P2 and NMOS transistor 201N1 are in a non-conducting state, the data latch unit 201 is in a high-impedance state, the data at the input end D cannot pass through the data latch unit 201, and the data at the node S0 is latched and kept in the original state, thereby playing a role of data registration.

With continued reference to fig. 2, the data holding unit 202 of the dynamic latch 200 is an inverter structure, and the data holding unit 202 can use its parasitic capacitance to temporarily store the data transmitted from the data latch unit 201, i.e. the data at the node S0, and can also invert the data at the node S0 and transmit the inverted data to the output terminal of the dynamic latch 200. It can be seen that the data at the node S0 and the input terminal D are inverted data, the data at the output terminal Q and the node S0 are also inverted data, and the data at the input terminal D and the output terminal Q are identical data.

It can be seen that the data latch unit 201 is controlled by the clock signal to transfer the data of the input terminal D to the data holding unit 202, and the data of the input terminal D of the dynamic latch 200 passes through the data latch unit 201 and the twice inversion of the data holding unit 202, so that the data of the output terminal Q and the data of the input terminal D are kept in phase. Meanwhile, the data holding unit 202 may also function to improve the data driving capability.

As shown in fig. 2, the dynamic latch 200 further includes a leakage compensation unit 203. In the present embodiment, the leakage compensation unit 203 includes a PMOS transistor 203P and an NMOS transistor 203N, and the PMOS transistor 203P and the NMOS transistor 203N are connected in series between the input terminal D and the node S0. The source terminal of the PMOS transistor 203P is electrically connected to the node S0, the drain terminal of the PMOS transistor 203P is electrically connected to the drain terminal of the NMOS transistor 203N, the source terminal of the NMOS transistor 203N is electrically connected to the input terminal D, and the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are connected together in parallel and are electrically connected to the node S0.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to the node S0, under the driving of the same level signal, the PMOS transistor 203P and the NMOS transistor 203N are not turned on at the same time, and only one of them is turned on and the other is turned off. For example, when the potential at the node S0 is high level, the PMOS transistor 203P is in an off state, and the NMOS transistor 203N is in an on state; when the potential at the node S0 is low, the PMOS transistor 203P is in an on state, and the NMOS transistor 203N is in an off state.

When the data latch unit 201 is in the on state, the data at the input terminal D of the dynamic latch 200 is normally written.

When the data latch unit 201 is in the high impedance state, the data of the dynamic latch 200 is held at the node S0. When the data on the input terminal D changes, for example, when the data on the input terminal D changes from "0" to "1", the data on the node S0 needs to keep the state of "1", the NMOS transistor 201N2 in the data latch unit 201 changes from off to on, and the data on the node S0 is dynamically leaked through the NMOS transistor 201N1 and the NMOS transistor 201N 2. At this time, the leakage compensation unit 203 may feed back the current of the input terminal D to the node S0, compensate the dynamic leakage current at the node S0, and increase the stability of the data at the node S0.

Similarly, when the data at the input terminal D changes from "1" to "0", the data at the node S0 needs to keep the state of "0", the PMOS transistor 201P1 in the data latch unit 201 changes from off to on, and the data at the node S0 dynamically leaks through the PMOS transistor 201P1 and the PMOS transistor 201P 2. At this time, the leakage compensation unit 203 may feed back the leakage current of the input terminal D to the node S0, compensate the dynamic leakage current at the node S0, and improve the stability of data storage, thereby enhancing the security and accuracy of data.

Example two:

fig. 3 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention. As shown in fig. 3, the difference from the embodiment shown in fig. 2 is that in the present embodiment, in the leakage compensation unit 203, the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are connected together in parallel and are electrically connected to the input terminal D.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to the input terminal D, the PMOS transistor 203P and the NMOS transistor 203N are not turned on simultaneously under the driving of the same level signal, and only one of them is turned on and the other is turned off. For example, when the potential of the input terminal D is high level, the PMOS transistor 203P is in an off state, and the NMOS transistor 203N is in an on state; when the potential of the input terminal D is low, the PMOS transistor 203P is in an on state, and the NMOS transistor 203N is in an off state. Therefore, the leakage compensation unit 203 can feed back the leakage current of the input terminal D to the node S0, compensate the leakage current at the node S0, and improve the stability of data storage, thereby enhancing the safety and accuracy of data.

Modification example:

fig. 4 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and fig. 4, the difference between the embodiments shown in fig. 2 is that in the leakage compensation unit 203 of the present embodiment, the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are connected together in parallel and are electrically connected to the power supply VDD.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to the power supply VDD, the PMOS transistor 203P is in the off state and the NMOS transistor 203N is in the on state under the driving of the high-level signal of the power supply VDD. Therefore, the leakage compensation unit 203 can feed back the leakage current of the input terminal D to the node S0, compensate the leakage current at the node S0, and improve the stability of data storage, thereby enhancing the safety and accuracy of data.

Fig. 5 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and fig. 5, the difference between the embodiments shown in fig. 2 is that in the leakage compensation unit 203 of the present embodiment, the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are connected together in parallel and are electrically connected to the ground VSS.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to ground VSS, the PMOS transistor 203P is in the on state and the NMOS transistor 203N is in the off state under the driving of the signal with low level of ground VSS. Therefore, the leakage compensation unit 203 can feed back the leakage current of the input terminal D to the node S0, compensate the leakage current at the node S0, and improve the stability of data storage, thereby enhancing the safety and accuracy of data.

Fig. 6 is a schematic circuit diagram of an embodiment of the dynamic register with leakage compensation according to the present invention. As shown in fig. 6, the leakage compensation unit 203 of the leakage compensation dynamic register 200 includes an NMOS transistor 203N, a source terminal of the NMOS transistor 203N is electrically connected to the node S0, a drain terminal of the NMOS transistor 203N is electrically connected to the output terminal Q, and a gate terminal of the NMOS transistor 203N is electrically connected to the ground VSS.

Since the gate terminal of the NMOS transistor 203N is electrically connected to ground VSS, the NMOS transistor 203N is in the off state driven by the low level signal of ground VSS. Therefore, the leakage compensation unit 203 can feed back the leakage current of the input terminal D to the node S0, compensate the leakage current at the node S0, and improve the stability of data storage, thereby enhancing the safety and accuracy of data.

Fig. 7 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 7, the leakage compensation unit 203 of the leakage compensation dynamic register 200 includes a PMOS transistor 203P, a source terminal of the PMOS transistor 203P is electrically connected to the output terminal, a drain terminal of the PMOS transistor 203P is electrically connected to the node S0, and a gate terminal of the PMOS transistor 203P is electrically connected to the power VDD.

Since the gate terminal of the PMOS transistor 203P is electrically connected to the power supply VDD, the PMOS transistor 203P is in the off state driven by the high level signal of the power supply VDD. Therefore, the leakage compensation unit 203 can feed back the leakage current of the input terminal D to the node S0, compensate the leakage current at the node S0, and improve the stability of data storage, thereby enhancing the safety and accuracy of data.

The utility model also provides a data arithmetic unit, figure 8 is the utility model discloses data arithmetic unit's schematic structure diagram. As shown in fig. 8, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of dynamic latches 200. The control circuit 801 refreshes data in the dynamic latch 200 and reads the data from the dynamic latch 200, and the arithmetic circuit 802 performs arithmetic on the read data and outputs the arithmetic result from the control circuit 801.

The utility model also provides a chip, fig. 9 is the utility model discloses the structural schematic of chip. As shown in fig. 9, the chip 900 includes a control unit 901, and one or more data operation units 900. The control unit 901 inputs data to the data operation unit 900 and processes the data output by the data operation unit 900.

The utility model discloses still provide a calculate the power board, fig. 10 is the utility model discloses calculate the structural schematic diagram of power board. As shown in fig. 10, each computing board 1000 includes one or more chips 900 for performing large-scale operations on the working data sent by the computing device.

The utility model also provides a computing equipment, computing equipment is preferred to be used for excavating the operation of virtual digital currency, of course computing equipment also can be used for any other magnanimity operation. Fig. 11 is a schematic structural diagram of the computing device of the present invention. As shown in fig. 11, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power board 1104, and one or more computing boards 1000. The control board 1102 is connected to the force computing board 1000 via a connection board 1101, and a heat sink 1103 is disposed around the force computing board 1000. The power board 1104 is used for supplying power to the connection board 1101, the control board 1102, the heat sink 1103 and the computing power board 1000.

It should be noted that, in the description of the present invention, the terms "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In other words, the present invention may have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims (17)

1. A dynamic latch, comprising:

an input end for inputting a data;

an output terminal for outputting the data;

a clock signal terminal for providing a clock signal;

a data latch unit for latching the data under the control of the clock signal;

a data holding unit for holding the data transmitted by the data latch unit;

the data latch unit and the data holding unit are connected in series between the input end and the output end, and a node is arranged between the data latch unit and the data holding unit;

the leakage compensation unit is electrically connected between the input end and the node.

2. The dynamic latch of claim 1, wherein: the leakage compensation unit has a first end, a second end and a control end, wherein the first end is electrically connected to the input end, and the second end is electrically connected to the node.

3. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises a PMOS transistor and an NMOS transistor which are connected in series between the input end and the node.

4. The dynamic latch of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the node, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the input terminal.

5. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the node.

6. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the input end.

7. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to a power supply.

8. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the ground.

9. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises an NMOS transistor, wherein the NMOS transistor is provided with a source end, a drain end and a grid end, the drain end of the NMOS transistor is electrically connected to the node, the source end is electrically connected to the input end, and the grid end is electrically connected to the ground.

10. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises a PMOS transistor, wherein the PMOS transistor is provided with a source end, a drain end and a grid end, the source end of the PMOS transistor is electrically connected to the node, the drain end of the PMOS transistor is electrically connected to the input end, and the grid end of the PMOS transistor is electrically connected to a power supply.

11. The dynamic latch of claim 1, wherein: the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

12. The dynamic latch of claim 1, wherein: the data latch unit is a tri-state inverter.

13. The dynamic latch of claim 1, wherein: the data holding unit is an inverter.

14. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of dynamic latches which are connected in an interconnecting way, wherein the plurality of dynamic latches are connected in series and/or in parallel; the method is characterized in that: the plurality of dynamic latches are as claimed in any one of claims 1 to 13.

15. A chip comprising at least one data arithmetic unit as claimed in claim 14.

16. An computing force board for a computing device comprising at least one chip as recited in claim 15.

17. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force computing board is as claimed in claim 16.

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