CN211209690U

CN211209690U - Dynamic latch, data operation unit, chip, force calculation board and computing equipment

Info

Publication number: CN211209690U
Application number: CN201921985791.2U
Authority: CN
Inventors: 刘杰尧; 张楠赓; 吴敬杰; 马晟厚
Original assignee: Hangzhou Canaan Creative Information Technology Ltd
Current assignee: Hangzhou Canaan Creative Information Technology Ltd
Priority date: 2019-09-30
Filing date: 2019-11-15
Publication date: 2020-08-07
Anticipated expiration: 2029-11-15
Also published as: CN110912548A

Abstract

The utility model provides a dynamic latch, data arithmetic unit, chip, calculation power board and computational equipment. The dynamic latch comprises an input end, an in-phase output end, an anti-phase output end, a clock signal end, a data transmission unit, an in-phase data holding unit and an anti-phase data holding unit, wherein the data transmission unit, the in-phase data holding unit and the anti-phase data holding unit are sequentially connected in series between the input end and the in-phase output end, a first node is arranged between the data transmission unit and the in-phase data holding unit, a second node is arranged between the in-phase data holding unit and the anti-phase data holding unit, and the anti-phase output end is electrically connected to the second node; the power supply further comprises a leakage compensation unit electrically connected between the in-phase output end and the first node. The dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

Description

Dynamic latch, data operation unit, chip, force calculation board and computing equipment

Technical Field

The utility model relates to a by clock control's storage device, especially relate to a dynamic latch, data arithmetic element, chip, calculation power board and the computational device who uses in extensive data arithmetic device.

Background

Dynamic latches are widely used and can be used for registering digital signals. Fig. 1 is a circuit configuration diagram of a conventional dynamic latch. As shown in fig. 1, the dynamic latch 100 includes a transmission gate 101, an inverter 102, and an inverter 103 connected in series between an input terminal D and a non-inverting output terminal Q. A node S0 is formed between the transmission gate 101 and the inverter 102, a node S1 is formed between the inverter 102 and the inverter 103, and data is temporarily stored at the node S0 and/or the node S1 by the parasitic capacitances of the transistors in the inverter 102 and the inverter 103. The dynamic latch outputs data in phase with the data at the input terminal D through the in-phase output terminal Q, and outputs data in phase opposite to the data at the input terminal D through the inverted output terminal QN, however, dynamic leakage is easily generated at the node S0 and the node S1, resulting in temporary data loss.

Therefore, how to effectively reduce the dynamic leakage of the dynamic latch is a problem to be solved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a dynamic latch is provided, the dynamic leakage current of node can effectively be compensated, the security and the exactness of data are improved.

In order to achieve the above object, the present invention provides a dynamic latch, comprising an input terminal for inputting a data; a non-inverting output terminal for outputting the data in an inverting manner; the inverting output end is used for inverting and outputting the data; a clock signal terminal for providing a clock signal; a data transmission unit for transmitting the data under the control of the clock signal; an in-phase data holding unit for holding the data transmitted by the data transmission unit in phase; an inverted data holding unit for inverting and holding the data transmitted by the data transmission unit; the data transmission unit, the in-phase data holding unit and the reverse-phase data holding unit are sequentially connected in series between the input end and the in-phase output end, a first node is arranged between the data transmission unit and the in-phase data holding unit, a second node is arranged between the in-phase data holding unit and the reverse-phase data holding unit, and the reverse-phase output end is electrically connected to the second node; the power supply further comprises a leakage compensation unit electrically connected between the in-phase output end and the first node.

In the above dynamic latch, the leakage compensation unit has a first end, a second end and a control end, the first end is electrically connected to the in-phase output end, and the second end is electrically connected to the first node.

In the above dynamic latch, the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the non-inverting output terminal and the first node.

In the above dynamic latch, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the first node.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the first node.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the second node.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

In the above dynamic latch, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

In the above dynamic latch, the leakage compensation unit includes an NMOS transistor, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the in-phase output terminal, the source terminal is electrically connected to the first node, and the gate terminal is electrically connected to a ground.

In the above dynamic latch, the leakage compensation unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal of the PMOS transistor is electrically connected to the first node, and the gate terminal of the PMOS transistor is electrically connected to a power source.

In the above dynamic latch, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are inverted.

In the above dynamic latch, the data transmission unit is a transmission gate.

The above dynamic latch, wherein the in-phase data holding unit and/or the inverted data holding unit is an inverter.

Use the utility model discloses a dynamic latch can follow output feedback leakage current to node, and the dynamic leakage current of compensation node improves data storage's stability, and then strengthens the security and the exactness of data.

In order to better achieve the above object, the present invention further provides a data operation unit, which comprises a control circuit, an operation circuit, and a plurality of dynamic latches connected in series and/or in parallel; wherein the plurality of dynamic latches are any one of the dynamic latches described above.

In order to better achieve the above object, the present invention further provides a chip, wherein the chip comprises at least one data operation unit.

To better achieve the above objects, the present invention also provides a computing board for a computing device, wherein at least one chip as described above is included.

In order to better achieve the above object, the utility model also provides a computing device, including power strip, control panel, connecting plate, radiator and a plurality of power strip, the control panel passes through the connecting plate with power strip connects, the radiator sets up around power strip, the power strip be used for to the connecting plate the control panel the radiator and power strip provides the power, wherein, power strip is foretell power strip.

The utility model has the beneficial effects that: the dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

The present invention will be described in detail with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.

Drawings

FIG. 1 is a schematic diagram of a conventional dynamic latch circuit;

fig. 2 is a schematic circuit diagram of a dynamic latch according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a dynamic latch according to yet another embodiment of the present invention;

fig. 6 is a schematic circuit structure diagram of a dynamic latch according to an expanded embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of the data operation unit of the present invention;

fig. 9 is a schematic structural diagram of the chip of the present invention;

fig. 10 is a schematic structural view of the force calculating plate of the present invention;

fig. 11 is a schematic structural diagram of the computing device of the present invention.

Wherein, the reference numbers:

100. 200: dynamic latch

101: transmission gate

102. 103: inverter with a capacitor having a capacitor element

201: data transmission unit

202: first data holding unit

203: second data holding unit

204: leakage compensation unit

201P, 204P: PMOS transistor

201N, 204N: NMOS transistor

800: data arithmetic unit

801: control circuit

802: arithmetic circuit

900: chip and method for manufacturing the same

901: control unit

1000: force calculating board

1100: computing device

1101: connecting plate

1102: control panel

1103: heat radiator

1104: power panel

D: input terminal

Q: in-phase output terminal

QN: inverting output terminal

CKP, CKN: clock signal

S0, S1: node point

Detailed Description

The following describes the structural and operational principles of the present invention in detail with reference to the accompanying drawings:

certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

The first embodiment is as follows:

fig. 2 is a schematic circuit diagram of a dynamic latch according to an embodiment of the present invention. As shown in fig. 2, the dynamic latch 200 includes an input terminal D, a non-inverting output terminal Q, an inverting output terminal QN, a clock signal terminal CKN, a clock signal terminal CKP, a data transmission unit 201, a first data holding unit 202, a second data holding unit 203, and a leakage compensation unit 204. The data transmission unit 201, the first data holding unit 202, and the second data holding unit 203 are sequentially connected in series between the input terminal D and the non-inverting output terminal Q, a first node S0 is formed between the data transmission unit 201 and the first data holding unit 202, a second node S1 is formed between the first data holding unit 202 and the second data holding unit 203, and the inverting output terminal QN is electrically connected to the second node S1. The leakage compensation unit 204 is electrically connected between the first node S0 and the non-inverting output Q. The input end D is used for inputting data, the in-phase output end Q is used for outputting data in-phase, the reverse-phase output end QN is used for outputting data in reverse phase, the clock signal end CKN and the clock signal end CKP are used for providing a clock signal CKN and a clock signal CKP, and the clock signal CKN and the clock signal CKP are reverse-phase clock signals.

Specifically, as shown in fig. 2, the data transmission unit 201 of the dynamic latch 200 is a transmission gate structure, and the data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P and the source terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the input terminal D of the dynamic latch 200, and the drain terminal of the PMOS transistor 201P and the drain terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the first node S0. The gate of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, both the PMOS transistor 201P and the NMOS transistor 201N are turned on, and the data at the input end D of the dynamic latch 200 is transmitted to the first node S0 through the data transmission unit 201. When CKP is high, CKN is low, both PMOS transistor 201P and NMOS transistor 201N are off, and data at input D of dynamic latch 200 cannot be transmitted to first node S0 through data transmission unit 201. In this embodiment, the data transmission unit 201 is exemplified by a transmission gate structure, and of course, other types of data transmission units are also possible as long as the switching function can be realized under the control of the clock signal, and the present invention is not limited thereto.

With continued reference to fig. 2, the first data holding unit 202 and the second data holding unit 203 of the dynamic latch 200 are both inverter structures, and the first data holding unit 202 can temporarily store the data transmitted from the data transmission unit 201, i.e., the data at the first node S0, by using its parasitic capacitance, and can invert the data at the first node S0 and transmit the data to the second data holding unit 203. The second data holding unit 203 also temporarily stores the data transferred from the first data holding unit 202, i.e., the data at the second node S1, using its parasitic capacitance, and also inverts the data at the second node S1 and transfers it to the non-inverting output terminal Q. It can be seen that the data at the first node S0 and the second node S1 are inverse data, and the inverted output QN is electrically connected to the second node S1, so the data outputted by the non-inverted output QN and the inverted output QN are also inverse data.

It can be seen that the data transmission unit 201 is controlled by the clock signal to transmit data to the first data holding unit 202 and the second data holding unit 203, and the data at the input terminal D of the dynamic latch 200 passes through the inverse phase of the first data holding unit 202 and the second data holding unit 203, so that the data at the non-inverting output terminal Q is in phase with the data at the input terminal D, and the data at the inverting output terminal QN is in inverse phase with the data at the input terminal D. Meanwhile, the first data holding unit 202 and the second data holding unit 203 may also function to improve the data driving capability.

As shown in fig. 2, the dynamic latch 200 further includes a leakage compensation unit 204. In the present embodiment, the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N, and the PMOS transistor 204P and the NMOS transistor 204N are connected in series between the non-inverting output terminal Q and the first node S0. The source terminal of the PMOS transistor 204P is electrically connected to the in-phase output terminal Q, the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the first node S0, and the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected together in parallel and electrically connected to the first node S0.

Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are also electrically connected to the first node S0, under the driving of the same level signal, the PMOS transistor 204P and the NMOS transistor 204N are not turned on at the same time, and only one of them is turned on and the other is turned off. For example, when the potential at the first node S0 is high level, the PMOS transistor 204P is in an off state, and the NMOS transistor 204N is in an on state; when the potential at the first node S0 is low, the PMOS transistor 204P is in an on state, and the NMOS transistor 204N is in an off state. At this time, the leakage compensation unit 204 may feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensate the dynamic leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

Example two:

fig. 3 is a schematic circuit diagram of a dynamic latch according to another embodiment of the present invention. As shown in fig. 3, the difference between the embodiment shown in fig. 2 is that in the leakage compensation unit 204 of the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected together in parallel and are electrically connected to the second node S1.

Since the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are also electrically connected to the second node S1, under the driving of the same level signal, the PMOS transistor 204P and the NMOS transistor 204N are not turned on at the same time, and only one of them is turned on and the other is turned off. For example, when the potential at the second node S1 is high level, the PMOS transistor 204P is in an off state, and the NMOS transistor 204N is in an on state; when the potential at the second node S1 is low, the PMOS transistor 204P is in an on state, and the NMOS transistor 204N is in an off state. Therefore, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensate the leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

Modification example:

fig. 4 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and 4, the difference between the embodiments of fig. 2 and fig. 2 is that in the leakage compensation unit 204 of the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected together in parallel and are electrically connected to the ground VSS.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to ground VSS, the PMOS transistor 203P is in the on state and the NMOS transistor 203N is in the off state under the driving of the signal with low level of ground VSS. Therefore, the leakage compensation unit 203 can feed back the current of the input terminal D to the node S0, compensate the leakage current at the node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

Fig. 5 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and fig. 5, the difference between the embodiments shown in fig. 2 is that in the leakage compensation unit 204 of the present embodiment, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected together in parallel and are electrically connected to the power supply VDD.

Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to the power supply VDD, the PMOS transistor 203P is in the off state and the NMOS transistor 203N is in the on state under the driving of the high-level signal of the power supply VDD. Therefore, the leakage compensation unit 203 can feed back the current of the input terminal D to the node S0, compensate the leakage current at the node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

Fig. 6 is a schematic circuit diagram of an embodiment of the dynamic register with leakage compensation according to the present invention. As shown in fig. 6, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes an NMOS transistor 204N, a source terminal of the NMOS transistor 204N is electrically connected to the first node S0, a drain terminal of the NMOS transistor 204N is electrically connected to the in-phase output terminal Q, and a gate terminal of the NMOS transistor 204N is electrically connected to the ground VSS.

Since the gate terminal of the NMOS transistor 204N is electrically connected to ground VSS, the NMOS transistor 204N is in the off state driven by the low level signal of ground VSS. Therefore, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensate the leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

Fig. 7 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 7, the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes a PMOS transistor 204P, a source terminal of the PMOS transistor 204P is electrically connected to the non-inverting output terminal, a drain terminal of the PMOS transistor 204P is electrically connected to the first node S0, and a gate terminal of the PMOS transistor 204P is electrically connected to the power VDD.

Since the gate terminal of the PMOS transistor 204P is electrically connected to the power VDD, the PMOS transistor 204P is turned off when the power VDD is driven by a high-level signal. Therefore, the leakage compensation unit 204 can feed back the leakage current of the non-inverting output terminal Q to the first node S0, compensate the leakage current at the first node S0, improve the stability of data storage at the first node S0, and enhance the correctness and safety of data.

The utility model also provides a data arithmetic unit, figure 8 is the utility model discloses data arithmetic unit's schematic structure diagram. As shown in fig. 8, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of dynamic latches 200. The control circuit 801 refreshes data in the dynamic latch 200 and reads the data from the dynamic latch 200, and the arithmetic circuit 802 performs arithmetic on the read data and outputs the arithmetic result from the control circuit 801.

The utility model also provides a chip, fig. 9 is the utility model discloses the structural schematic of chip. As shown in fig. 9, the chip 900 includes a control unit 901, and one or more data operation units 900. The control unit 901 inputs data to the data operation unit 900 and processes the data output by the data operation unit 900.

The utility model discloses still provide a calculate the power board, fig. 10 is the utility model discloses calculate the structural schematic diagram of power board. As shown in fig. 10, each computing board 1000 includes one or more chips 900 for performing large-scale operations on the working data sent by the computing device.

The utility model also provides a computing equipment, computing equipment is preferred to be used for excavating the operation of virtual digital currency, of course computing equipment also can be used for any other magnanimity operation. Fig. 11 is a schematic structural diagram of the computing device of the present invention. As shown in fig. 11, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power board 1104, and one or more computing boards 1000. The control board 1102 is connected to the force computing board 1000 via a connection board 1101, and a heat sink 1103 is disposed around the force computing board 1000. The power board 1104 is used for supplying power to the connection board 1101, the control board 1102, the heat sink 1103 and the computing power board 1000.

It should be noted that, in the description of the present invention, the terms "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In other words, the present invention may have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims

1. A dynamic latch, comprising:

an input end for inputting a data;

a non-inverting output terminal for outputting the data in an inverting manner;

the inverting output end is used for inverting and outputting the data;

a clock signal terminal for providing a clock signal;

a data transmission unit for transmitting the data under the control of the clock signal;

an in-phase data holding unit for holding the data transmitted by the data transmission unit in phase;

an inverted data holding unit for inverting and holding the data transmitted by the data transmission unit;

the data transmission unit, the in-phase data holding unit and the reverse-phase data holding unit are sequentially connected in series between the input end and the in-phase output end, a first node is arranged between the data transmission unit and the in-phase data holding unit, a second node is arranged between the in-phase data holding unit and the reverse-phase data holding unit, and the reverse-phase output end is electrically connected to the second node;

the power supply further comprises a leakage compensation unit electrically connected between the in-phase output end and the first node.

2. The dynamic latch of claim 1, wherein: the leakage compensation unit has a first end, a second end and a control end, wherein the first end is electrically connected to the in-phase output end, and the second end is electrically connected to the first node.

3. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises a PMOS transistor and an NMOS transistor which are connected in series between the in-phase output end and the first node.

4. The dynamic latch of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the in-phase output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the first node.

5. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the first node.

6. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the second node.

7. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the ground.

8. The dynamic latch of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to a power supply.

9. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises an NMOS transistor, wherein the NMOS transistor is provided with a source end, a drain end and a grid end, the drain end of the NMOS transistor is electrically connected to the in-phase output end, the source end is electrically connected to the first node, and the grid end is electrically connected to the ground.

10. The dynamic latch of claim 2, wherein: the leakage compensation unit comprises a PMOS transistor, wherein the PMOS transistor is provided with a source end, a drain end and a grid end, the source end of the PMOS transistor is electrically connected to the in-phase output end, the drain end of the PMOS transistor is electrically connected to the first node, and the grid end of the PMOS transistor is electrically connected to a power supply.

11. The dynamic latch of claim 1, wherein: the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

12. The dynamic latch of claim 1, wherein: the data transmission unit is a transmission gate.

13. The dynamic latch of claim 1, wherein: the in-phase data holding unit and/or the inverted data holding unit are inverters.

14. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of dynamic latches which are connected in an interconnecting way, wherein the plurality of dynamic latches are connected in series and/or in parallel; the method is characterized in that: the plurality of dynamic latches are as claimed in any one of claims 1 to 13.

15. A chip comprising at least one data arithmetic unit as claimed in claim 14.

16. An computing force board for a computing device comprising at least one chip as recited in claim 15.

17. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force computing board is as claimed in claim 16.