TW369700B - Intrachip power distribution package and method for semiconductors - Google Patents
Intrachip power distribution package and method for semiconductorsInfo
- Publication number
- TW369700B TW369700B TW087102634A TW87102634A TW369700B TW 369700 B TW369700 B TW 369700B TW 087102634 A TW087102634 A TW 087102634A TW 87102634 A TW87102634 A TW 87102634A TW 369700 B TW369700 B TW 369700B
- Authority
- TW
- Taiwan
- Prior art keywords
- power
- intermediate node
- node
- supply
- intrachip
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/805,391 US5838072A (en) | 1997-02-24 | 1997-02-24 | Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes |
Publications (1)
Publication Number | Publication Date |
---|---|
TW369700B true TW369700B (en) | 1999-09-11 |
Family
ID=25191441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087102634A TW369700B (en) | 1997-02-24 | 1998-02-24 | Intrachip power distribution package and method for semiconductors |
Country Status (2)
Country | Link |
---|---|
US (1) | US5838072A (zh) |
TW (1) | TW369700B (zh) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1092857A (ja) * | 1996-09-10 | 1998-04-10 | Mitsubishi Electric Corp | 半導体パッケージ |
US6097098A (en) * | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
FR2769131B1 (fr) * | 1997-09-29 | 1999-12-24 | St Microelectronics Sa | Dispositif semi-conducteur a deux plots de connexion de masse relies a une patte de connexion de masse et procede pour tester un tel dispositif |
US6351040B1 (en) | 1998-01-22 | 2002-02-26 | Micron Technology, Inc. | Method and apparatus for implementing selected functionality on an integrated circuit device |
US6169331B1 (en) | 1998-08-28 | 2001-01-02 | Micron Technology, Inc. | Apparatus for electrically coupling bond pads of a microelectronic device |
JP2001024150A (ja) * | 1999-07-06 | 2001-01-26 | Sony Corp | 半導体装置 |
US6392428B1 (en) * | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
US6483043B1 (en) | 2000-05-19 | 2002-11-19 | Eaglestone Partners I, Llc | Chip assembly with integrated power distribution between a wafer interposer and an integrated circuit chip |
US6529081B1 (en) | 2000-06-08 | 2003-03-04 | Zeta, Division Of Sierra Tech Inc. | Method of operating a solid state power amplifying device |
WO2002005342A1 (en) * | 2000-07-06 | 2002-01-17 | Zeta, A Division Of Sierratech, Inc. | A solid state power amplifying device |
US6812048B1 (en) | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6537831B1 (en) * | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
US6538337B2 (en) * | 2000-08-17 | 2003-03-25 | Samsung Electronics Co., Ltd. | Ball grid array package for providing constant internal voltage via a PCB substrate routing configuration |
US6815712B1 (en) | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US6686657B1 (en) | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
US20020078401A1 (en) * | 2000-12-15 | 2002-06-20 | Fry Michael Andrew | Test coverage analysis system |
US6529022B2 (en) | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US20020076854A1 (en) * | 2000-12-15 | 2002-06-20 | Pierce John L. | System, method and apparatus for constructing a semiconductor wafer-interposer using B-Stage laminates |
US6673653B2 (en) * | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
US6608390B2 (en) | 2001-11-13 | 2003-08-19 | Kulicke & Soffa Investments, Inc. | Wirebonded semiconductor package structure and method of manufacture |
US8258616B1 (en) | 2002-01-16 | 2012-09-04 | Marvell International Ltd. | Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads |
US6770982B1 (en) | 2002-01-16 | 2004-08-03 | Marvell International, Ltd. | Semiconductor device power distribution system and method |
US6861762B1 (en) | 2002-05-01 | 2005-03-01 | Marvell Semiconductor Israel Ltd. | Flip chip with novel power and ground arrangement |
TW582100B (en) * | 2002-05-30 | 2004-04-01 | Fujitsu Ltd | Semiconductor device having a heat spreader exposed from a seal resin |
US7326594B2 (en) * | 2002-07-31 | 2008-02-05 | Microchip Technology Incorporated | Connecting a plurality of bond pads and/or inner leads with a single bond wire |
US7157790B2 (en) * | 2002-07-31 | 2007-01-02 | Microchip Technology Inc. | Single die stitch bonding |
US20050230850A1 (en) * | 2004-04-20 | 2005-10-20 | Taggart Brian C | Microelectronic assembly having a redistribution conductor over a microelectronic die |
US7737553B2 (en) * | 2004-10-06 | 2010-06-15 | Panasonic Corporation | Semiconductor device |
JP2010087403A (ja) * | 2008-10-02 | 2010-04-15 | Elpida Memory Inc | 半導体装置 |
JP2010192680A (ja) * | 2009-02-18 | 2010-09-02 | Elpida Memory Inc | 半導体装置 |
US8448118B2 (en) | 2011-02-22 | 2013-05-21 | International Business Machines Corporation | Determining intra-die wirebond pad placement locations in integrated circuit |
US9196598B1 (en) | 2014-06-12 | 2015-11-24 | Freescale Semiconductor, Inc. | Semiconductor device having power distribution using bond wires |
US10217717B2 (en) * | 2015-11-18 | 2019-02-26 | Stmicroelectronics (Rousset) Sas | Distribution of electronic circuit power supply potentials |
US9721928B1 (en) | 2016-04-28 | 2017-08-01 | Nxp Usa, Inc. | Integrated circuit package having two substrates |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5276352A (en) * | 1990-11-15 | 1994-01-04 | Kabushiki Kaisha Toshiba | Resin sealed semiconductor device having power source by-pass connecting line |
US5172471A (en) * | 1991-06-21 | 1992-12-22 | Vlsi Technology, Inc. | Method of providing power to an integrated circuit |
KR940006187Y1 (ko) * | 1991-10-15 | 1994-09-10 | 금성일렉트론 주식회사 | 반도체장치 |
US5170312A (en) * | 1991-11-04 | 1992-12-08 | Motorola, Inc. | Protection circuit on a lead of a power device |
FR2701153B1 (fr) * | 1993-02-02 | 1995-04-07 | Matra Marconi Space France | Composant et module de mémoire à semi-conducteur. |
JPH07130788A (ja) * | 1993-09-09 | 1995-05-19 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
US5723906A (en) * | 1996-06-07 | 1998-03-03 | Hewlett-Packard Company | High-density wirebond chip interconnect for multi-chip modules |
-
1997
- 1997-02-24 US US08/805,391 patent/US5838072A/en not_active Expired - Lifetime
-
1998
- 1998-02-24 TW TW087102634A patent/TW369700B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5838072A (en) | 1998-11-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |