TW367622B - Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor - Google Patents

Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor

Info

Publication number
TW367622B
TW367622B TW085104944A TW85104944A TW367622B TW 367622 B TW367622 B TW 367622B TW 085104944 A TW085104944 A TW 085104944A TW 85104944 A TW85104944 A TW 85104944A TW 367622 B TW367622 B TW 367622B
Authority
TW
Taiwan
Prior art keywords
thin film
film transistor
polycrystalline silicon
manufacturing
low temperature
Prior art date
Application number
TW085104944A
Other languages
Chinese (zh)
Inventor
Kang-Cheng Lin
Li-Ting Chen
Original Assignee
Ind Tech Res Inst
Au Optronics Corp
Quanta Display Inc
Hannstar Display Corp
Chunghwa Picture Tubes Ltd
Chi Mei Optoelectronics Corp
Toppoly Optoelectronics Corp
Prime View Int Corp Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst, Au Optronics Corp, Quanta Display Inc, Hannstar Display Corp, Chunghwa Picture Tubes Ltd, Chi Mei Optoelectronics Corp, Toppoly Optoelectronics Corp, Prime View Int Corp Ltd filed Critical Ind Tech Res Inst
Priority to TW085104944A priority Critical patent/TW367622B/en
Application granted granted Critical
Publication of TW367622B publication Critical patent/TW367622B/en

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  • Thin Film Transistor (AREA)

Abstract

A kind of manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor which employs the laser from the back of transparent substrate to irradiate the a-Si layer in the front of transparent substrate to make it become polycrystalline silicon and activate the crud doped in source and drain of thin film transistor and save the energy and simplify the processes of coplanar thin film transistor. The temperature of all the processes should be below 400 degree C and with only once laser quenching so that the a-Si can be converted to polycrystalline silicon. The method can be used for self-aligned thin film transistor and the light doped source/drain and source/drain offset thin film transistor.
TW085104944A 1996-04-25 1996-04-25 Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor TW367622B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW085104944A TW367622B (en) 1996-04-25 1996-04-25 Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085104944A TW367622B (en) 1996-04-25 1996-04-25 Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor

Publications (1)

Publication Number Publication Date
TW367622B true TW367622B (en) 1999-08-21

Family

ID=57941272

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085104944A TW367622B (en) 1996-04-25 1996-04-25 Manufacturing method and structure for low temperature polycrystalline silicon coplanar thin film transistor

Country Status (1)

Country Link
TW (1) TW367622B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892919B1 (en) 2019-11-29 2021-01-12 Industrial Technology Research Institute Detector and interference cancellation method for spatial multiplexing filter bank multicarrier with offset quadrature amplitude modulation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892919B1 (en) 2019-11-29 2021-01-12 Industrial Technology Research Institute Detector and interference cancellation method for spatial multiplexing filter bank multicarrier with offset quadrature amplitude modulation

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