TW364118B - Parallel output buffers in memory circuit - Google Patents

Parallel output buffers in memory circuit

Info

Publication number
TW364118B
TW364118B TW086102311A TW86102311A TW364118B TW 364118 B TW364118 B TW 364118B TW 086102311 A TW086102311 A TW 086102311A TW 86102311 A TW86102311 A TW 86102311A TW 364118 B TW364118 B TW 364118B
Authority
TW
Taiwan
Prior art keywords
output buffers
memory circuit
output
parallel output
buffers
Prior art date
Application number
TW086102311A
Other languages
English (en)
Inventor
Robert J Proebsting
Original Assignee
Townsend & Townsend & Crew Llp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Townsend & Townsend & Crew Llp filed Critical Townsend & Townsend & Crew Llp
Application granted granted Critical
Publication of TW364118B publication Critical patent/TW364118B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Memories (AREA)
TW086102311A 1995-12-22 1997-02-24 Parallel output buffers in memory circuit TW364118B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/577,525 US5689462A (en) 1995-12-22 1995-12-22 Parallel output buffers in memory circuits

Publications (1)

Publication Number Publication Date
TW364118B true TW364118B (en) 1999-07-11

Family

ID=24309108

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086102311A TW364118B (en) 1995-12-22 1997-02-24 Parallel output buffers in memory circuit

Country Status (6)

Country Link
US (1) US5689462A (zh)
EP (1) EP0785556A3 (zh)
JP (1) JP2951278B2 (zh)
KR (1) KR100253853B1 (zh)
CN (1) CN1156884A (zh)
TW (1) TW364118B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624658B2 (en) * 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US6034547A (en) * 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
KR100264076B1 (ko) * 1997-06-20 2000-08-16 김영환 데이타 출력 드라이버 전류를 증가시킨 디램
US5896337A (en) 1998-02-23 1999-04-20 Micron Technology, Inc. Circuits and methods for multi-level data through a single input/ouput pin
US6366131B1 (en) * 2000-05-01 2002-04-02 Hewlett-Packard Company System and method for increasing a drive signal and decreasing a pin count
US6871257B2 (en) * 2002-02-22 2005-03-22 Sandisk Corporation Pipelined parallel programming operation in a non-volatile memory system
US20070191487A1 (en) * 2004-03-17 2007-08-16 Rigassi-Dietrich Petra G Galenic formulations of organic compounds
JP2005340227A (ja) * 2004-05-24 2005-12-08 Hitachi Ltd 半導体記憶装置と半導体装置
US20060129712A1 (en) * 2004-12-10 2006-06-15 Siva Raghuram Buffer chip for a multi-rank dual inline memory module (DIMM)
KR100792431B1 (ko) 2006-08-31 2008-01-10 주식회사 하이닉스반도체 반도체 메모리 장치
JP5599560B2 (ja) * 2008-11-27 2014-10-01 富士通セミコンダクター株式会社 半導体メモリ
CN101489124B (zh) * 2008-12-31 2011-04-27 深圳裕达富电子有限公司 一种同步动态存储器的使用方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH079976B2 (ja) * 1985-04-10 1995-02-01 日本電気株式会社 半導体メモリ
JPH0697560B2 (ja) * 1987-11-19 1994-11-30 三菱電機株式会社 半導体記憶装置
US5027326A (en) * 1988-11-10 1991-06-25 Dallas Semiconductor Corporation Self-timed sequential access multiport memory
JPH0344890A (ja) * 1989-07-12 1991-02-26 Toshiba Corp 半導体記憶装置のデータ出力制御回路
US5262990A (en) * 1991-07-12 1993-11-16 Intel Corporation Memory device having selectable number of output pins
JP2748053B2 (ja) * 1991-07-23 1998-05-06 三菱電機株式会社 半導体記憶装置
US5353250A (en) * 1991-12-09 1994-10-04 Texas Instruments Inc. Pin programmable dram that provides customer option programmability
JPH05250872A (ja) * 1992-03-09 1993-09-28 Oki Electric Ind Co Ltd ランダム・アクセス・メモリ
JP2819951B2 (ja) * 1992-07-28 1998-11-05 日本電気株式会社 半導体記憶装置
GB2282721B (en) * 1993-09-30 1997-08-20 Advanced Risc Mach Ltd Output signal driver

Also Published As

Publication number Publication date
KR100253853B1 (ko) 2000-04-15
JP2951278B2 (ja) 1999-09-20
EP0785556A2 (en) 1997-07-23
CN1156884A (zh) 1997-08-13
JPH09293375A (ja) 1997-11-11
KR970051297A (ko) 1997-07-29
EP0785556A3 (en) 1998-07-01
US5689462A (en) 1997-11-18

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