TW364097B - SIMD correction circuit for arithmetic/shift operations - Google Patents

SIMD correction circuit for arithmetic/shift operations

Info

Publication number
TW364097B
TW364097B TW086113822A TW86113822A TW364097B TW 364097 B TW364097 B TW 364097B TW 086113822 A TW086113822 A TW 086113822A TW 86113822 A TW86113822 A TW 86113822A TW 364097 B TW364097 B TW 364097B
Authority
TW
Taiwan
Prior art keywords
arithmetic
instructions
correction circuit
shift
simd
Prior art date
Application number
TW086113822A
Other languages
English (en)
Inventor
Robert Michael Dinkjian
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW364097B publication Critical patent/TW364097B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
TW086113822A 1996-12-20 1997-09-23 SIMD correction circuit for arithmetic/shift operations TW364097B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/770,349 US6006316A (en) 1996-12-20 1996-12-20 Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction

Publications (1)

Publication Number Publication Date
TW364097B true TW364097B (en) 1999-07-11

Family

ID=25088262

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113822A TW364097B (en) 1996-12-20 1997-09-23 SIMD correction circuit for arithmetic/shift operations

Country Status (5)

Country Link
US (1) US6006316A (zh)
KR (1) KR19980063501A (zh)
CN (1) CN1108558C (zh)
GB (1) GB2321547B (zh)
TW (1) TW364097B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US7197625B1 (en) * 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US5864703A (en) 1997-10-09 1999-01-26 Mips Technologies, Inc. Method for providing extended precision in SIMD vector arithmetic operations
US6211892B1 (en) * 1998-03-31 2001-04-03 Intel Corporation System and method for performing an intra-add operation
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
GB2343969A (en) 1998-11-20 2000-05-24 Advanced Risc Mach Ltd A data processing apparatus and method for performing an arithemtic operation on a plurality of signed data values
GB2362732B (en) * 2000-05-23 2004-08-04 Advanced Risc Mach Ltd Parallel processing of multiple data values within a data word
US7711763B2 (en) 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US7162621B2 (en) 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US7181484B2 (en) 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
JP3779602B2 (ja) * 2001-11-28 2006-05-31 松下電器産業株式会社 Ｓｉｍｄ演算方法およびｓｉｍｄ演算装置
US7565514B2 (en) * 2006-04-28 2009-07-21 Freescale Semiconductor, Inc. Parallel condition code generation for SIMD operations
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations
WO2013095513A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Packed data operation mask shift processors, methods, systems, and instructions
CN103377031B (zh) * 2012-04-27 2017-09-26 腾讯科技（深圳）有限公司 一种多数据处理方法和装置
US10915319B2 (en) 2017-05-15 2021-02-09 Google Llc Two dimensional masked shift instruction

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139899A (en) * 1976-10-18 1979-02-13 Burroughs Corporation Shift network having a mask generator and a rotator
US5418915A (en) * 1990-08-08 1995-05-23 Sumitomo Metal Industries, Ltd. Arithmetic unit for SIMD type parallel computer
US5276634A (en) * 1990-08-24 1994-01-04 Matsushita Electric Industrial Co., Ltd. Floating point data processing apparatus which simultaneously effects summation and rounding computations
US5408670A (en) * 1992-12-18 1995-04-18 Xerox Corporation Performing arithmetic in parallel on composite operands with packed multi-bit components
US5689592A (en) * 1993-12-22 1997-11-18 Vivo Software, Inc. Parallel processing of digital signals in a single arithmetic/logic unit
EP0661624A1 (en) * 1994-01-04 1995-07-05 Sun Microsystems, Inc. Pseudo-superscalar technique for video processing
ZA9510127B (en) * 1994-12-01 1996-06-06 Intel Corp Novel processor having shift operations

Also Published As

Publication number Publication date
US6006316A (en) 1999-12-21
GB9724532D0 (en) 1998-01-21
CN1185606A (zh) 1998-06-24
KR19980063501A (ko) 1998-10-07
GB2321547A (en) 1998-07-29
GB2321547B (en) 2001-10-24
CN1108558C (zh) 2003-05-14

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