TW362194B - Method and apparatus for decreasing thread switch latency in a multithread processor - Google Patents

Method and apparatus for decreasing thread switch latency in a multithread processor

Info

Publication number
TW362194B
TW362194B TW086117440A TW86117440A TW362194B TW 362194 B TW362194 B TW 362194B TW 086117440 A TW086117440 A TW 086117440A TW 86117440 A TW86117440 A TW 86117440A TW 362194 B TW362194 B TW 362194B
Authority
TW
Taiwan
Prior art keywords
thread
instruction queue
instructions
multithread processor
thread switch
Prior art date
Application number
TW086117440A
Other languages
English (en)
Inventor
William Thomas Flynn
Philip Rogers Hiller Iii
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW362194B publication Critical patent/TW362194B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW086117440A 1997-03-28 1997-11-21 Method and apparatus for decreasing thread switch latency in a multithread processor TW362194B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/829,518 US5907702A (en) 1997-03-28 1997-03-28 Method and apparatus for decreasing thread switch latency in a multithread processor

Publications (1)

Publication Number Publication Date
TW362194B true TW362194B (en) 1999-06-21

Family

ID=25254763

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086117440A TW362194B (en) 1997-03-28 1997-11-21 Method and apparatus for decreasing thread switch latency in a multithread processor

Country Status (8)

Country Link
US (1) US5907702A (zh)
JP (1) JP3573943B2 (zh)
KR (1) KR100274268B1 (zh)
CN (1) CN1092360C (zh)
GB (1) GB2324392B (zh)
HK (1) HK1011567A1 (zh)
SG (1) SG63818A1 (zh)
TW (1) TW362194B (zh)

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US7234139B1 (en) * 2000-11-24 2007-06-19 Catharon Productions, Inc. Computer multi-tasking via virtual threading using an interpreter
US8762581B2 (en) * 2000-12-22 2014-06-24 Avaya Inc. Multi-thread packet processor
US7149880B2 (en) * 2000-12-29 2006-12-12 Intel Corporation Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor
US7320065B2 (en) 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US6965982B2 (en) * 2001-06-29 2005-11-15 International Business Machines Corporation Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread
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US7275247B2 (en) * 2002-09-19 2007-09-25 International Business Machines Corporation Method and apparatus for handling threads in a data processing system
US7062606B2 (en) * 2002-11-01 2006-06-13 Infineon Technologies Ag Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
US7076616B2 (en) * 2003-03-24 2006-07-11 Sony Corporation Application pre-launch to reduce user interface latency
US7496915B2 (en) * 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US20040226011A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Multi-threaded microprocessor with queue flushing
US7653904B2 (en) * 2003-09-26 2010-01-26 Intel Corporation System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected
US8140829B2 (en) * 2003-11-20 2012-03-20 International Business Machines Corporation Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution
US7430737B2 (en) * 2003-12-04 2008-09-30 Sun Microsystems, Inc. Processor and method for supporting compiler directed multithreading management
US7441101B1 (en) * 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
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US7617499B2 (en) * 2003-12-18 2009-11-10 International Business Machines Corporation Context switch instruction prefetching in multithreaded computer
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US7206922B1 (en) 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US8074051B2 (en) * 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US20050246461A1 (en) * 2004-04-29 2005-11-03 International Business Machines Corporation Scheduling threads in a multi-processor computer
US20050270297A1 (en) * 2004-06-08 2005-12-08 Sony Corporation And Sony Electronics Inc. Time sliced architecture for graphics display system
ATE550720T1 (de) * 2004-08-03 2012-04-15 Nxp Bv System, controller und verfahren zur steuerung der kommunikation zwischen einem prozessor und einer externen peripherievorrichtung
US7487503B2 (en) 2004-08-12 2009-02-03 International Business Machines Corporation Scheduling threads in a multiprocessor computer
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Also Published As

Publication number Publication date
CN1195135A (zh) 1998-10-07
GB2324392A (en) 1998-10-21
GB9803618D0 (en) 1998-04-15
SG63818A1 (en) 1999-03-30
HK1011567A1 (en) 1999-07-16
KR100274268B1 (ko) 2000-12-15
JPH10283203A (ja) 1998-10-23
CN1092360C (zh) 2002-10-09
GB2324392B (en) 2001-09-05
JP3573943B2 (ja) 2004-10-06
KR19980079506A (ko) 1998-11-25
US5907702A (en) 1999-05-25

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