AU2001285072A1 - Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously - Google Patents
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneouslyInfo
- Publication number
- AU2001285072A1 AU2001285072A1 AU2001285072A AU8507201A AU2001285072A1 AU 2001285072 A1 AU2001285072 A1 AU 2001285072A1 AU 2001285072 A AU2001285072 A AU 2001285072A AU 8507201 A AU8507201 A AU 8507201A AU 2001285072 A1 AU2001285072 A1 AU 2001285072A1
- Authority
- AU
- Australia
- Prior art keywords
- dsp
- instruction
- instructions
- sub
- shadow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title abstract 2
- 230000003111 delayed effect Effects 0.000 abstract 2
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
- G06F9/381—Loop buffering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Physics (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Computing Systems (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09652100 | 2000-08-30 | ||
US09/652,100 US6408376B1 (en) | 1999-10-25 | 2000-08-30 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
PCT/US2001/025905 WO2002019099A1 (en) | 2000-08-30 | 2001-08-16 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001285072A1 true AU2001285072A1 (en) | 2002-03-13 |
Family
ID=24615512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001285072A Abandoned AU2001285072A1 (en) | 2000-08-30 | 2001-08-16 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
Country Status (7)
Country | Link |
---|---|
US (2) | US6408376B1 (en) |
EP (1) | EP1323030B1 (en) |
CN (1) | CN1251063C (en) |
AT (1) | ATE461480T1 (en) |
AU (1) | AU2001285072A1 (en) |
DE (1) | DE60141591D1 (en) |
WO (1) | WO2002019099A1 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US7010579B1 (en) * | 2000-09-26 | 2006-03-07 | Cisco Technology, Inc. | Direct data routing system |
GB2382673B (en) * | 2001-10-31 | 2005-10-26 | Alphamosaic Ltd | A vector processing system |
US7681046B1 (en) | 2003-09-26 | 2010-03-16 | Andrew Morgan | System with secure cryptographic capabilities using a hardware specific digital secret |
US7694151B1 (en) | 2003-11-20 | 2010-04-06 | Johnson Richard C | Architecture, system, and method for operating on encrypted and/or hidden information |
US7496727B1 (en) | 2005-12-06 | 2009-02-24 | Transmeta Corporation | Secure memory access system and method |
US8565519B2 (en) * | 2007-02-09 | 2013-10-22 | Qualcomm Incorporated | Programmable pattern-based unpacking and packing of data channel information |
US8327120B2 (en) | 2007-12-29 | 2012-12-04 | Intel Corporation | Instructions with floating point control override |
US20100115239A1 (en) * | 2008-10-29 | 2010-05-06 | Adapteva Incorporated | Variable instruction width digital signal processor |
US20130262827A1 (en) * | 2012-03-27 | 2013-10-03 | Resilient Science, Inc. | Apparatus and method using hybrid length instruction word |
US9619229B2 (en) * | 2012-12-27 | 2017-04-11 | Intel Corporation | Collapsing of multiple nested loops, methods and instructions |
US9785435B1 (en) * | 2016-10-27 | 2017-10-10 | International Business Machines Corporation | Floating point instruction with selectable comparison attributes |
KR102295677B1 (en) * | 2018-05-18 | 2021-08-30 | 주식회사 모르미 | Parallel processing apparatus capable of consecutive parallelism |
Family Cites Families (28)
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US5142677A (en) | 1989-05-04 | 1992-08-25 | Texas Instruments Incorporated | Context switching devices, systems and methods |
US4969118A (en) | 1989-01-13 | 1990-11-06 | International Business Machines Corporation | Floating point unit for calculating A=XY+Z having simultaneous multiply and add |
EP0466997A1 (en) * | 1990-07-18 | 1992-01-22 | International Business Machines Corporation | Improved digital signal processor architecture |
US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
US5341374A (en) | 1991-03-01 | 1994-08-23 | Trilan Systems Corporation | Communication network integrating voice data and video with distributed call processing |
US5241492A (en) | 1991-05-06 | 1993-08-31 | Motorola, Inc. | Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor |
JPH06150023A (en) | 1992-11-06 | 1994-05-31 | Hitachi Ltd | Microcomputer and system thereof |
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US6154828A (en) | 1993-06-03 | 2000-11-28 | Compaq Computer Corporation | Method and apparatus for employing a cycle bit parallel executing instructions |
JP3532975B2 (en) | 1993-09-27 | 2004-05-31 | 株式会社ルネサステクノロジ | Microcomputer and method of executing instructions using the same |
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JP3579843B2 (en) * | 1994-10-24 | 2004-10-20 | 日本テキサス・インスツルメンツ株式会社 | Digital signal processor |
US5530663A (en) | 1994-11-14 | 1996-06-25 | International Business Machines Corporation | Floating point unit for calculating a compound instruction A+B×C in two cycles |
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JP2931890B2 (en) | 1995-07-12 | 1999-08-09 | 三菱電機株式会社 | Data processing device |
JP3767930B2 (en) | 1995-11-13 | 2006-04-19 | 沖電気工業株式会社 | Information recording / reproducing method and information storage device |
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-
2000
- 2000-08-30 US US09/652,100 patent/US6408376B1/en not_active Expired - Fee Related
-
2001
- 2001-08-16 CN CN01818138.4A patent/CN1251063C/en not_active Expired - Fee Related
- 2001-08-16 WO PCT/US2001/025905 patent/WO2002019099A1/en active Application Filing
- 2001-08-16 AT AT01964189T patent/ATE461480T1/en not_active IP Right Cessation
- 2001-08-16 EP EP01964189A patent/EP1323030B1/en not_active Expired - Lifetime
- 2001-08-16 DE DE60141591T patent/DE60141591D1/en not_active Expired - Lifetime
- 2001-08-16 AU AU2001285072A patent/AU2001285072A1/en not_active Abandoned
-
2002
- 2002-01-29 US US10/059,698 patent/US6748516B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1323030A1 (en) | 2003-07-02 |
US20020188824A1 (en) | 2002-12-12 |
CN1471666A (en) | 2004-01-28 |
US6408376B1 (en) | 2002-06-18 |
EP1323030A4 (en) | 2006-04-19 |
US6748516B2 (en) | 2004-06-08 |
CN1251063C (en) | 2006-04-12 |
ATE461480T1 (en) | 2010-04-15 |
EP1323030B1 (en) | 2010-03-17 |
DE60141591D1 (en) | 2010-04-29 |
WO2002019099A1 (en) | 2002-03-07 |
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