TW360852B - Pipeline processor - Google Patents
Pipeline processorInfo
- Publication number
- TW360852B TW360852B TW085104015A TW85104015A TW360852B TW 360852 B TW360852 B TW 360852B TW 085104015 A TW085104015 A TW 085104015A TW 85104015 A TW85104015 A TW 85104015A TW 360852 B TW360852 B TW 360852B
- Authority
- TW
- Taiwan
- Prior art keywords
- instruction
- address
- counter
- branch
- predictive
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8684495 | 1995-04-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW360852B true TW360852B (en) | 1999-06-11 |
Family
ID=13898127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085104015A TW360852B (en) | 1995-04-12 | 1996-04-06 | Pipeline processor |
Country Status (3)
Country | Link |
---|---|
US (1) | US5724563A (zh) |
KR (1) | KR100233220B1 (zh) |
TW (1) | TW360852B (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6170053B1 (en) * | 1996-06-27 | 2001-01-02 | Texas Instruments Incorporated | Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy |
JPH1185515A (ja) * | 1997-09-10 | 1999-03-30 | Ricoh Co Ltd | マイクロプロセッサ |
US6016555A (en) * | 1997-11-19 | 2000-01-18 | Texas Instruments Incorporated | Non-intrusive software breakpoints in a processor instruction execution pipeline |
US6334184B1 (en) * | 1998-03-24 | 2001-12-25 | International Business Machines Corporation | Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request |
WO2001016702A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US7681018B2 (en) | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US7178138B2 (en) * | 2001-01-24 | 2007-02-13 | Texas Instruments Incorporated | Method and tool for verification of algorithms ported from one instruction set architecture to another |
ATE432499T1 (de) * | 2001-06-29 | 2009-06-15 | Texas Instruments Inc | Verfahren zur verbesserung der sichtbarkeit von berechnung der effektiven adressen in pipelinearchitektur |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US7225281B2 (en) * | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US7487505B2 (en) * | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7610451B2 (en) * | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
US7337275B2 (en) * | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
US7634640B2 (en) * | 2002-08-30 | 2009-12-15 | Infineon Technologies Ag | Data processing apparatus having program counter sensor |
JP2004206389A (ja) * | 2002-12-25 | 2004-07-22 | Denso Corp | Risc型cpu,コンパイラ,マイクロコンピュータ及び補助演算装置 |
US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
US7454585B2 (en) * | 2005-12-22 | 2008-11-18 | International Business Machines Corporation | Efficient and flexible memory copy operation |
US8966228B2 (en) * | 2009-03-20 | 2015-02-24 | Arm Limited | Instruction fetching following changes in program flow |
JP2011209905A (ja) * | 2010-03-29 | 2011-10-20 | Sony Corp | 命令フェッチ装置、プロセッサ、および、プログラムカウンタ加算制御方法 |
US9535701B2 (en) | 2014-01-29 | 2017-01-03 | Telefonaktiebolaget Lm Ericsson (Publ) | Efficient use of branch delay slots and branch prediction in pipelined computer architectures |
US9430245B2 (en) | 2014-03-28 | 2016-08-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Efficient branch predictor history recovery in pipelined computer architectures employing branch prediction and branch delay slots of variable size |
GB2548604B (en) * | 2016-03-23 | 2018-03-21 | Advanced Risc Mach Ltd | Branch instruction |
US10936318B2 (en) * | 2018-11-14 | 2021-03-02 | International Business Machines Corporation | Tagged indirect branch predictor (TIP) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05108345A (ja) * | 1991-10-16 | 1993-04-30 | Nec Corp | 分岐命令処理装置 |
-
1996
- 1996-04-06 TW TW085104015A patent/TW360852B/zh active
- 1996-04-08 US US08/629,216 patent/US5724563A/en not_active Expired - Lifetime
- 1996-04-12 KR KR1019960010897A patent/KR100233220B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960038602A (ko) | 1996-11-21 |
KR100233220B1 (ko) | 1999-12-01 |
US5724563A (en) | 1998-03-03 |
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