TW347556B - System and method for generating mask layouts - Google Patents

System and method for generating mask layouts

Info

Publication number
TW347556B
TW347556B TW086102595A TW86102595A TW347556B TW 347556 B TW347556 B TW 347556B TW 086102595 A TW086102595 A TW 086102595A TW 86102595 A TW86102595 A TW 86102595A TW 347556 B TW347556 B TW 347556B
Authority
TW
Taiwan
Prior art keywords
mask layout
input data
generating
generating mask
mask layouts
Prior art date
Application number
TW086102595A
Other languages
English (en)
Inventor
Philip Fishburn John
Robert Kemp Craig
Anne Schevon Gatherine
R Seigfried Todd
Taneja Sanjiv
Original Assignee
At&T Ipm Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At&T Ipm Corp filed Critical At&T Ipm Corp
Application granted granted Critical
Publication of TW347556B publication Critical patent/TW347556B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
TW086102595A 1995-05-01 1997-03-04 System and method for generating mask layouts TW347556B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/431,585 US5633807A (en) 1995-05-01 1995-05-01 System and method for generating mask layouts

Publications (1)

Publication Number Publication Date
TW347556B true TW347556B (en) 1998-12-11

Family

ID=23712583

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086102595A TW347556B (en) 1995-05-01 1997-03-04 System and method for generating mask layouts

Country Status (6)

Country Link
US (1) US5633807A (zh)
EP (1) EP0741365A1 (zh)
JP (1) JPH08305001A (zh)
KR (1) KR960042917A (zh)
SG (1) SG43363A1 (zh)
TW (1) TW347556B (zh)

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US5923569A (en) * 1995-10-17 1999-07-13 Matsushita Electric Industrial Co., Ltd. Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof
KR100439562B1 (ko) * 1996-03-07 2005-10-19 마츠시타 덴끼 산교 가부시키가이샤 트랜지스터 배치 방법
JP2798055B2 (ja) * 1996-05-30 1998-09-17 日本電気株式会社 半導体集積回路のレイアウト方法
JP3346982B2 (ja) * 1996-06-13 2002-11-18 株式会社東芝 集積回路のレイアウト生成装置及びその方法
US5984510A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts
US6086630A (en) * 1996-12-23 2000-07-11 Nortel Networks Corporation Automated PCB checklist
JP3042443B2 (ja) * 1997-03-14 2000-05-15 日本電気株式会社 マスクパターンデータの作成方法
WO1998055950A1 (en) * 1997-06-06 1998-12-10 Chapman David C Integrated circuit layout synthesis tool
US5845233A (en) * 1997-07-30 1998-12-01 Lucent Technologies, Inc. Method and apparatus for calibrating static timing analyzer to path delay measurements
US6077308A (en) * 1997-08-21 2000-06-20 Micron Technology, Inc. Creating layout for integrated circuit structures
US6208907B1 (en) * 1998-01-30 2001-03-27 International Business Machines Corporation Domino to static circuit technique
JP3070679B2 (ja) * 1998-03-24 2000-07-31 日本電気株式会社 図形レイアウト圧縮システム及び図形レイアウト圧縮方法
US6269277B1 (en) * 1998-07-27 2001-07-31 The Leland Stanford Junior University Board Of Trustees System and method for designing integrated circuits
US6691297B1 (en) 1999-03-04 2004-02-10 Matsushita Electric Industrial Co., Ltd. Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
DE10025583A1 (de) * 2000-05-24 2001-12-06 Infineon Technologies Ag Verfahren zur Optimierung integrierter Schaltungen, Vorrichtung zum Entwurf von Halbleitern und Programmobjekt zum Entwerfen integrierter Schaltungen
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
GB0104945D0 (en) * 2001-02-28 2001-04-18 3Com Corp Automatic generation of interconnect logic components
US6574779B2 (en) 2001-04-12 2003-06-03 International Business Machines Corporation Hierarchical layout method for integrated circuits
US7065727B2 (en) * 2001-04-25 2006-06-20 Barcelona Design, Inc. Optimal simultaneous design and floorplanning of integrated circuit
US6954921B2 (en) * 2002-03-05 2005-10-11 Barcelona Design, Inc. Method and apparatus for automatic analog/mixed signal system design using geometric programming
US20030191611A1 (en) * 2002-04-05 2003-10-09 Hershenson Maria Del Mar Behavioral circuit modeling for geometric programming
US6909330B2 (en) * 2002-04-07 2005-06-21 Barcelona Design, Inc. Automatic phase lock loop design using geometric programming
AU2003224951A1 (en) * 2002-04-10 2003-10-27 Barcelona Design, Inc. Method and apparatus for efficient semiconductor process evaluation
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US20060055704A1 (en) * 2004-09-10 2006-03-16 Kruk James L Empty space reduction for auto-generated drawings
JP4592438B2 (ja) * 2005-02-08 2010-12-01 株式会社東芝 半導体集積回路のレイアウト方法、製造方法及びレイアウトプログラム
JP5141028B2 (ja) * 2007-02-07 2013-02-13 富士通セミコンダクター株式会社 マスクレイアウトデータ作成方法、マスクレイアウトデータ作成装置及び半導体装置の製造方法
US8131943B2 (en) * 2007-07-09 2012-03-06 International Business Machines Corporation Structure for dynamic initial cache line coherency state assignment in multi-processor systems
JP6328974B2 (ja) * 2014-03-28 2018-05-23 株式会社メガチップス 半導体装置及び半導体装置の設計手法

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US4827428A (en) * 1985-11-15 1989-05-02 American Telephone And Telegraph Company, At&T Bell Laboratories Transistor sizing system for integrated circuits
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US5416717A (en) * 1989-09-06 1995-05-16 Hitachi, Ltd. Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern
JP2746762B2 (ja) * 1990-02-01 1998-05-06 松下電子工業株式会社 半導体集積回路のレイアウト方法
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US5402358A (en) * 1990-05-14 1995-03-28 Vlsi Technology, Inc. Method and structure for the automated design of analog integrated circuits
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JP2509755B2 (ja) * 1990-11-22 1996-06-26 株式会社東芝 半導体集積回路製造方法
JP2739013B2 (ja) * 1992-09-01 1998-04-08 三菱電機株式会社 論理合成装置
JPH06102659A (ja) * 1992-09-22 1994-04-15 Toshiba Corp マスク・レイアウト生成方法
EP0610626A3 (en) * 1993-01-28 1995-02-08 Advanced Micro Devices Inc Method for simulating an integrated circuit.

Also Published As

Publication number Publication date
JPH08305001A (ja) 1996-11-22
US5633807A (en) 1997-05-27
EP0741365A1 (en) 1996-11-06
SG43363A1 (en) 1997-10-17
KR960042917A (ko) 1996-12-21

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