TW343241B - Recording paper - Google Patents

Recording paper

Info

Publication number
TW343241B
TW343241B TW085103779A TW85103779A TW343241B TW 343241 B TW343241 B TW 343241B TW 085103779 A TW085103779 A TW 085103779A TW 85103779 A TW85103779 A TW 85103779A TW 343241 B TW343241 B TW 343241B
Authority
TW
Taiwan
Prior art keywords
emulsions
lies
layer
range
recording layer
Prior art date
Application number
TW085103779A
Other languages
Chinese (zh)
Inventor
Norio Fukushima
Michiko Okamoto
Yoshio Yoshida
Tuyoshi Yasuda
Yoshihiro Kuroyama
Original Assignee
Nippon Seishi Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Seishi Kk filed Critical Nippon Seishi Kk
Application granted granted Critical
Publication of TW343241B publication Critical patent/TW343241B/en

Links

Abstract

A recording paper having a recording layer comprising 100 parts by weight of synthetic silica and 10-100 parts by weight of an aqueous resin or aqueous emulsion selected from polyvinyl alcohol, starch, casein, soybean protein, cellulose derivatives, styrene/acrylic resins, isobutyrene/maleic anhydride resins, acrylic emulsions, vinyl acetate emulsions, vinylidene chloride emulsions, polyester emulsions, styrene/butadiene latex or acrylonitrile/butadiene latex as its principal components, the layer being formed on at least one surface of a base paper and the amount of the layer lying within the range of 0.5-4.0 g/m2 in terms of solids on each surface on which the layer is formed, in which either the critical surface tension of the recording layer surface (γc) lies within the limits 32≰γc≰42 dyne/cm or the contact angle measured using water lies in the range of 100°-120°, or alternatively, the critical surface tension of the recording layer surface (γc) lies within the limits 32≰γc≰42 dyne/cm and the contact angle measured using water lies in the range of 100°-120°.
TW085103779A 1995-03-31 1996-03-27 Recording paper TW343241B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10062895A JP3150569B2 (en) 1995-03-31 1995-03-31 Dual-purpose recording paper for inkjet recording and electrophotographic transfer paper

Publications (1)

Publication Number Publication Date
TW343241B true TW343241B (en) 1998-10-21

Family

ID=14279109

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085103779A TW343241B (en) 1995-03-31 1996-03-27 Recording paper

Country Status (2)

Country Link
JP (1) JP3150569B2 (en)
TW (1) TW343241B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269701B2 (en) 2012-09-28 2016-02-23 Intel Corporation Localized high density substrate routing
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9666549B2 (en) 2013-09-25 2017-05-30 Intel Corporation Methods for solder for through-mold interconnect
US9929119B2 (en) 2012-12-06 2018-03-27 Intel Corporation High density substrate routing in BBUL package

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2004266919B2 (en) * 2003-08-26 2010-03-04 Nippon Paper Industries Co., Ltd. Process for producing inkjet recording medium
JP2011011492A (en) * 2009-07-03 2011-01-20 Ricoh Co Ltd Inkjet recording method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269701B2 (en) 2012-09-28 2016-02-23 Intel Corporation Localized high density substrate routing
US9679843B2 (en) 2012-09-28 2017-06-13 Intel Corporation Localized high density substrate routing
US10366951B2 (en) 2012-09-28 2019-07-30 Intel Corporation Localized high density substrate routing
US10796988B2 (en) 2012-09-28 2020-10-06 Intel Corporation Localized high density substrate routing
US9929119B2 (en) 2012-12-06 2018-03-27 Intel Corporation High density substrate routing in BBUL package
US10199346B2 (en) 2012-12-06 2019-02-05 Intel Corporation High density substrate routing in package
US10438915B2 (en) 2012-12-06 2019-10-08 Intel Corporation High density substrate routing in package
US10861815B2 (en) 2012-12-06 2020-12-08 Intel Corporation High density substrate routing in package
US11251150B2 (en) 2012-12-06 2022-02-15 Intel Corporation High density substrate routing in package
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9666549B2 (en) 2013-09-25 2017-05-30 Intel Corporation Methods for solder for through-mold interconnect

Also Published As

Publication number Publication date
JP3150569B2 (en) 2001-03-26
JPH08269893A (en) 1996-10-15

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees