TW340971B - Multiple-level conductor wordline strapping scheme - Google Patents

Multiple-level conductor wordline strapping scheme

Info

Publication number
TW340971B
TW340971B TW086109214A TW86109214A TW340971B TW 340971 B TW340971 B TW 340971B TW 086109214 A TW086109214 A TW 086109214A TW 86109214 A TW86109214 A TW 86109214A TW 340971 B TW340971 B TW 340971B
Authority
TW
Taiwan
Prior art keywords
lines
conductor
layer
wordline
covering
Prior art date
Application number
TW086109214A
Other languages
English (en)
Inventor
P Mcadams Hugh
R Mckee William
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW340971B publication Critical patent/TW340971B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW086109214A 1996-06-28 1997-07-02 Multiple-level conductor wordline strapping scheme TW340971B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2096196P 1996-06-28 1996-06-28

Publications (1)

Publication Number Publication Date
TW340971B true TW340971B (en) 1998-09-21

Family

ID=21801543

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086109214A TW340971B (en) 1996-06-28 1997-07-02 Multiple-level conductor wordline strapping scheme

Country Status (6)

Country Link
US (1) US6100588A (zh)
EP (1) EP0817269B1 (zh)
JP (1) JPH1065125A (zh)
KR (1) KR100440410B1 (zh)
DE (1) DE69738971D1 (zh)
TW (1) TW340971B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2340985A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
JP4886434B2 (ja) * 2006-09-04 2012-02-29 株式会社東芝 不揮発性半導体記憶装置
US10109674B2 (en) * 2015-08-10 2018-10-23 Qualcomm Incorporated Semiconductor metallization structure
US10304518B2 (en) * 2017-06-26 2019-05-28 Micron Technology, Inc. Apparatuses with compensator lines laid out along wordlines and spaced apart from wordlines by dielectric, compensator lines being independently controlled relative to the wordlines providing increased on-current in wordlines, reduced leakage in coupled transistors and longer retention time in coupled memory cells
US11018157B2 (en) 2017-09-28 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Local interconnect structure
CN110349960B (zh) * 2019-07-08 2021-06-18 上海华虹宏力半导体制造有限公司 嵌入式闪存的版图结构、嵌入式闪存及其形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4695981A (en) * 1984-12-04 1987-09-22 Hewlett-Packard Company Integrated circuit memory cell array using a segmented word line
JP2511415B2 (ja) * 1986-06-27 1996-06-26 沖電気工業株式会社 半導体装置
US5177027A (en) * 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5055898A (en) * 1991-04-30 1991-10-08 International Business Machines Corporation DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor
EP0573728B1 (en) * 1992-06-01 1996-01-03 STMicroelectronics S.r.l. Process for fabricating high density contactless EPROMs
JP3068378B2 (ja) * 1993-08-03 2000-07-24 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
US5671175A (en) * 1996-06-26 1997-09-23 Texas Instruments Incorporated Capacitor over bitline DRAM cell

Also Published As

Publication number Publication date
JPH1065125A (ja) 1998-03-06
KR100440410B1 (ko) 2004-10-14
DE69738971D1 (de) 2008-10-23
EP0817269B1 (en) 2008-09-10
EP0817269A2 (en) 1998-01-07
KR980006297A (ko) 1998-03-30
US6100588A (en) 2000-08-08
EP0817269A3 (en) 2002-01-23

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees