DE69207386T2 - Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's - Google Patents

Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's

Info

Publication number
DE69207386T2
DE69207386T2 DE69207386T DE69207386T DE69207386T2 DE 69207386 T2 DE69207386 T2 DE 69207386T2 DE 69207386 T DE69207386 T DE 69207386T DE 69207386 T DE69207386 T DE 69207386T DE 69207386 T2 DE69207386 T2 DE 69207386T2
Authority
DE
Germany
Prior art keywords
production
highly integrated
integrated contactless
contactless eprom
eprom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69207386T
Other languages
English (en)
Other versions
DE69207386D1 (de
Inventor
Gabriella Fontana
Orio Bellezza
Giuseppe Paolo Crisenza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE69207386D1 publication Critical patent/DE69207386D1/de
Publication of DE69207386T2 publication Critical patent/DE69207386T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69207386T 1992-06-01 1992-06-01 Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's Expired - Fee Related DE69207386T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830282A EP0573728B1 (de) 1992-06-01 1992-06-01 Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's

Publications (2)

Publication Number Publication Date
DE69207386D1 DE69207386D1 (de) 1996-02-15
DE69207386T2 true DE69207386T2 (de) 1996-09-12

Family

ID=8212118

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69207386T Expired - Fee Related DE69207386T2 (de) 1992-06-01 1992-06-01 Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's

Country Status (4)

Country Link
US (2) US5723350A (de)
EP (1) EP0573728B1 (de)
JP (1) JPH06188396A (de)
DE (1) DE69207386T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
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US5604141A (en) * 1994-03-15 1997-02-18 National Semiconductor Corporation Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction
US5409854A (en) * 1994-03-15 1995-04-25 National Semiconductor Corporation Method for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array
US5436478A (en) * 1994-03-16 1995-07-25 National Semiconductor Corporation Fast access AMG EPROM with segment select transistors which have an increased width
DE69738971D1 (de) * 1996-06-28 2008-10-23 Texas Instruments Inc Wortleitungsanordnung für Halbleiter-Speicherbauteil
EP0851485B1 (de) * 1996-12-24 2007-05-23 STMicroelectronics S.r.l. Selbstjustiertes Ätzverfahren zur verwirklichung der Wortleitungen integrierter Halbleiterspeicherbauelemente
DE69636738D1 (de) * 1996-12-27 2007-01-11 St Microelectronics Srl Kontaktstruktur für elektronische EPROM oder flash EPROM Halbleiterschaltungen und ihr Herstellungsverfahren
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
KR100277888B1 (ko) 1997-12-31 2001-02-01 김영환 플래쉬메모리및그의제조방법
JPH11265987A (ja) * 1998-01-16 1999-09-28 Oki Electric Ind Co Ltd 不揮発性メモリ及びその製造方法
ITTO980516A1 (it) * 1998-06-12 1999-12-12 St Microelectronics Srl Procedimento per la fabbricazione di transistori di selezione di memor ie non volatili serial-flash, eprom, eeprom e flash-eeprom in configur
US6033955A (en) * 1998-09-23 2000-03-07 Advanced Micro Devices, Inc. Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture
EP1017087A1 (de) 1998-12-29 2000-07-05 STMicroelectronics S.r.l. Herstellungsverfahren für einen halbleitersubstratintegrierten MOS-Transistor
EP1032029A1 (de) 1999-02-26 2000-08-30 STMicroelectronics S.r.l. Herstellungsverfahren für integrierte, elektronische Halbleiterspeicherbauelemente mit virtuell geerderter Zellenmatrix
EP1032035B1 (de) * 1999-02-26 2004-10-13 STMicroelectronics S.r.l. Herstellungsverfahren für elektronische Speicheranordnungen mit Zellenmatrix mit virtueller Erdung
US6862223B1 (en) 2002-07-05 2005-03-01 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
US7064978B2 (en) * 2002-07-05 2006-06-20 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
KR100655287B1 (ko) * 2004-11-11 2006-12-11 삼성전자주식회사 플로팅 게이트를 갖는 비휘발성 기억 소자의 형성 방법
KR100944591B1 (ko) * 2007-12-03 2010-02-25 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US8859343B2 (en) * 2013-03-13 2014-10-14 Macronix International Co., Ltd. 3D semiconductor structure and manufacturing method thereof

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US4519849A (en) * 1980-10-14 1985-05-28 Intel Corporation Method of making EPROM cell with reduced programming voltage
US4597060A (en) * 1985-05-01 1986-06-24 Texas Instruments Incorporated EPROM array and method for fabricating
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
US4785375A (en) * 1987-06-11 1988-11-15 Tam Ceramics, Inc. Temperature stable dielectric composition at high and low frequencies
US4780424A (en) * 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US4951103A (en) * 1988-06-03 1990-08-21 Texas Instruments, Incorporated Fast, trench isolated, planar flash EEPROMS with silicided bitlines
US4996668A (en) * 1988-08-09 1991-02-26 Texas Instruments Incorporated Erasable programmable memory
US5051796A (en) * 1988-11-10 1991-09-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
US5110753A (en) * 1988-11-10 1992-05-05 Texas Instruments Incorporated Cross-point contact-free floating-gate memory array with silicided buried bitlines
IT1235690B (it) * 1989-04-07 1992-09-21 Sgs Thomson Microelectronics Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia.
US4939105A (en) * 1989-08-03 1990-07-03 Micron Technology, Inc. Planarizing contact etch
JPH0783066B2 (ja) * 1989-08-11 1995-09-06 株式会社東芝 半導体装置の製造方法
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
US5111270A (en) * 1990-02-22 1992-05-05 Intel Corporation Three-dimensional contactless non-volatile memory cell
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
US5071782A (en) * 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
US5075245A (en) * 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
US5077230A (en) * 1990-08-03 1991-12-31 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth
US5102814A (en) * 1990-11-02 1992-04-07 Intel Corporation Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions
US5240870A (en) * 1991-04-18 1993-08-31 National Semiconductor Corporation Stacked gate process flow for cross-point EPROM with internal access transistor
US5212541A (en) * 1991-04-18 1993-05-18 National Semiconductor Corporation Contactless, 5v, high speed eprom/flash eprom array utilizing cells programmed using source side injection
US5120670A (en) * 1991-04-18 1992-06-09 National Semiconductor Corporation Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories
US5346842A (en) * 1992-02-04 1994-09-13 National Semiconductor Corporation Method of making alternate metal/source virtual ground flash EPROM cell array

Also Published As

Publication number Publication date
US5707884A (en) 1998-01-13
EP0573728A1 (de) 1993-12-15
EP0573728B1 (de) 1996-01-03
US5723350A (en) 1998-03-03
DE69207386D1 (de) 1996-02-15
JPH06188396A (ja) 1994-07-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee