TW334636B - The producing method for high density IC with stack capacitor DRAM device - Google Patents
The producing method for high density IC with stack capacitor DRAM deviceInfo
- Publication number
- TW334636B TW334636B TW085110556A TW85110556A TW334636B TW 334636 B TW334636 B TW 334636B TW 085110556 A TW085110556 A TW 085110556A TW 85110556 A TW85110556 A TW 85110556A TW 334636 B TW334636 B TW 334636B
- Authority
- TW
- Taiwan
- Prior art keywords
- polysilicon
- insulating
- deposit
- silicide
- bit line
- Prior art date
Links
Abstract
A method for producing stack capacitor of DRAM on semiconductor substrate, it includes following steps: Deposit gate dielectric on substrate, deposit 1st polysilicon on gate dielectric. Deposit 1st insulating on 1st polysilicon, define pattern to produce shallow trench on 1st insulating, 1st polysilicon, gate dielectric and semiconductor substrate.Deposit 2nd insulating on top surface of 1st insulating to fill trench, and remove 2nd & 1st insulating from top surface of 1st polysilicon. Deposit 1st silicide on top surface of 1st polysilicon & 2nd insulating, deposit 3rd insulating on 1st silicide. Define pattern of 3rd insulating, 1st silicide & 1st polysilicon, form polysilicon gate structure on gate dielectric, define pattern of 3rd insulating & 1st silicide, form metal island on top surface of 2nd insulating & inside shallow trench.Deposit 4th insulating, anisotropically etch 4th insulating, form 1st insulating spacer at sidewall of polysilicon gate, and remove gate dielectric from polysilicon gate, and form 1st insulating spacer on metal island structure.Implant 1st conductive dopant in polysilicon gate structure to form S/D area; Deposit 2nd polysilicon on top surface of 3rd insulating, polysilicon gate structure and metal island structure, to fill in polysilicon gate structure & space between metal island structure & polysilicon gate structure.Deposit 2nd silicide on 2nd polysilicon, deposit 5th insulating on 2nd silicide. Define pattern of 5th insulating, 2nd silicide & 2nd polysilicon, form bit line contact in between polysilicon gate structure to form passage through S/D, and portion bit line to cover polysilicon gate structure, and remain portion of 2nd polysilicon in between polysilicon gate structure and metal island structure. Deposit 6th insulating, anisotropically etch 6th insulating, form 2nd insulating spacer at sidewall of bit line contact structure, deposit 3rd polysilicon on top surface of bit line, metal island & polysilicon gate uncovered by bit line and on 2nd polysilicon. Define 3rd polysilicon pattern, to form bottom electrode of stack capacitor in bit line structures, form capacitor dielectric on bottom electrode, deposit 4th polysilicon on capacitor dielectric and top surface of bit line structure uncovered by bottom electrode, and define 4th polysilicon pattern to form top electrode of stack capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW085110556A TW334636B (en) | 1996-08-29 | 1996-08-29 | The producing method for high density IC with stack capacitor DRAM device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW085110556A TW334636B (en) | 1996-08-29 | 1996-08-29 | The producing method for high density IC with stack capacitor DRAM device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW334636B true TW334636B (en) | 1998-06-21 |
Family
ID=58263010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085110556A TW334636B (en) | 1996-08-29 | 1996-08-29 | The producing method for high density IC with stack capacitor DRAM device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW334636B (en) |
-
1996
- 1996-08-29 TW TW085110556A patent/TW334636B/en not_active IP Right Cessation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |