TW330324B - The manufacturing method for memory cell capacitor of DRAM - Google Patents

The manufacturing method for memory cell capacitor of DRAM

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Publication number
TW330324B
TW330324B TW085110546A TW85110546A TW330324B TW 330324 B TW330324 B TW 330324B TW 085110546 A TW085110546 A TW 085110546A TW 85110546 A TW85110546 A TW 85110546A TW 330324 B TW330324 B TW 330324B
Authority
TW
Taiwan
Prior art keywords
layer
conductive layer
capacitor
sacrificial layer
etch stopping
Prior art date
Application number
TW085110546A
Other languages
Chinese (zh)
Inventor
Yuan-Chang Hwang
Chyuan-Jong Wang
Menq-Song Liang
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW085110546A priority Critical patent/TW330324B/en
Application granted granted Critical
Publication of TW330324B publication Critical patent/TW330324B/en

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Abstract

A manufacturing method for memory cell capacitor of DRAM is used for forming MOS transistor on semiconductor substrate to produce memory cell capacitor. The method includes following steps: - Sequentially form insulating and etch stopping layer on semiconductor substrate; - Form contact window on insulating and etch stopping layer that are located on one of source & drain of MOS transistor; - Form 1st conductive layer on contact window and etch stopping layer; - Proceed etching back for 1st conductive layer, and remove 1st conductive layer located on etch stopping layer; - Form 1st sacrificial layer on etch stopping layer, and form opening on 1st sacrificial layer to define the range of bottom electrode plate of capacitor; - Form 2nd conductive layer on opening and 1st sacrificial layer; - Form 2nd sacrificial layer on 2nd conductive layer; - Proceed etching back for 2nd sacrificial layer, then use the 1:1 selecting rate of 2nd conductive to sacrificial layer to proceed etching back for 2nd conductive layer, and remove the 2nd conductive layer located on 1st sacrificial layer; - Remove 1st and 2nd sacrificial layer to let the 1st & 2nd conductive layer located in contact window to be the bottom electrode plate of capacitor; - Form dielectric on bottom electrode plate of capacitor; - Form upper electrode plate of capacitor on dielectric.
TW085110546A 1996-08-29 1996-08-29 The manufacturing method for memory cell capacitor of DRAM TW330324B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW085110546A TW330324B (en) 1996-08-29 1996-08-29 The manufacturing method for memory cell capacitor of DRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085110546A TW330324B (en) 1996-08-29 1996-08-29 The manufacturing method for memory cell capacitor of DRAM

Publications (1)

Publication Number Publication Date
TW330324B true TW330324B (en) 1998-04-21

Family

ID=58262603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085110546A TW330324B (en) 1996-08-29 1996-08-29 The manufacturing method for memory cell capacitor of DRAM

Country Status (1)

Country Link
TW (1) TW330324B (en)

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees