TW330325B - The manufacturing method for DRAM having porous-Si capacitor - Google Patents

The manufacturing method for DRAM having porous-Si capacitor

Info

Publication number
TW330325B
TW330325B TW086104186A TW86104186A TW330325B TW 330325 B TW330325 B TW 330325B TW 086104186 A TW086104186 A TW 086104186A TW 86104186 A TW86104186 A TW 86104186A TW 330325 B TW330325 B TW 330325B
Authority
TW
Taiwan
Prior art keywords
dielectric
layer
hsg
porous
etch
Prior art date
Application number
TW086104186A
Other languages
Chinese (zh)
Inventor
Shye-Lin Wu
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW086104186A priority Critical patent/TW330325B/en
Application granted granted Critical
Publication of TW330325B publication Critical patent/TW330325B/en

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

A manufacturing method for IC capacitor, it includes: - Form 1st dielectric on substrate; - Form 2nd dielectric on 1st dielectric; - Use lithography and etching technology to etch 1st & 2nd dielectric layer to form contact hole in 1st & 2nd dielectric; - Form 1st conductive on 2nd dielectric layer, and fill it into contact hole; - Form HSG-Si on 1st conductive layer; - Etch HSG-Si to separate HSG-Si; - Form SOG on HSG-Si and 1st conductive layer; - Proceed heat-treatment on SOG layer; - Etch SOG layer to expose the top of HSG-Si, then remain residual SOG layer on 1st conductive layer; - Use residual SOG layer as etching mask to etch portion of 1st conductive layer and HSG-Si to produce plurality trenches in 1st conductive layer, and remove the whole HSG-Si during the etching process; - Remove residual SOG to form porous-polysilicon structure; - Form photoresist on porous-polysilicon structure; - Etch porous-polysilicon structure till 2nd dielectric layer; - Form capacitor dielectric to cover the surface of porous-polysilicon structure; - Form 2nd conductive layer on capacitor dielectric.
TW086104186A 1997-04-01 1997-04-01 The manufacturing method for DRAM having porous-Si capacitor TW330325B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086104186A TW330325B (en) 1997-04-01 1997-04-01 The manufacturing method for DRAM having porous-Si capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086104186A TW330325B (en) 1997-04-01 1997-04-01 The manufacturing method for DRAM having porous-Si capacitor

Publications (1)

Publication Number Publication Date
TW330325B true TW330325B (en) 1998-04-21

Family

ID=58262604

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086104186A TW330325B (en) 1997-04-01 1997-04-01 The manufacturing method for DRAM having porous-Si capacitor

Country Status (1)

Country Link
TW (1) TW330325B (en)

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