TW307036B - - Google Patents

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Publication number
TW307036B
TW307036B TW084101521A TW84101521A TW307036B TW 307036 B TW307036 B TW 307036B TW 084101521 A TW084101521 A TW 084101521A TW 84101521 A TW84101521 A TW 84101521A TW 307036 B TW307036 B TW 307036B
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Taiwan
Prior art keywords
package
patent application
leads
lead frame
lead
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TW084101521A
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English (en)
Inventor
R Haas Glen Jr
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Texas Instruments Inc
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)

Description

A7 B7 3ΰν〇3β 五、發明说明（1 ) 對照之相Μ申請案 下述之已讓渡專利申請案於此併入，以供麥考： 申請案編號 申請曰期 ΤΙ檔案编號 07/890,900 05/29/92 ΤΙ-18091 發明領域 本發明係關於元件封裝。 發明背景 茲在不限制本發明之範國之原則下，以RF元件封装爲例 來説明本發明之背景。 迄今，於此領域中，於1 GHz以上之頻率運作之封裝通 常爲屬於金屬-陶瓷構造，或爲具有塑膠空腔蓋及貫穿塑 膠侧面而黏著之金屬引線之金屬座。 標準型S08, S014及S020塑膠封包封裝已使用於頻率高 達1 GHz之RF應用。然而，彼等之引線框係具有於介入引 線框中之ICs在設計時必須加以説明之高引線電感。引線 間之隔離亦甚低，一般於1 GHz時爲20 dB以下。此將限制 可於微波頻率介入封裝中之放大器之增益量，並將產生RF 埠與RF及DC埠間之耦合問題的可能性。 發明概要 吾人認知，目前存在有一種對於可使用於較高頷率應用 之成本較低廉，更具效率之元件封装的需求。本發明旨在 迎合此種需求。 一般言之，本發明之一種形式之元件封裝係包括：一引 線框，其包括有複數條可將電路接至該元件之引線；以及 本紙張尺度遑用中國國家樣準（CNS ) Α4规格（210X297公釐） --------·棄-- (免先閲讀#面之注$項再填寫本頁) Γ 經濟部中央標準局負工消費合作社印装 307036 a? 五、發明説明（2 ) 一接至該引線框之金屬接地件。警如，接地件得係一接到 引線框底側之接地芯堍，或係一可作爲接至引線框底侧之 封裝用座之金屬接地平面。 在本發明之另一形式中，有一個以上的引線之宽度實質 上係較其餘之引線寬度大。於運轉時，某些較究的引線係 接地’而有些寬引線則栽有RF信號。在本發明之又一形式 中，至少有某些引線係群集在一起成爲兩個以上的引線組 群，俾提供分屬每一引線组群之單一元件連接。 本發明之封裝得舆許多種型式之元件連用。此封裝得以 各種不同的方法予以構建及製造，俾達獲本發明之優點。 幾個可行方式將於下文説明。 本發明之另一形式之封裝元件係包括：一引線框，其包 括有複數條可將電路接至元件之引線；以及一接至引線框 之金屬接地件。警如，此封裝元件得爲一放大器，其包括 GaAs異接面雙極性雩晶體。本發明之封裝元件得係通信系 统之一部分，或係一無線電話機。 圈式之簡單説明 附圖中： «ΙΑ、1B係本發明之第一較佳實施例之元件封裝之視圈 番 费 國2爲本發明之第一較佳實施例引線框之平視國； 圈3A、3B係本發明之第一較佳實施例元件封裝之圈式； 圈4A、4B係本發明之第二較佳實施例之元件封裝及引線 框之國式； A7
五、發明説明（3 ) 圈5爲本發明之元件封裝之性能結果圈； ，6爲本發明之第三較佳實施例之元件封裝及引線框之 两式， 圈7A、7B係本發明之第四較佳實施例之 框之圈式； 元件封裝及引線 Ϊ- it 聞 經濟部中央標準局貝工消费合作社印製 圈8A、8B係本發明之第五較佳實施例之元件封裝及引線 框之國式； 圈9A、9B係本發明之第六較佳實施例之元件封裝及引線 框之圈式； 圈10A、10B係本發明之第七較佳實施例之元件封裝及引 線框之圈式； 明11A、11B係本發明之第八較佳實施例之元件錡裝及引 線框之圈式；以及 圈12係本發明之第九實施例之元件封裝之圈式。 除特别指明者外，不同圖式中之對應數字及符號係表示 對應的组件。 較佳實施例之詳細説明 具鳢表現本發明之構想之SO封裝業已實驗地付諸設計、 製造，並於高達6 GHz之頻率下運作而加以測試。與習知 之標準型SO封裝不同，本發明之封裝可提供低介入損失、 低VSWR、及微波頻率下之RF引線輿RF-DC引線間之高隔離 性。本發明之封装可提供低接地電感引線、低接地電感回 路路徑，及低熱阻抗。 本發明之實施例之單件式SO型引線框係可經由實施濾波 本紙張尺度逋用中困國家標率（CNS ) Α4规格（210X297公釐） Λ 之 注
I 寫 本 页 訂 307036 A7 B7 經濟部中央揉準局貝工消费合作社印製 五、發明説明（4 ) 器及微片觀念來選擇RF引線又寸以使RF埠SWR及介入損失 極小化而提高技術水準，並可經由改變接地引線至寬接地 样之構造而增大RF引線間之隔離性。此外，可將接地芯塊 加入下述之單件式S0型封裝實例中，以使其rf埠引線間之 隔離性可較未添加有接地芯塊之任何單件式引線框者增加 達10〜15dB之多。下述之兩件式封裝實例係具有標準型 S020外輪廓，並可封包於標準S020棋具中。兩件式封裝實 例可提供多至6個之RF埠，以供像接線器或混合器之多RF 埠電路使用，而複MMICs亦可安裝於封裝内。 此可經由將引線框及接地平面或封裝座布藏加以調整以 便控制RF引線特性阻抗使其接近50歐姆，使引線之低通濾 波特性最適化以增進封裝RF性能；及經由產生低重感金屬 座及低電感引線接地；而達成之。該等接地引線之適當定 位亦可增進RF埠引線間及DC輿RF埠引線間之隔離性。 下述之雙件式S0封裝係實現一種標準型S0外引線框，惟 亦可使用引線對以形成RF埠或接地引線埠。此有助於改變 總RF埠特性阻抗使其接近50歐姆，而且藉由於rf埠引線段 增加分路電容（即經由增加封裝内之引線寬度及增加MMIC 及外電路板上之附設點之分路電容），可完成一種低通濾 波器而將卓越封装RF性能提高至6 GHz。兩件式SO封裝之 第二組件係爲金屬座，其可作爲低重感電接地回路路徑， 並可提供自安裝於封裝底座上之MMIC至封裝地板之低熱阻 抗。S0封裝金屬座之底部完全曝露，以便將具有導電性環 氧樹脂或焊料之底座直接安裝於電路板上。輿接地芯塊一 請- 先 閲 讀 背— 之 注
I 旁 装 訂 本紙張尺度適用中國國家梂準（CNS) M规格（210><297公釐） 經濟部中央樣準局員工消费合作社印製 A7 B7 五、發明説明（5 ) 樣，此種直接金屬座特點係可使SO封裝之RF引線間之隔離 性增加程度超過10 dB。下述之兩件式S020封裝實例之RF 引線間之隔離性在約6 GHz之頻率下爲45dB以上，而在顧 率爲約3 GHz以下時隔離性可加大至超過5〇 dB。 本發明之單件式及兩件式SO封裝構想得應用於具有任何 引線數，如8，14, 16, 20, 28, 40等等之SO封裝。 標準型表面黏著式SO封裝可容許1C於1或2 GHz之頷率 下運作，惟ICs必須大幅調諧俾與封裝一起運作，而且無法遠 獲最大的1C性能。典型的SO封裝於1 GHz時會呈現高介入 損失（>1 dB)及高SWR (於1 GHz時，> 2:1 )。典型的SO封 裝其DC/IF/RF梢間之隔離性亦低，於1 GHz時一般爲20 dB 以下。此會產生不同信號輸入間之耦合問題，並限制放大 器增益量（一般限制爲小於20dB增益），按放大器增益係 可介入封裝中而不會產生振盪問题。典型的S〇封装亦具有 高熱阻抗，致使其無法使用於散逸較少瓦特功率之MMICs 〇 圈ΙΑ、1B、2、3A及3B«示本發明實施例之封裝1〇及引 線框12。參照國2 ’引線框12具有兩個RF埠引線（以RF IN 14及RF OUT 16表示）及兩個接地埠引線18、2〇 (以 GND表示）。其餘的四個引線得加以使用，俾提供偏廛及 控制信號至如安装在引線框12上之傳輪放大器3〇之组件。 圈2中之引線框12因數種原因而可於高達6 GHz之領率 下良好運作。RF IN 14及RF OUT 16引線寬度宜各爲接近 • 050" (1.25則〇 ’幾乎爲標準S0引線寬度的三倍。此一寬 度得小心選定，俾使封包於置放在由圈1之雹路板及散熱 本紙張尺度逍用中國國家梂準（CNS ) A4规格（210x297公釐） — ^ ·裳 訂 n 旅 (象先閲讀r面之注$項再填寫本頁) 經濟部中央標準局員工消费合作社印簟 30 ί 036 Α7 ______Β7_ 五、發明説明（6 ) 座所提供之金屬接地平面32上之塑膠中之引線得具傷近乎 50歐姆特性阻抗。 由於此係一種單件式引線框，故RF導體特性係由其引線 寬度輿厚度，接地平面32上方之導體14、16之高度、塑膠 封包劑之介質常數，及電路板35所提供之金屬接地平面32 加以決定。圈1Β提供一種實施方法實例，其係藉由於電路 板35上割削孔洞33，並以環氧樹脂34將封裝10安裝在金屬 平面及散熱座32上而完成之。此可爲多層鼇路板之金屬接 地平面。接地平面32上方之微片RF引線14、16之高度宜約 爲0.040" (1mm)。重路板上之電鍍通孔33得用作自封裝寬 接地引線18、20至金屬接地平面及散熱座32之接地回路路 徑。 一種替代方法係將S0-8引線RF封裝之引線向下彎曲成 鱗翼構形，俾得將封裝表面黏著於電路板。電路板之板 頂部上之接地平面金屬區宜安置於封裝之RF導體區下面。 此電路板頂部"接地平面"得藉通道連至電路板之下金屬層 〇 圈1A〜3B所示之接地引線18、20之寬線宜爲近乎0.150" 。此等極爲寬闊的引線可提供自封裝中心至電路板之低電 感。此低電感接地回路路徑係爲控制RF in/out埠14、16 間之隔離性之主要因素。此電感愈低，則封裝RF埠14、 16間之隔離性愈高。 寬接地引線18、20有助於作爲電路之其它埠間之遮蔽。 謦如’RF in 14及out 16埠引線係利用其間之寬接地引線 -8 - 本紙张Xjt逋用中國國家棣準（CNS ) A4规格（210X297公釐） i------,tr------^.^ (亦先閲讀t面之注f項再填寫本頁) A7 B7 五、發明説明（7 ) ' "" 20而分離。此引線2〇可減少RF引線14、16間之信號耦合， 從而改善RF引線14、16間之隔離性。 S0封裝隔離性可藉由將國4A中所示之接地芯塊40從引線 框12之底部中心直接接至封裝1〇下方之電路板，而進一步 獲得改善。此可大幅減小封装接地回路路徑之長度及電感 ’藉以增加RF埠14、16間之隔離性。 警如，接地芯塊40得係一藉環氧樹脂置設在引線框底部 上之圆形或矩形金屬盤。於模塑封裝1〇之後，芯塊40最好 係暴露於封裝10之底部，俾得與該金屬芯塊40直接電接觸 及熱接觸。在圈4A所示之儕視圈中，芯塊40表示爲引線框 12中心之一個圓圈。圈4B之封裝之側視國顯示封裝10於樸 塑之後，芯塊40之底部完全外露。 將宜爲圓形或矩形金屬盤之接地"芯堍"40附設於封装引 線框12之實驗證實：在1 GHz時，可增加RF埠14、16間之 隔離性達10〜15 dB，而於較高頻率時，隔離性亦有所增 加0 經濟部中央梯準局貝工消費合作社印装 須注意的是，此接地芯塊方法及思想可應用於任何S0-xx 引線框，以增進任何SO-χχ封裝之RF性能及隔離性。上述 之寬引線思想亦可與接地芯線fc合運用，或者，二者亦可 視需要個别應用。 具備及未具備接地芯塊之S0-8引線RF封装之測定特性係 於10 GHz下測定，而如國5所示，該圈係燴製至7 GHz。 圈5顯示：就RF埠14、16端接成短路之RF埠輿埠間之隔離 性言，未具備接地芯線之S0封装在1 GHz下之隔離性爲30 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） A7 —___ _B7_ _ 五、發明説明（8 ) 肋，而具備有接地芯塊40之SO封裝之隔離性將增加爲40dB ，其增加値爲10 dB (改善因數爲10)。 下附表1係簡略縝示具備及未具備接地芯塊之如-8引線 單件式引線框封裝（圈1〜4 )之洌定RF特性值。 表 1 有/無接地芯塊之單件式SO-8 RF引線框封裝之測定特性 頻率=1 GHz;施加於RF IN及RF OUT埠 (内部RF埠螓接成短路〉 請- 先 Μ 讀 背 之 注 介入摘失 (dB) VSfR RF埠間之隔離性 (dB) 無接地思塊 0.08 1.03 30.5 具備接地芯塊 0.09 1.10 40.5 旁 裝 下，有/無接地芯塊40個例之RF埠14、16間之隔離性測定 値分别爲大於50 dB及40 dB。 表1所示具40 dB隔離性之接地芯塊4〇之SO-8 RF封裝係 較1 GHz下之標準so-χχ引線框封裝者高約2〇 dB，亦即高 約100倍。此外，無論有/無接地芯塊，其VSWR及介入損 失均較1 GHz下之標準s〇-xx引線框者大幅改善。在i GHz 時，標準SO-χχ引線框封裝所呈現之介入損失爲大於〗〇dB ，而VSWR爲大於2 : 1。 兩件式SO封裝方法宜具有單獨引線框及單獨金屬接地平 面封裝座。雖然單件式S0_8 RF封裝之涮定性能甚佳且較 標準型SG-χχ?丨線框⑽性能上大幅改進惟在某些應用 訂 旅 經濟部中央標準局負工消费合作社印製 10 -
A7 - __ B7 五、發明説明（9 ) 中仍期望能進一步改善1 GHz下之RF埠間之隔離性，警如 改善至使1 GHz下之RF埠間隔離性達至60 dB。本發明之兩 件式封裝可提供甚高的RF埠間隔離性。 請· 先 閲 背- 之 注 訂 旅 經濟部中央榉準局貝工消费合作社印裝 兩件式S0-20封裝之較佳實施例係示於圈6A、6B。之所 以稱爲SO-20封裝，係因其外尺寸幾乎輿標準型SO-20封裝 者相同，惟具有較少的引線。^6A、6B中之封裝50爲具有 兩個组件，最好係一稱爲封座之矩形金屬桿接地平面50及 一上引線框54。H4A中之圓形金屬接地芯塊40宜以矩形金 屬接地桿52 (封裝座）取代之。此金屬座52係遠較圈4A中 之接地芯塊40大，且可遮蔽更大的區域。矩形封裝座金屬 接地桿52係可提供優越的低電感接地回路路徑，並可充作 於圈6A、6B中爲置於其上方之RF導體56、58之接地平面。 圈6A、6B中之RF導髖56、58可較圈4A、4B中之封裝安置成 更爲接近接地平面52 ;按國4A、4B之封装係依賴封裝下方 之電路板來提供接地平面，經由將RF導體56、58其距接地 平面之高度從國4B中之0.040"減小至約.010"或.020"(未 於圈6B之側視圈表示），可大幅減小RF引線56、58及RF 56、58與DC 66、68、70、72引線間之輻射耦合，以增加 RF引線56、58間之隔離性。此亦可減小欲達獲50欧姆特性 阻抗所需之引線寬度。與圈4B中之接地芯塊40相似，圈6B 中之封裝之金屬座52係完全曝露於封裝50之底部，俾得使 用導電性環氧樹脂或焊料而完成直接霣路徑及熱路徑連接 上引線框54之GND (接地 > 引線60、62、64得使用例如 -11 本紙張尺度逋用中國國家榡準（CNS ) A4规格（210X297公釐） 經濟部中央橾準局負工消费合作杜印製 δυ.ϋοϋ a? ____Β7 __ 五、發明説明（10 ) 類似鉚釘74之物件接至封裝座金屬桿52。彼等連接件74可 進一步減低接地路徑電感。與Η4Α者相似，GND引線60、 62係置於RF in 56與out埠58之間，俾作爲遮蔽，以減低 RF引線56、58間之耦合並增進RF引線56、58間之隔離性。 圈7A顧示兩件式SO-20封裝之替代實施例，其中之RF輸 入56及輸出58埠不再位於封裝之一側，而係以對角方式進 入封裝中。若需要時，此可使RF引線間之隔離性獲得某些 改善。 圈8A中之電路係一兩件式S0-20封裝，其使用輿國6A及 7A相似之金屬座，惟此次使用具20條外引線之引線框79, 並具有輿標準型SO-20引線框相同之外布置。圈8A中之金 屬座76係以實線内矩形表示，其具有四個自側邊突出之 '凸耳"，其中之接地引線宜"駐紮"或"鉚設"於基座。 圈8A顯示使用一對引線以形成RF埠80/82, 84/86, 88/ 90,而模型颟示：此種由引線對80/82, 84/86, 88/90來 组成RF埠之方法可達獲近乎50歐姆特性阻抗，假如將整個 結構視爲係一具有藉電容於兩側分路之串聯電感（引線） 之低通濾波器（分路C-串聯L-分路C低通濾波器）。 圈8A亦繽示使用引線對作爲接地引線92/94，96/98, 100/102，104/106，以減小接地5丨線電感。每一接地引線 對係藉鉚釘108接至封裝座76。此可將封裝之兩個組件連 接在一起。RF埠線，80/82, 84/86, 88/90及接地引線92 /94, 96/98, 100/102, 104/106宜交錯隔開，俾對接地引 線92/94, 96/98, 100/102, 104/106之遮蔽作用作最大利 -12 - 本紙張尺度適用中國國家棣準（CNS ) A4规格（210X297公釐） --------^-裳------訂------旅 (沐先閲讀背面之注$項再填寫本頁) 經濟部中央揉準局貝工消费合作社印装 A7 B7 五、發明説明（11 ) 用，以增進RF引線對80/82, 84/86，88/90間之隔離性。 爲能形成圈8A中之RF埠80/82, 84/86, 88/90,兩條搭
接線 110/112，114/116，118, 120 連接通常應自一 MMIC RF埠跨接至封裝RF埠對80/82，84/86, 88/90之每一引線。 國8A中所示封裝引線框79構造係可提供彈性。高達6個 之雙引線對可出入作爲RF埠。每一埠係藉一接地引線及/ 或封裝金屬座而與次一RF埠隔離。假設將一單極雙投 (SPDT)開關組合於封裝内，則須使用三個引線對作爲盱埠 ，而其餘引線則用以提供控制信號至開關。S020 RF兩件 式封裝亦可輿需要4個RF埠之SP3T開關連用，此仍將剩下 四個封裝"DC"引線可供控制信號使用。 S0-20 RF封裝之布藏彈性使得此種封裝對於如DC_6 GHz 之類比與數位多埠黨路應用極具吸引力。 圈9A類示一實施例，其中有一 HBT放大器13〇介入s〇2〇 RF封裝150中，須注意者爲RF輸入埠132/134。單一線136 係用以將MMIC RF接至封裝RF埠之引線种132/134之一，而 兩個封裝引線得使用短搭接線138在封裝内速接在一起。 RF輸出埠146/148係颟示兩搭接線140/142之正常搭接構造 ，而一搭接線接至每一引線146/148。 圈9A亦類示：此實例中，除安裝在封裝座152上之HBT放 大器130 MMIC之外，其它元件如M0SCAP 156及昀磁薄膜或 厚膜電路158亦得安裝在封裝座152上。其表面上設有導鳢 之_瓷雷路158係可用以將封裝15〇内之線長度減至最小。 此亦提供一種封裝彈性實例，俾得接受複组件。在圈9八所 -13 - 本紙張尺度通用中國國家橾準（CNS > A4规格（210X297公釐） ---------^ ▲------.订------^.^ (价先閱讀背面之注f項再填寫本頁) 經濟部中央揲準局負工消费合作社印輦 A7 B7 五、發明説明（12 ) 示之封装結構實例中，仍有五條引線160、162、164、166 、168並未使用。 圖10A中，如放大器雩路之重路係安裝於RF S020封裝 170内。於此實例中，放大器172及設於礬土上之薄膜或厚 膜電路174宜安裝在封裝170内。_瓷電路174得用以選定 封裝170内之偏壓信號輿控制信號之路徑，並將線長度減 至最小。 圈11A、11B類示封裝180構造之替代實施例。可將封裝 180之一端或兩端上之引線框182向内延伸，俾如所示般地 接近元件192。然後，可將引線框導體184、186、188、 190、194、196、198、200直接搭接於元件，而無需如圖 9A、10A所示之额外_瓷電路158、174。 使用本發明之封裝之幾個實施例已加以類示。然而，上 述諸實施例仍有許多的替代態樣及组合。警如，國lu所 示之廷伸引線框構想可與圈12所示之薄膜或厚膜網路 結合。本發明之許多其它實施例亦可付諸實現。 兩件式SO-20 RF封裝之RF性能測定已麵示：在沉_6 GHz 之傾率範國内，封裝運作甚爲良好。下迷表2係爲一簡短 的性能網要： 14 - 本紙诔纽顧+ HS家榡準（CNS ) ( 2丨GX297公着> ---------^-裳------訂------^咸 (免先聞讀背面之注$項再填寫本頁} 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（l3 ) 表 2 兩件式SO-20 RF封裝之Rf性能測定 頰率 介入損失 線短路隔離性 VSWR (MHz) (dB) (dB) 870 < 0.10 59 <1.20:1 1800 < 0.16 51 <1.20:1 2400 < 0.16 49 <1.20:1 此封裝於1 GHz之最壞情況短路隔離性為接近60 dB (當封 裝内蜂短路而接地時之RF蜂間之隔離性）。因此，增益位 準達40 dB以上之如高增益傳輸放大器之元件得安置於封 裝内，而無產生振盪或反饋問题之虞。低封裝VSWR及介入 損失亦表示MM 1C之性能因封裝而故變之程度甚微。 兩件式SO-xx RF封裝所提供之RF埠間之隔離位準係較標 準型SO-χχ封裝於1 GHz所能提供者高約40 dB，亦即高約 1〇,000倍。 舆RF S020封裝關專之另一额外優點在於可使用標準s〇2〇 模具來封包金屬座及引線框；此可大幅降低工具成本。警 如，完成此種構造之一種方法係在封裝金屬座之底部形成 壓痕’此壓·痕係於座中心之小矩形區内形成，約〇 〇〇5"， 以避免輿樸具上之隆起字母接觸。依此，可將封裝座置於 模具之陣列中，而不會接觸到彼等字母。於封裝组合在電 路板上之期間當中，壓痕區對封裝性能之影響並不大，而 -15 - 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） ----------装------訂------ (资先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ____B7 五、發明説明（14 ) 且將爲環氧樹脂或焊料所部分充填。 金屬封裝座及5丨線對、接地引線對5丨線框布蕙可應用於 S0-8，14、16、20、28，等等之梢封裝，俾產生一组高性 能、高隔離封裝。此外，TS0P及其它封裝型式之性能亦可 因上迷構思而獲益。 若需要時，可將封裝座在封裝長度方向上之尺寸做得小 些；非RF引線並不需要封裝座接地平面。 對非RF引線言，在搭接過程當中並不需要間隔物。因此 ，假如引線係於封裝内延伸時，如國11A所示，可能不需 要陶瓷或塑膠間隔物。 對於安裝在SO-RF封裝中且以光學造明塑膠予以封包之 電路，及以標準黑色不透明塑膠予以封包之電路，亦曾測 定其甚爲相似之RF性能。光學透明塑繆開啓了用以封包光 敏性ICs之可能性。輸入至塑膠封裝型1(：之信號或放大信 號之調變係可由光線提供/控制。譬如，紅色及黑色IR透 明染色塑膠亦屬可行，彼等將僅傳輸紅色或11{波長。 較佳實施例已於上文詳細説明。應知的是，本發明之範 面亦涵括與上述不同、惟仍落在申請專利範国所界定之範 面内之實施例。譬如，雖然本發明係麥照肝HBT放大器加 以説明，惟任何可因本發明封裝之優點而獲利之元件均可 使用。同樣地，封裝内之元件猜確安置方式，以及梢之數 目及布置，均可視需要加以變動。本發明之耩思亦可併入 於SO除外之其它型式的封裝。實驗數據係就某些頻率而提 供，然而，本發明之封裝在幾個頷帶内亦均可良好工作。 -16 - 本紙張處用兩家縣(CNS ) A4規格( | -裝 訂 f,^ (Λ-先閱讀背面之注意事項再填寫本頁) A7 、發明説明（15 ) 警:、’ X_波料率應用亦屬可行。本發明之封裝及構思將 可泛應用於目前及未來之發及GaAs類比舆數位積體電路 警如，本發明可應用於分房式電話技術。在審視本發明 之範«時，文字含意應詮释爲廣義性者。 雖然本發明已參照例示性實施例加以説明，惟此説明不 應解稞爲限制性者〇熟習本項技藝之人士於參照本説明書 之餘，將可知悉前迷例示性實施例之各種變更舆组合以及 本發明之其它實施例。因此，下附之申請專利範面昏在能 涵括任何此類變更或實施例。 請· 先 閲 之 注 項 再> 填 - |裝 頁 訂 經濟部中央標準局員工消費合作社印製 17 本紙張尺度適用中國國家橾準（CNS〉A4规格（210X297公釐）

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  1. 經濟部中央標準局貝工消費合作社印製 B8 C8 D8 六、申請專利範圍 1. 一種元件用封裝，包括： a. —引線框，其包括有可將電路接至該元件之複數條 引線，其中該等引線中至少有一引線係爲一具有低通濾 波器特性之RF引線；以及 b. —金屬接地件，該金屬接地件之前側係接至該引線 框，而該金屬接地件之背側爲裸露者。 2. 如申請專利範園第1項之封裝，其中該接地件係接地芯 塊。 3. 如申請專利範困第2項之封裝，其中該芯塊係接至該引 線框之底側。 4. 如申請專利範困第1項之封裝，其中該接地件係一可充 作該封裝之基座之金屬接地平面。 5. 如申請專利範困第4項之封裝，其中該接地平面係接至 該引線框之底側。 6. 如申請專利範团第1項之封裝，其中該等引線中之一或 一條以上的5丨線之寬度實質上係較其餘5丨線寬者。 7‘如申請專利範囲第1項之封裝，其中該等引線中至少有 某些引線係群集在一起成爲兩個以上的引線組群，俾使 每一引線组群得輿該元件形成單一連接。 8·如申請專利範園第1項之封裝，其中該等引線中有兩個 或兩個以上的引線係爲RF埠。 9.如申請專利範固第1項之封裝，其中該元件係可以特性 阻抗運作。 10·如申請專利範固第1項之封装，其中該引線框係向内 -18 - --------_裝------訂------^球 (t先閱讀背面之注意事項再填寫本頁) 紙張尺度適用中國國家棣準（CNS ) ( 210X297公釐） •严.厂* A8 B8 C8 D8 經濟部中央標率局貝工消費合作社印製 申請專利範圍 延伸，俾便利接至該元件。 u.如申請專利範圍第1项之封裝，其中使用有一麴瓷黨 路，俾選定信號路徑並將線長度減至最小。 12. 如申請專利範國第2項之封裝，其中多數個组件安裝 於封裝内》 13. 如申請專利範固第}項之封裝，其中該封裝係封包於 光學透明塑膠内。 14·如申請專利範園第13项之封裝，其中該光學透明塑膠 係僅於預定波長範國内爲透明者。 15. —種封裝型元件，包括： a. —引線框，其中包括有可將電路接至該元件之複數 條引線，其中該等引線中至少有一引線係爲一具有低通 濾波器特性之RF引線；以及 b. —金屬接地件，該金屬接地件之前側係接至該引線 框，而該金屬接地件之背側爲裸露者。 16. 如申請專利範園第15項之封裝型元件，其中該元件係 放大器。 17. 如申請專利範固第16項之封裝型元件，其中該放大器 包含GaAs異接面雙極性電晶雒。 18. 如申請專利範固第15項之封裝型元件，其中該元件係 爲通信系統之一部分。 -19 - 本紙張尺度逋用中國國家標準（CNS ) A4規格（21〇><297公釐） --------¾------，訂------ (t先聞讀背面之注意事項再填寫本頁)
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799213A (ja) * 1993-06-09 1995-04-11 At & T Corp 集積回路チップ
US5917233A (en) * 1997-02-18 1999-06-29 The Whitaker Corporation Integrated circuit having a parasitic resonance filter
US6211462B1 (en) * 1998-11-05 2001-04-03 Texas Instruments Incorporated Low inductance power package for integrated circuits
US6388319B1 (en) * 1999-05-25 2002-05-14 International Rectifier Corporation Three commonly housed diverse semiconductor dice
US6759742B2 (en) * 1999-10-12 2004-07-06 The Whitaker Corporation Interchangeable bond-wire interconnects
US6459147B1 (en) * 2000-03-27 2002-10-01 Amkor Technology, Inc. Attaching semiconductor dies to substrates with conductive straps
US6521982B1 (en) 2000-06-02 2003-02-18 Amkor Technology, Inc. Packaging high power integrated circuit devices
US6566164B1 (en) 2000-12-07 2003-05-20 Amkor Technology, Inc. Exposed copper strap in a semiconductor package
FI20021218A0 (fi) * 2002-06-20 2002-06-20 Nokia Corp Menetelmä radiojärjestelmän elektroniikkayksikön koneelliseksi valmistamiseksi, radiojärjestelmän elektroniikkayksikkö ja sen valmistamiseen käytettävä elektroniikkakomponentti
WO2006087822A1 (ja) * 2005-02-16 2006-08-24 Hitachi, Ltd. 電子タグチップ
US7489022B2 (en) * 2005-08-02 2009-02-10 Viasat, Inc. Radio frequency over-molded leadframe package
WO2008069755A1 (en) * 2006-12-05 2008-06-12 Infineon Technologies Ag Integrated semiconductor outline package
US8872333B2 (en) 2008-02-14 2014-10-28 Viasat, Inc. System and method for integrated waveguide packaging
JP4985809B2 (ja) 2010-03-23 2012-07-25 サンケン電気株式会社 半導体装置
US8592960B2 (en) 2010-08-31 2013-11-26 Viasat, Inc. Leadframe package with integrated partial waveguide interface
US9450547B2 (en) 2013-12-12 2016-09-20 Freescale Semiconductor, Inc. Semiconductor package having an isolation wall to reduce electromagnetic coupling
US9401682B2 (en) 2014-04-17 2016-07-26 Freescale Semiconductor, Inc. Structure for a radio frequency power amplifier module within a radio frequency power amplifier package
US9673164B2 (en) 2014-04-25 2017-06-06 Nxp Usa, Inc. Semiconductor package and system with an isolation structure to reduce electromagnetic coupling
US9349693B2 (en) 2014-08-05 2016-05-24 Freescale Semiconductor, Inc. Semiconductor device with an isolation structure coupled to a cover of the semiconductor device
US9986646B2 (en) 2014-11-21 2018-05-29 Nxp Usa, Inc. Packaged electronic devices with top terminations, and methods of manufacture thereof
WO2019026975A1 (en) * 2017-08-02 2019-02-07 Sumitomo Electric Device Innovations, Inc. METHOD FOR ASSEMBLING SEMICONDUCTOR DEVICE
US10438908B2 (en) * 2017-10-19 2019-10-08 Nxp Usa, Inc. Integrally formed bias and signal lead for a packaged transistor device
JP6991316B2 (ja) * 2018-04-25 2022-01-12 三菱電機株式会社 共用ベースプレート及びこれを備えた半導体モジュール
US11158567B2 (en) 2019-08-09 2021-10-26 Texas Instruments Incorporated Package with stacked power stage and integrated control die
US11715679B2 (en) 2019-10-09 2023-08-01 Texas Instruments Incorporated Power stage package including flexible circuit and stacked die
US11302615B2 (en) 2019-12-30 2022-04-12 Texas Instruments Incorporated Semiconductor package with isolated heat spreader
US11581859B2 (en) 2020-06-26 2023-02-14 Wolfspeed, Inc. Radio frequency (RF) transistor amplifier packages with improved isolation and lead configurations
CN118402064A (zh) * 2021-12-17 2024-07-26 罗姆股份有限公司 电子装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0052054A1 (en) * 1980-11-10 1982-05-19 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Packaged semiconductor device which provides for enhanced power dissipation
US4791473A (en) * 1986-12-17 1988-12-13 Fairchild Semiconductor Corporation Plastic package for high frequency semiconductor devices
EP0282617A1 (de) * 1987-03-18 1988-09-21 Texas Instruments Deutschland Gmbh Integrierte Schaltung mit einer elektrisch leitenden Trägerplatte
EP0331289A3 (en) * 1988-02-26 1991-04-03 Hitachi, Ltd. Semiconductor device with impedance matching means
US5072283A (en) * 1988-04-12 1991-12-10 Bolger Justin C Pre-formed chip carrier cavity package
US4933741A (en) * 1988-11-14 1990-06-12 Motorola, Inc. Multifunction ground plane
US5019941A (en) * 1989-11-03 1991-05-28 Motorola, Inc. Electronic assembly having enhanced heat dissipating capabilities
US5028741A (en) * 1990-05-24 1991-07-02 Motorola, Inc. High frequency, power semiconductor device

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EP0595600B1 (en) 1999-08-25
EP0595600A1 (en) 1994-05-04
DE69326112T2 (de) 2000-02-03
KR100306988B1 (ko) 2001-12-15
DE69326112D1 (de) 1999-09-30
JPH06283658A (ja) 1994-10-07
US5663597A (en) 1997-09-02
SG74556A1 (en) 2000-08-22

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