經濟部中央標準局員工消費合作社印製 IΊ Ic I 4 Ο I t w Γ dou 11 m m >700 2 Λ7 ___B7 五、發明説明（丨） 本發明是有關於一種形成淺溝渠隔離（Shallow Trench Isolation，STI )的方法，且特別是有關於一種以 问把度電獎型化學氣相沈積（High-Density Plasma Chemical Vapor Deposition，HDPCVD )法形成淺溝渠隔 離的方法。 .〜一- 溝渠隔離（Trench Isolation )，在超大型積體電路 (VLSI )製作上的應用’已愈來愈普遍。例如，已被廣 泛應用在新一代記憶體製程上的金氧半導體（MOS )隔離 技術，以及應用在動態隨機存取記憶體（DRAM )的製作 上等等。前者的原理，係利用非等向性（Anisotropic )乾 蝕刻（Dry Etching )，在MOS間“挖出”一道溝渠 (Trench )，然後陸續塡入絕緣物質，例如二氧化矽。而 後者，其溝渠不再做爲隔離之用，而是做爲DRAM胞的電 容器，使其在不損及DRAM積集度的情況下，而增加電容 器的面積。 請參照第la〜lc圖，其繪示習知一種形成淺溝渠隔 離的方法。首先，如第la圖所示，在一半導體基底10上， 例如一矽基底，陸續形成一墊氧化層12以及一矽氮化物層 Μ後，利用乾蝕刻以形成多數個溝渠16，並在溝渠16內 形成一薄氧化層（Lining Oxide ) 18，例如直接以熱氧化 法或沈積法來形成。接著，如圖lb所示，沈積一氧化層 Π於上述元件上，以完成該些溝渠16的溝塡（Gap Filling )，而由於溝渠16所造成基底10上的地形 (Topographic )變化，因此形成的氧化層Π，其在溝渠 ---------ί'Λ-------訂------成· I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） c,|l 4 Ο I t w t ϋ o c / .1 i m m y / 0 〇 2 c,|l 4 Ο I t w t ϋ o c / .1 i m m y / 0 〇 2 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（1 ) 16上的沈積將不爲一平坦面。接著，以化學機械硏磨法 (Chemical Mechanic Polishing » CMP )，將沈積在砂氮 化物層14上的氧化層11完全除去，以平坦化 (Planarizing )上述的元件，其結果如圖1 c所不。當CMP 進行時，晶片的正面壓在舖有一層硏磨墊（P〇lishiiTgTa~d ) 的硏磨台上，由於溝渠16的凹陷，使硏磨墊在較大的溝渠 處16c產生了墊變形（Pad Deformation )，如此一來，將 造成經平坦化過程後，至少有下列問題產生： 1. 渠溝的開口區域，即可能凹陷成盤狀（Dishing ) 13，而造成氧化層在較寬的溝渠16c內變薄。 2. 較小的砂氮化物層平台14a、14b上，將造成砂氮 化物的侵蝕（Si3N4 Erosion )或過度硏磨，即砂氮化物 可能被磨掉，若半導體基底被磨到，則將來這裡形成的元 會產生問題。 3. 較大的矽氮化物層平台14c上，將造成氧化層的殘 留（Oxide Remaining )。 4. 因矽氮化物層平台的大小不同，欲以單一的CMP硏 磨，很難達到將氧化層去除時，其嚴格的均勻性 (Uniformity )要求。 爲達到在剝除（Strip )矽氮化物層之前，將其上的氧 化層完全去除，經常以過度硏磨（Overpolishing )的方法 來進行，如此可解決上述第3、4項的問題，但是卻可能 使上述第1、2項的問題更加嚴重。因此，如第2a〜2d 圖所示，另一種在元件區（Device Area )上以反向罩幕 4 (诗先W讀背面之注意事項再填寫本頁)Printed by the Employees ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs I Ί Ic I 4 Ο I tw Γ dou 11 mm > 700 2 Λ7 ___B7 V. Description of the invention (丨) The present invention relates to a shallow trench isolation (STI) ) Method, and in particular, a method for forming a shallow trench isolation by high-density chemical vapor deposition (HDPCVD) method. . ~ One-trench isolation (Trench Isolation), the application of VLSI manufacturing has become more and more common. For example, the metal oxide semiconductor (MOS) isolation technology that has been widely used in the new generation of memory systems and the production of dynamic random access memory (DRAM) and so on. The principle of the former is to use anisotropic dry etching (Dry Etching) to "dig out" a trench between MOS, and then successively insert an insulating substance, such as silicon dioxide. In the latter case, the trench is no longer used for isolation, but as a capacitor of the DRAM cell, which increases the area of the capacitor without compromising the degree of DRAM accumulation. Please refer to Figures la ~ lc, which shows a conventional method for forming shallow trench isolation. First, as shown in FIG. 1a, after forming a pad oxide layer 12 and a silicon nitride layer M on a semiconductor substrate 10, such as a silicon substrate, dry etching is used to form a plurality of trenches 16, and the trenches A thin oxide layer (Lining Oxide) 18 is formed in 16, for example, directly formed by thermal oxidation method or deposition method. Next, as shown in FIG. 1b, an oxide layer Π is deposited on the above-mentioned elements to complete the gap filling of the trenches 16, and the topography on the substrate 10 due to the trenches 16 changes, thus forming The oxide layer Π, which is in the ditches --------- ί'Λ ------- order ------ cheng · I (Please read the precautions on the back before filling this page) The size of this paper is in accordance with Chinese National Standard (CNS) Λ4 specification (210X 297mm) c, | l 4 Ο I twt ϋ oc / .1 immy / 0 〇2 c, | l 4 Ο I twt ϋ oc / .1 immy / 0 〇2 Printed B7 by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (1) The deposit on 16 will not be a flat surface. Then, the chemical layer 11 (Chemical Mechanic Polishing »CMP) is used to completely remove the oxide layer 11 deposited on the sand nitride layer 14 to planarize (Planarizing) the above-mentioned device. The result is shown in FIG. 1c . When CMP is in progress, the front of the wafer is pressed against the grinding table with a layer of polishing pad (P〇lishiiTgTa ~ d). Due to the depression of the ditch 16, the pad is deformed at the larger ditch 16c (Pad Deformation), as a result, after the planarization process, at least the following problems will occur: 1. The opening area of the trench may be recessed into a dish shape (Dishing) 13, which causes the oxide layer to be wider The trench 16c becomes thinner. 2. The smaller sand nitride layer platform 14a, 14b will cause sand nitride erosion (Si3N4 Erosion) or excessive grinding, that is, sand nitride may be worn away, if the semiconductor substrate is rubbed, then here The yuan formed can cause problems. 3. The larger silicon nitride layer platform 14c will cause the oxide layer to remain (Oxide Remaining). 4. Due to the different size of the silicon nitride layer platform, it is difficult to achieve the strict uniformity (Uniformity) requirement when removing the oxide layer by a single CMP polishing. In order to completely remove the oxide layer on the silicon nitride layer before stripping it, it is often carried out by the method of overpolishing, which can solve the problems of items 3 and 4 above, but It may make the problems in items 1 and 2 above more serious. Therefore, as shown in Figures 2a ~ 2d, there is another way to reverse the screen on the device area (Device Area) 4 (Poem first read the precautions on the back and then fill in this page)
*1T 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X297公1 ) 1 I 4 0 I t w Γ d oc /.1 i m m \ /00 2 Λ7 B7 經濟部中央標隼局員工消費合作社印焚 五、發明説明（p ) (Reverse-Tone Mask )，形成淺溝渠隔離的方法便因應 而生。首先，請參照第2a圖，其如圖U及lb的製程，在 〜包含一墊氧化層22及一矽氮化物層24的半導體基底20 上，蝕刻形成了多數個溝渠26，並在溝渠26內形成一薄 氧化層28。之後，沈積一氧化層21以完成該些溝棠16·的 溝塡。接著，在氧化層21上塗覆一層光阻層23，並利用 微影（Photolithography )製程，以光罩定義出如圖2b的 光阻層圖案23，定義出的光阻層圖案23將形成在溝渠16 的上方。接著，如第2c圖所示，以溼蝕刻或乾蝕刻法蝕刻 氧化層21。之後，再利用CMP法將氧化層21完全去除， 以形成圖2d。 上述的反向罩幕法，係利用兩段式的處理方式，將氧 化層完全去除，雖然能解決傳統淺溝渠隔離形成時的缺 點，但是在半導體元件愈趨縮小的情況下，如線寬大小已 達 0_18μιτι 的深半次微米（Deep Sub-Half Micron )技術 時，在相距很近的溝渠26a、26b間，形成的較小矽氮化 物層平台24a、24b上，其光阻層23圖案間將靠得很近， 甚至相互連接形成另一光阻層圖案，如此便失去了反向罩 幕的意義，使得矽氮化物層24a ' 24b在CMP硏磨時，依 然會造成氮矽化物被侵蝕及氧化層殘留的情形發生。 因此，利用一種高密度電漿型化學氣相沈積法，其於 溝渠內的溝塡能力的特性，再利用修正上述反向罩幕的觀 念，以使CMP形成淺溝渠隔離時，能達到嚴格的均一性的 要求。 (請先閱讀背面之注意事項再填寫本頁) ，4* 1T The size of this paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 1) 1 I 4 0 I tw Γ d oc /.1 imm \ / 00 2 Λ7 B7 Printing and burning of the employee consumer cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (p) (Reverse-Tone Mask), the method of forming shallow trench isolation was born. First, please refer to FIG. 2a, which is shown in FIGS. U and 1b. On the semiconductor substrate 20 including a pad oxide layer 22 and a silicon nitride layer 24, a plurality of trenches 26 are formed by etching, and the trenches 26内 formation of a thin oxide layer 28. After that, an oxide layer 21 is deposited to complete the gully 16 of the gullies. Next, a photoresist layer 23 is coated on the oxide layer 21, and a photolithography process is used to define a photoresist layer pattern 23 as shown in FIG. 2b with a photomask. The defined photoresist layer pattern 23 will be formed in the trench 16 above. Next, as shown in FIG. 2c, the oxide layer 21 is etched by wet etching or dry etching. After that, the oxide layer 21 is completely removed by the CMP method to form FIG. 2d. The above-mentioned reverse mask method uses a two-stage treatment method to completely remove the oxide layer. Although it can solve the shortcomings of the traditional shallow trench isolation formation, but in the case of shrinking semiconductor devices, such as line width size When the Deep Sub-Half Micron technology of 0_18μιτι has been reached, the photoresist layer 23 pattern is formed between the smaller silicon nitride layer platforms 24a, 24b formed between the trenches 26a, 26b that are very close to each other Will be close together, and even interconnected to form another photoresist layer pattern, so that the meaning of the reverse mask is lost, so that the silicon nitride layers 24a '24b will still cause the nitrogen silicide to be eroded during CMP grinding And the oxide layer remains. Therefore, using a high-density plasma chemical vapor deposition method, the characteristics of the trench capacity in the trench, and then using the concept of revising the above-mentioned reverse mask to make the CMP form a strict trench isolation, can achieve strict Requirements for uniformity. (Please read the precautions on the back before filling out this page), 4
*1T 尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐) ~ A7 B7 [I 4 0 I i w I d o c / J I m m y / 0 0 2 五、發明説明（¥ ) 爲達到本發明的主要目的’提供一種形成淺溝渠隔離 的方法，包括下列步驟： a. 提供一半導體基底，並在基底上陸續形成一墊氧化 層及一矽氮化物層； b. 定義矽氮化物層與墊氧化層，在基底上形成•多ΊΤ個 溝渠； c. 在溝渠內形成一薄氧化層； d. 利用高密度電漿型化學氣相沈積法，在基底上沈積 一氧化層，使之塡滿溝渠； e. 定義氧化層，蝕刻去除寬度尺寸大於Ιμπι之矽氮化 物層上的氧化層：以及 f. 利用化學機械硏磨法，以矽氮化物層爲硏磨終點， 將剩餘之氧化層去除。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 圖示之簡單說明： 第la〜lc圖繪示習知一種形成淺溝渠隔離的製造方 法； 桌2 a〜2 d圖繪不一種以反向罩幕法形成淺溝渠隔離 的方法；以及 第3a〜2d圖繪示本發明之較佳實施例，一種以高密 度電漿型化學氣相沈積法沈積絕緣層，以形成淺溝渠隔離 的方法。 (請先閱讀背面之注意事項再填寫本頁) Λ. 丁 、\=0 經濟部中央標隼局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公煃） 經濟部中央標隼局員工消费合作杜印裝 f 11 c : I 4 (H t vv t d n c h nun \ / 0 0 2 A 7 B7 五、發明説明（l ) 實施例 請參照第3a圖，提供一半導體基底30 ’例如一矽基 底，並在半導體基底30上陸續形成一墊氧化層32以及一 矽氮化物層34後，再利用蝕刻，例如乾蝕刻，以形成多數 個溝渠3 6，並在溝渠3 6內形成一薄氧化層3 8，例['如·以·熱 氧化法或沈積法來形成，接著以HDPCVD法沈積一氧化層 40，HDPCVD法之電漿氣體包括矽烷（Silane，SiH4)、 氧及氬氣（Ar )，由於HDPCVD的特性，氧化層40在較 小的矽氮化物平台34a、34b上，將形成較薄的沈積，而 在較大的矽氮化物平台34c上，形成較厚的沈積。 接著，請參照第3b圖，在氧化層40上塗覆一層光阻 層42，並利用微影製程，以光罩定義出光阻層圖案42， 使較大尺寸，例如大於〗μπι，的矽氮化物層平台34c，其 上沈積的較厚氧化層，能被後續的蝕刻製程去除，此外， 所定義出的光阻層圖案42 ，其寬度必須多出一偏極 (Bias ) 44的寬度，使在矽氮化物層平台34c上被飩刻 掉氧化層4〇區域，比矽氮化物層平台34c的尺寸來得小， 如此才不會蝕刻掉溝渠36內的氧化層40，同時允許34c 上的氧化層可徹底被蝕刻掉，如此大塊的矽氧化物就沒有 氧化層殘留的問題。 接著，以溼蝕刻或乾蝕刻，除去未被光阻層42保護的 氧化層40 ’以形成圖3c所示。並將光阻層42去除後，利 用CMP法’以矽氮化物層34爲硏磨終點，將剩餘的氧化 層40完全去除，如此便可完成如圖3d的淺溝渠隔離的製 7 適用中國國家鮮（CNS ) Λ4規格（210 X297公趨) " ^ " (請先閱讀背面之注意事項再填寫本頁) λ. 訂 f- 11 c : 1 4 Ο I t « f d o c / I I m m y / 0 0 2 A 7 __B7 五、發明説明（△) 作。 經由本較佳實施例所形成的淺溝渠隔離，將具有下列 的優點： 1. 反向罩幕法不能適用於較小線寬的淺溝渠隔離，將 可以本較佳實施例完成。 、…- 2. 氧化層所形成的盤狀凹陷的情形將不會發生。 3. 矽氮化物層的侵蝕情況將降低。 4. CMP磨硏的均勻性將隨硏磨量的減少而有所改善。 5. CVD的產能（Throughputs )因溝渠氧化層的厚度 的減少：以及CMP的產能因硏磨量的減少而有所增 進。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 、訂 婢！ 經濟部中央標準局員工消費合作社印褽 8 本纸張尺度適用中國國家標率（CNS ) Λ4規格（210 X 297公漦）* 1T scale is applicable to China National Standard (CNS) Λ4 specification (210X297mm) ~ A7 B7 [I 4 0 I iw I doc / JI mmy / 0 0 2 V. Description of the invention (¥) To achieve the main purpose of the present invention ' Provide a method for forming shallow trench isolation, including the following steps: a. Provide a semiconductor substrate, and successively form a pad oxide layer and a silicon nitride layer on the substrate; b. Define the silicon nitride layer and the pad oxide layer, in • More than ΊT trenches are formed on the substrate; c. A thin oxide layer is formed in the trench; d. An oxide layer is deposited on the substrate using high-density plasma chemical vapor deposition method to fill the trench; e. Define the oxide layer, and etch and remove the oxide layer on the silicon nitride layer with a width greater than 1 μm: and f. Using the chemical mechanical grinding method, the silicon nitride layer is used as the grinding end point to remove the remaining oxide layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings, which are described in detail below. Brief description of the figures: Figures la ~ lc show a conventional manufacturing method for forming shallow trench isolation; Table 2 a ~ 2 d show a method for forming shallow trench isolation by reverse mask method; and section 3a ~ 2d shows a preferred embodiment of the present invention, a method for depositing an insulating layer by high-density plasma chemical vapor deposition to form a shallow trench isolation. (Please read the precautions on the back before filling in this page) Λ. Ding, \ = 0 The Ministry of Economic Affairs Central Standard Falcon Bureau employee consumption cooperation du printed this paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 Gongxu) Department of Central Standard Falcon Bureau Employee Consumption Cooperation Du Printing f 11 c: I 4 (H t vv tdnch nun \ / 0 0 2 A 7 B7 V. Invention description (l) For an embodiment, please refer to FIG. 3a to provide a semiconductor substrate 30 ′, for example, a silicon substrate, and a pad oxide layer 32 and a silicon nitride layer 34 are successively formed on the semiconductor substrate 30, and then etching, such as dry etching, is used to form a plurality of trenches 36, and the trenches 36 A thin oxide layer 38 is formed inside, for example ['such as · thermal oxidation method or deposition method, and then an oxide layer 40 is deposited by HDPCVD method, the plasma gas of HDPCVD method includes silane (Silane, SiH4), oxygen And argon (Ar), due to the characteristics of HDPCVD, the oxide layer 40 will form a thinner deposit on the smaller silicon nitride platforms 34a, 34b, and a thicker on the larger silicon nitride platform 34c Deposition. Next, please refer to Figure 3b, in the oxide layer 40 A photoresist layer 42 is coated, and a photolithography process is used to define a photoresist layer pattern 42 with a photomask, so that a silicon oxide layer platform 34c of a larger size, such as greater than Φμm, is deposited with a thicker oxide layer It can be removed by the subsequent etching process. In addition, the width of the defined photoresist layer pattern 42 must be more than the width of a polarizer (Bias) 44 so that the silicon nitride layer platform 34c is etched away and oxidized. The area of layer 40 is smaller than the size of the silicon nitride layer platform 34c, so that the oxide layer 40 in the trench 36 will not be etched away, while allowing the oxide layer on the 34c to be completely etched away, such a large piece of silicon is oxidized There is no problem of residual oxide layer. Next, by wet etching or dry etching, the oxide layer 40 ′ not protected by the photoresist layer 42 is removed to form the layer shown in FIG. 3c. After the photoresist layer 42 is removed, the CMP method is used 'Using the silicon nitride layer 34 as the end point of grinding, the remaining oxide layer 40 is completely removed, so that the shallow trench isolation as shown in Figure 3d can be completed. 7 Applicable to China National Fresh (CNS) Λ4 specification (210 X297 general trend) " ^ " (Please read the back first (Please fill out this page again if necessary) λ. Order f- 11 c: 1 4 Ο I t «fdoc / II mmy / 0 0 2 A 7 __B7 V. Description of the invention (△). Formed by this preferred embodiment Shallow trench isolation will have the following advantages: 1. The reverse mask method cannot be applied to shallow trench isolation with a smaller line width, which can be accomplished by this preferred embodiment. , ...- 2. Disc-shaped depressions formed by the oxide layer will not occur. 3. The erosion of the silicon nitride layer will be reduced. 4. The uniformity of CMP grinding will improve as the amount of grinding decreases. 5. The throughput of CVD (Throughputs) due to the reduction of the thickness of the trench oxide layer: and the production capacity of CMP has increased due to the reduction of the amount of grinding. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page), order maid! Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 8 This paper scale is applicable to China ’s National Standard Rate (CNS) Λ4 specification (210 X 297 gong)