經濟部智慧財產局員工消費合作社印製 4 4 9 83 9 a? 6055pif.doc/008 β7 五、發明說明（丨） 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種在半導體元件上形成隔離區的方法。 本申請案係申請於丨9"年1月ls日、日本申請案號 168111/1"9之申請案，主申請案一倂作爲參考。 八 至目前爲止’在半導體元件中，例如是DRAM(動態隨 機存取記憶體）’矽（Si)是一種便宜的成分，而隔離區則是 以STI(Shallow Trench Isolation，淺溝渠隔離）之技術來形 成。 請參照第1A圖至第1D圖說明STI技術形成隔離區之 方法。第1A圖至第1D圖係繪示傳統隔離區之製造流程的 剖面示意圖。隔離區的形成方法係先在基底100上形成一 層墊氧化層l〇2x ’再於墊氧化層ι〇2χ上形成一層氮化矽 (Si3N4)層104x(第1A圖）。接著，以蝕刻法去除氮化矽層 104x中預定形成隔離區之處，再鈾刻墊氧化層l〇2x與矽 基底100，以在基底100中隔離區之處形成溝渠106(第1B 圖）。其後，以譬如爲CVD(化學氣相沉積法）的方式，在溝 渠106之中以及氮化矽層104上沉積一層厚絕緣層(氧化 層）108(第 1C 圖）。接著，以 CMP(Chemical Mechanical Polish，化學機械硏磨法）的方式將氧化層108的表面平坦 化。其製程係硏磨氧化層18表面至暴露出氮化矽層的 表面。氮化矽層104係作爲化學機械硏磨製程的終止層’ 當氮化矽層104暴露出來之後則完成硏磨之製程。之後’ 去除氮化矽層104與墊氧化層102,以形成隔離區l〇8x(第 1D 圖）。 然而，以上述淺溝渠隔離技術在形成隔離區的過程 4 ^紙張疋度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4 -------------•裝·-------訂--------•線 (靖先閱讀背面之沒意事項再填寫本頁) 449839 ^ A7 6055pif.doc/008 β7 經濟部智慧財產局員工消貲合作社印製 五、發明說明（1 ) 中，當氧化層以化學機械硏磨製程施行平坦化時，各個隔 離區的硏磨特性係隨著每一個被CMP硏磨的區域而改 CMP是一種平坦化的方法，此方法係注入硏磨物質， 以位於基底上的硏磨墊硏磨物體表面（此處爲氧化物表面） 以平坦化的方法。當CMP製程硏磨至裸露出氮化矽層的表 面時，比較寬隔離區與窄隔離區的硏磨結果，寬隔離區被 硏磨之處的表面會深於氮化矽層的表面=由於使用於CMP 製程的硏磨墊係由具有彈性的物質所組成，因此，硏磨墊 在寬隔離區中心之處所產生的形變(Deflection)大於硏磨墊 在窄隔離區之處者。所以，硏磨墊在其發生形變之處的深 度會較深於氮化矽層的表面。 在上述方法中，當硏磨速率隨著隔離區的寬度而改變 時，隔離區的形狀亦會隨之而改變，因而使得隔離的能力 以及電晶體的特性發生改變。 ‘ 因此，傳統的方法，在施行CMP製程時係在隔離區形 成虛擬主動區(Dummy Active region，Dummy AC) ’ 以使硏 磨速率不會隨著隔離區的寬度而有所改變。 虛擬主動區並非是用來作爲主動區。虛擬主動區係在 隔離區的寬溝渠上留下島狀的基底、墊氧化層與氮化矽 層。因此，當氮化矽層因施行CMP製程而裸露出來時’/.由: 於虛擬主動區可以支撐寬隔離區上的硏磨墊，因此可 免硏磨墊發生形變。 陶 然而，以虛擬主動區之方式在製程之後，隔離區_ 在電性主動區。因此，在近幾年來，當半導體元件變得更 5 I-----•丨丨 III! j 1 丨 I 訂· ！1111 ^^ {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） A7 B7 449839 6055pifdoc/008 五、發明說明（> ) 小時，上述之方法容易菴成線電容的增加。 本發明之目的在於提出一種半遵御 、出七& 1丨、Μ^ΠΦ丨丄#龅厂辱之隔離區的製 = 之氧化層其硏磨速率的 棚之半導體元件的製造方法，其 ㈣基底上形成-層罩幕層，接著，在罩幕 _底中形成預定深度之溝渠，以用以形成隔離區方 在溝渠之中與罩幕層上形成-層絕緣層，再_^^ 使其平坦化至暴露出罩幕層。之後，去除罩幕層，$並 成絕緣層與施行平坦化步驟之間，在最小寬度大於 値的溝渠上形成一層氮化圖案層。 上述之隔離區溝渠例如是寬溝渠與窄溝渠，其彳系pi 一基底中，製造半導體兀件結構之隔離區的溝渠。^了將 絕緣層塡入於溝渠之中，以形成隔離區，當絕緣層 渠之後，絕緣層必須被硏磨與平坦化。而在進行硏 之前，在溝渠以外的基底上所形成的罩幕層，其材 磨速率較低於絕緣層的硏磨速率。當罩幕層在硏磨的 中裸露出來之際，則結束硏磨製程。硏磨製程結束時，^ 幕層中，具有高密度的區域，也就是窄溝渠上之絕 及具有低密度的區域，也就是寬溝渠上之絕緣層的_磨速 率將有所改變。寬溝渠上的絕緣層容易快速被硏磨，ggj 爲位於寬溝渠上之硏磨墊發生形變所造成°本發明在寬溝 渠的絕緣層上形成一層硏磨速率低於絕緣層的氮化圖案 層，可以同時硏磨寬溝渠上之絕緣層與窄溝渠上的袍緣 層，避免硏磨製程結束時寬溝渠上之絕緣層被過度研磨。 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公釐） ---------------裝--------訂---------線 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 449839 6055pif.doc/008 經濟部智慧財產局8工消費合作社印製 五、發明說明（4) 較佳之預定値，係以隔離區之溝渠上所形成的氮化層 爲基準’在施行硏磨製程時，硏磨墊到達罩幕層表面時硏 磨墊產生形變的極限寬度。 雖然此寬度係依照用以硏磨的硏磨墊的彈性而定，但 是’硏磨墊施加於被硏磨物體其表面的壓力、硏磨速度， 硏磨材料的種類等等，均與硏磨墊發生形變的最大寬度有 關。最大寬度’例如是半導體隔離區中10微米之溝渠。 較佳之氮化圖案層的形狀與寬度，係可以使氮化圖案 層在平坦化製程期間被去除者。 因此，相較於窄溝渠上之絕緣層，寬溝渠上之絕緣層 的硏磨速率可以被延緩。而且，由於氮化圖案層的厚度與 形狀，可以以硏磨製程去除，因此，在硏磨製程之後，可 以使氮化圖案層去除的時間減少。 此外，當在部分的絕緣層中形成溝渠，以用以形成氮 化圖案層之後，可以使氮化圖案層塡入於溝渠之中。 氮化圖案層的形狀與厚度係依據其本身之溝渠的形狀 與深度。因此，氮化圖案層的形狀與深度可以依照隔離區 其最小値之溝渠而定。當完成硏磨製程之後，可以調整窄 溝渠之上以及寬溝渠之上之絕緣層的硏磨速率，因此，可 以避免寬溝渠上的絕緣層被過度硏磨的現象。 而且，較佳的平坦化製程係包括第一平坦化製程與第 二平坦化製程。在硏磨絕緣層的第一平坦化製程中’必須 避免暴露出罩幕層的表面，而在第二平坦化製程時’方才 裸露出罩幕層的表面。而且，在進行第一平坦化製程與第 二平坦化製程之間，包括在溝渠的絕緣層上形成一層氮化 7 ----------------裝--------訂---------線 (請先閲讀背面之注意事項再堉寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（21〇χ 297公釐〉 經濟部智慧財產局員工消費合作社印製 ^49839 A7 _____6055pif.doc/008 β7 五·、發明說明（g ) 陶案層之步驟，其中，所述之溝渠係指隔離溝渠中，寬度 大於一預定値者。 因此’當第一平坦化與第二平坦化之硏磨製程結束 時’可以避免寬度大於一預定値之溝渠中的絕緣層被過度 硏磨的現象。較佳的預定寬度定義爲，硏磨墊到達罩幕層 _面其產生形變的極限寬度。 而且’在第一平坦化製程時，係硏磨絕緣層至位於罩 幕層上之絕緣層的厚度大於50nm，小於l〇〇nm。 此外，較佳的半.導體元件的製造方法包括在基底上形 成一層罩幕層；在罩幕層與其下方之基底中形成隔離區之 _渠，此溝渠具有一預定深度；塡入第一絕緣層，至少使 第一絕緣層的高度高於基底的最高表面；在寬度大於一預 定値之溝渠的絕緣層上形成一層氮化圖案層；在罩幕層、 第〜絕緣層與氮化圖案層上形成第二絕緣層；硏磨並平坦 化第二絕緣層至罩幕層的表面裸露出來；以及移除罩幕層 與氮化圖案層。 在塡入第一絕緣層的步驟中，所塡入的第一絕緣層例 如是以HDP(高密度電漿，High Density Plasma)方法所形成 者。因此，第一絕緣層可以塡入於隔離區的溝渠之中’並 且使其高度達到基底表面的最高之處。而且’使用HDP方 式，可以降低所沉積之第一絕緣層其厚度的差異。氮化圖 案層的形成方法係在寬度大於一預定値之寬溝渠的第一絕 緣層上形成氮化層。（較佳之預定値係等於第一平坦化製程 時，硏磨墊到達罩幕層，產生形變的極限寬度）。之後’沉 镣並硏磨一第二絕緣層，以使氮化圖案層可以被塡入於其 8 本紙張尺度適用中國國家標準（CNS)A4,規格（210x297公釐） -4 --1----------裝------丨丨訂- !1丨丨丨線 (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 49 839 A7 6055pif.doc/008 B7_ 五、發明說明U ) 中。在硏磨製程結束時，裸露出罩幕層的表面。在此同時， 形成於溝渠之中的氮化圖案層的表面亦被裸露出來。因 此，氮化圖案層的功用係作爲寬溝渠的罩幕層。位於氮化 圖案層下方的第一絕緣層將被硏磨得較深於基底的表面。 而且，在硏磨製程結束時，由於罩幕層與氮化圖案層可以 同時被去除，因此可以很容易地形成隔離區，而並不會增 加製程的步驟。 圖式之簡單說明： 第1A圖至第1D圖是一種傳統隔離區之製造流程的剖 面示意圖。 第2A圖至第2C圖係繪示本發明第一較佳實施例之一 種半導體元件之製造流程的示意圖。 第3A圖至第3C圖爲依據第2A圖至第2C圖繪示本 發明較佳實施例之製造流程的示意圖。 第4A圖至第4C圖係繪示本發明第一較佳實施例之製 造流程的剖面示意圖。 第5A圖至第5D圖爲依據第4A圖至第4C圖繪示本 發明第一較佳實施例之製造流程的示意圖。 第6A圖至第6D圖係繪示本發明第二較佳實施例之製 造流程的示意圖。 第7A圖至第7D圖係繪示本發明第三較佳實施例之製 造流程的示意圖。 第8A圖至第8D圖係繪示本發明第四較佳實施例之製 造流程的示意圖。 標記之簡單說明： 9 ------^--------裝--------訂---------線 (請先閱讀背面之注咅？事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 49839 A7 6055pif.doc/008 βτ 經濟部智慧財產局W工消费合作社印製 五、發明說明（1) 10、100 :基底 12、12x :罩幕層 14、14x、102x :墊氧化層 16、16x、104x :氮化砂層 18、40 ' 106 :溝渠 18a :窄溝渠 18b :寬溝渠 20、20x、108 :絕緣層 22、22x :氮化圖案層 30 :氧化層 108x :隔離區 實施縣 以下將配合所附圖式說明本發明之較佳實施例。圖式 中各個構件僅是槪略表示其形狀、大小與位置，以使本案 能更淸楚，然而並非用以限制本發明。 第2A圖至第2C圖以及第3A圖至第3C圖係繪示半 導體元件之隔離區的製造方法。第2A圖至第2C圖以及第 3A圖至第3C圖爲主要製程中各個流程的結構剖面圖。 首先，在基底10上形成一層罩幕層12x(第2A圖）。 基底10例如爲一矽基底，罩幕層12x例如爲一層墊氧化層 14χ與一層氮化砂層16x所組成。 接著，在罩幕層12x下方的基底10中形成一預定深度 的隔離溝渠18(第2B圖）。如第2B圖所示，溝渠18係由 窄溝渠18a(例如，寬度小於10微米的溝渠)與寬溝渠18b(例 如寬度大於10微米的溝渠)所組成。其後，在溝渠18之中 ----I----11--裝--------訂---------線- (請先閱讀背面之注意事項再填寫本ΐ > 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 449839 a? 6055pif-doc/008__B7 五、發明說明（）） 塡入絕緣層，此溝渠18係作爲隔離區。溝渠18例如是以 微影技術形成之罩幕層作爲蝕刻罩幕，蝕刻罩幕層12x以 及其下方之基底所形成者。溝渠18的深度需足以使塡 入其中的絕緣層電性隔離兩相鄰之元件。留下之罩幕層12 其下方的基底10區域係作爲主動區。 之後，在隔離溝渠18之中以及罩幕層12上形成一層 絕緣層20(第2C圖）。絕緣層2〇例如是以傳統CVD(化學 氣相沉積法)或HDP(高密度電漿沉積法)所形成之氧化矽 膜。在第2C圖中所繪示之絕緣層20係以CVD方法所形 成者。 其後，在隔離溝渠18中的寬溝渠ISb上形成一層氮化 圖案層22。氮化圖案層22之硏磨速率低於絕緣層20，其 中寬溝渠18b之最小寬度大於一預定値。預定値係爲施行 絕緣層2〇平坦化步驟時，一硏磨墊到達罩幕層12表面產 生變形的極限寬度。此極限寬度係由實驗而得，而在此例 中界定爲10微米》因此，氮化圖案層22係形成於寬度大 於10微米的寬溝渠18b上。氮化圖案層22例如是先以CVD 法在絕緣層20表面上形成氮化膜（Si3N4膜）(爲繪示出）， 然後’以微影技術與乾蝕刻法蝕刻氮化膜，以在寬度大於 10微米寬溝渠18b上形成氮化圖案層22。之後，硏磨絕緣 層20 ’至罩幕層12的表面裸露出來(第3Β圖）。此例中， 硏磨的方法爲CMP(Chemica丨Mechanical Polish，化學機械 硏磨法）。硏磨速率爲50微米/分鐘的氮化矽膜，其速率低 於氧化矽膜。因此，形成有氮化圖案層22之處的硏磨速率 將變得較爲緩慢。依照氮化圖案層22的膜厚與形狀，氮化 11 本紙張尺度適用中國困家標準（CNS)A4规格（21〇 « 297公* Ϊ ---- (請先閱讀背面之注^^項再浪寫本頁> V.'裝 -線· 經濟部智慧財產局貝工消费合作社印製 t 經濟部智慧財產局員工消費合作社印製 4-3839.Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 4 9 83 9 a? 6055pif.doc / 008 β7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing semiconductor devices. Method for forming an isolation region on a device. This application is an application filed on Jan. 9 " January ls, Japan application number 168111/1 " 9. The main application is for reference at a time. Eight to now 'In semiconductor devices, such as DRAM (Dynamic Random Access Memory)' Silicon (Si) is an inexpensive component, and the isolation area is based on STI (Shallow Trench Isolation) technology To form. Please refer to FIGS. 1A to 1D to describe a method for forming an isolation region by the STI technology. Figures 1A to 1D are schematic cross-sectional views showing the manufacturing process of a conventional isolation area. The isolation region is formed by first forming a pad oxide layer 102 'on the substrate 100, and then forming a silicon nitride (Si3N4) layer 104x on the pad oxide layer 102x (Fig. 1A). Next, the place where the isolation region is planned to be formed in the silicon nitride layer 104x is removed by etching, and then the oxide layer 102x and the silicon substrate 100 are etched with uranium to form a trench 106 in the isolation region in the substrate 100 (FIG. 1B). . Thereafter, a thick insulating layer (oxide layer) 108 is deposited in the trench 106 and on the silicon nitride layer 104 by, for example, CVD (chemical vapor deposition) (Fig. 1C). Next, the surface of the oxide layer 108 is planarized by CMP (Chemical Mechanical Polish). The process involves honing the surface of the oxide layer 18 to the surface where the silicon nitride layer is exposed. The silicon nitride layer 104 is used as a stop layer of the chemical mechanical honing process. After the silicon nitride layer 104 is exposed, the honing process is completed. After that, the silicon nitride layer 104 and the pad oxide layer 102 are removed to form an isolation region 108x (FIG. 1D). However, the process of forming the isolation zone with the above-mentioned shallow trench isolation technology 4 ^ Paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -4 ------------- • Equipment · -------- Order -------- • Line (Jing first read the unintentional matter on the back before filling in this page) 449839 ^ A7 6055pif.doc / 008 β7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative Cooperative 5. In the description of the invention (1), when the oxide layer is flattened by a chemical mechanical honing process, the honing characteristics of each isolation area are changed with each CMP honing area. A method of flattening, which is a method of injecting a honing substance, and honing an object surface (here, an oxide surface) with a honing pad on a substrate to planarize. When the CMP process is honed to the surface of the exposed silicon nitride layer, the honing results of the wide isolation region and the narrow isolation region are compared. The surface where the wide isolation region is honed is deeper than the surface of the silicon nitride layer = The honing pad used in the CMP process is composed of a substance having elasticity. Therefore, the deformation of the honing pad at the center of the wide isolation zone is greater than that of the honing pad at the narrow isolation zone. Therefore, the depth of the honing pad will be deeper than the surface of the silicon nitride layer. In the above method, when the honing rate is changed with the width of the isolation region, the shape of the isolation region is also changed accordingly, thereby changing the isolation capability and the characteristics of the transistor. ‘Therefore, the traditional method is to form a dummy active region (Dummy AC) in the isolation region during the CMP process so that the honing rate does not change with the width of the isolation region. The virtual active area is not intended as an active area. The virtual active region leaves an island-like substrate, pad oxide layer, and silicon nitride layer on a wide trench in the isolation region. Therefore, when the silicon nitride layer is exposed due to the CMP process, it is because: the virtual active region can support the honing pad on the wide isolation region, so the honing pad can be prevented from deforming. Tao However, after the manufacturing process in a virtual active area, the isolation area is in the electrical active area. Therefore, in recent years, when semiconductor components have become more 5 I ----- • 丨 丨 III! J 1 丨 I order!! 1111 ^^ {Please read the notes on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210x 297 mm) A7 B7 449839 6055pifdoc / 008 V. Description of the invention (>) hours, The above method can easily lead to an increase in line capacitance. The object of the present invention is to propose a method for manufacturing a semi-compliant, semi-compliance, manufacturing, and manufacturing of a semiconductor device for a shed with an isolation layer and a honing rate. -A -layer mask layer is formed on the substrate, and then a trench of a predetermined depth is formed in the bottom of the mask, so as to form an isolation zone. A -layer insulating layer is formed in the trench and the mask layer, and then ^^ It is flattened to expose the cover layer. After that, the mask layer is removed, and a nitrided pattern layer is formed on the trench having a minimum width greater than 値 between the insulating layer and the planarization step. The above-mentioned isolation area trenches are, for example, wide trenches and narrow trenches, which are pi-substrate trenches for manufacturing isolation areas of semiconductor element structures. ^ The insulating layer is inserted into the trench to form an isolation area. After the insulating layer is drained, the insulating layer must be honed and planarized. Before honing, the masking layer formed on the substrate outside the trench has a lower material polishing rate than the insulating layer. When the cover layer is exposed in the honing, the honing process ends. At the end of the honing process, the area of the curtain layer with high density, that is, the area above the narrow trench and the area with low density, that is, the insulation rate of the insulation layer on the wide channel will change. The insulating layer on a wide trench is easy to be honed quickly. Ggj is caused by the deformation of the honing pad located on the wide trench. The invention forms a nitrided pattern layer on the insulating layer of the wide trench with a lower honing rate than the insulating layer. It is possible to honing the insulation layer on the wide trench and the rim layer on the narrow trench at the same time, so as to avoid the grinding of the insulation layer on the wide trench at the end of the honing process. This paper size is applicable to China Solid State Standard (CNS) A4 specification (210 X 297 mm) ---- Line {Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 449839 6055pif.doc / 008 Printed by the 8th Industrial Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4) A better predetermined frame is based on the nitrided layer formed on the trenches in the isolation area as a reference. 'When the honing process is performed, the honing pad will have a deformation limit when the honing pad reaches the surface of the cover layer. Although this width is based on the elasticity of the honing pad used for honing, the pressure of the honing pad on the surface of the object being honed, the honing speed, the type of honing material, etc. are all related to the honing The maximum width of the pad deformation is related. The maximum width 'is, for example, a trench of 10 microns in the semiconductor isolation region. The preferred shape and width of the nitrided pattern layer are those capable of removing the nitrided pattern layer during the planarization process. Therefore, the honing rate of the insulating layer on the wide trench can be delayed compared to the insulating layer on the narrow trench. In addition, since the thickness and shape of the nitrided pattern layer can be removed by a honing process, after the honing process, the time for removing the nitrided pattern layer can be reduced. In addition, when a trench is formed in a part of the insulating layer to form a nitrided pattern layer, the nitrided pattern layer can be inserted into the trench. The shape and thickness of the nitrided pattern layer are based on the shape and depth of the trench itself. Therefore, the shape and depth of the nitrided pattern layer can be determined according to the minimum trench of the isolation region. After the honing process is completed, the honing rate of the insulating layer above the narrow trench and above the wide trench can be adjusted. Therefore, the phenomenon of excessive honing of the insulating layer on the wide trench can be avoided. Moreover, the preferred planarization process includes a first planarization process and a second planarization process. In the first planarization process of honing the insulating layer, 'the surface of the mask layer must be prevented from being exposed, and only during the second planarization process', is the surface of the mask layer exposed. In addition, between the first planarization process and the second planarization process, a layer of nitride is formed on the insulation layer of the trench. ----- Order --------- Line (Please read the precautions on the back before transcribing this page) This paper size applies to China National Standard (CNS) A4 (21〇χ 297 mm) 〉 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 49839 A7 _____ 6055pif.doc / 008 β7 V. Description of the invention (g) The steps of the ceramic case layer, wherein the ditch refers to the isolation ditch with a width greater than a predetermined Therefore, 'when the honing process of the first planarization and the second planarization is completed', the phenomenon that the insulation layer in a trench having a width larger than a predetermined ridge is excessively honed can be avoided. The preferred predetermined width is defined as, The honing pad has reached the limit width of the deformation of the mask layer. Also, in the first planarization process, the thickness of the honing insulating layer to the thickness of the insulating layer on the mask layer is greater than 50 nm and less than 100 nm. In addition, a preferred method for manufacturing a semi-conductor element includes forming a cover curtain layer on a substrate; Layer and a substrate forming an isolation region in the substrate below, the channel has a predetermined depth; the first insulating layer is inserted so that the height of the first insulating layer is at least higher than the highest surface of the substrate; the trench having a width greater than a predetermined channel Forming a nitride pattern layer on the insulating layer; forming a second insulating layer on the mask layer, the first to the first insulating layers and the nitride pattern layer; honing and flattening the second insulating layer to the surface of the mask layer; And removing the mask layer and the nitride pattern layer. In the step of inserting the first insulating layer, the first insulating layer inserted is formed by, for example, a HDP (High Density Plasma) method. Therefore, the first insulating layer can be inserted into the trench of the isolation region and its height reaches the highest point on the substrate surface. Furthermore, the HDP method can be used to reduce the thickness difference of the deposited first insulating layer. Nitrogen The method of forming the patterned pattern layer is to form a nitride layer on the first insulating layer having a width greater than a predetermined width of the trench. (The preferred predetermined temperature is equal to the first planarization process. The honing pad reaches the cover layer and produces Deformation width limit). Then 'sink and hob a second insulating layer so that the nitrided pattern layer can be incorporated into its 8 paper sizes. Applicable to China National Standard (CNS) A4, size (210x297 mm) ) -4 --1 ---------- install ------ 丨 丨 order-! 1 丨 丨 丨 line (please read the precautions on the back before filling this page) Wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau 4 49 839 A7 6055pif.doc / 008 B7_ V. Invention Description U). At the end of the honing process, the surface of the mask layer is exposed. At the same time, the surface of the nitrided pattern layer formed in the trench is also exposed. Therefore, the function of the nitrided pattern layer is to serve as a mask layer for a wide trench. The first insulating layer under the nitrided pattern layer will be honed deeper than the surface of the substrate. Moreover, at the end of the honing process, since the mask layer and the nitrided pattern layer can be removed at the same time, an isolation region can be easily formed without adding steps in the process. Brief description of the drawings: Figures 1A to 1D are schematic cross-sectional views of a manufacturing process of a conventional isolation region. Figures 2A to 2C are schematic diagrams illustrating a manufacturing process of a semiconductor device according to one of the first preferred embodiments of the present invention. Figures 3A to 3C are schematic diagrams illustrating the manufacturing process of the preferred embodiment of the present invention based on Figures 2A to 2C. Figures 4A to 4C are schematic sectional views showing the manufacturing process of the first preferred embodiment of the present invention. 5A to 5D are schematic diagrams illustrating the manufacturing process of the first preferred embodiment of the present invention according to FIGS. 4A to 4C. 6A to 6D are schematic diagrams showing a manufacturing process of the second preferred embodiment of the present invention. 7A to 7D are schematic diagrams illustrating a manufacturing process of a third preferred embodiment of the present invention. 8A to 8D are schematic diagrams illustrating a manufacturing process of a fourth preferred embodiment of the present invention. Simple description of the mark: 9 ------ ^ -------- install -------- order --------- line (please read the note on the back first? Please fill in this page again for this matter) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 49839 A7 6055pif.doc / 008 βτ Printed by W Industry Consumer Cooperative of Intellectual Property Bureau of Ministry of Economy 1) 10, 100: substrate 12, 12x: cover layer 14, 14x, 102x: pad oxide layer 16, 16x, 104x: nitrided sand layer 18, 40 '106: trench 18a: narrow trench 18b: wide trench 20, 20x , 108: insulation layer 22, 22x: nitrided pattern layer 30: oxide layer 108x: isolation area. The following embodiments will be described with reference to the accompanying drawings to illustrate preferred embodiments of the present invention. Each component in the drawing merely indicates its shape, size, and position, so that this case can be more conspicuous, but it is not intended to limit the present invention. FIGS. 2A to 2C and FIGS. 3A to 3C are diagrams showing a method for manufacturing an isolation region of a semiconductor element. Figures 2A to 2C and Figures 3A to 3C are structural cross-sectional views of each process in the main process. First, a mask layer 12x is formed on the substrate 10 (FIG. 2A). The substrate 10 is, for example, a silicon substrate, and the mask layer 12x is composed of a pad oxide layer 14x and a nitrided sand layer 16x, for example. Next, an isolation trench 18 (FIG. 2B) is formed in the substrate 10 under the mask layer 12x to a predetermined depth. As shown in FIG. 2B, the trench 18 is composed of a narrow trench 18a (e.g., a trench having a width of less than 10 microns) and a wide trench 18b (e.g., a trench having a width of greater than 10 microns). After that, in the ditch 18 ---- I ---- 11--install -------- order --------- line- (Please read the precautions on the back before Fill out this paper > This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 449839 a? 6055pif-doc / 008__B7 V. Description of the invention ()) Insulation layer, this trench 18 is used as isolation Area. The trench 18 is, for example, a mask layer formed by a photolithography technique as an etching mask, and the mask layer 12x and the substrate formed thereunder are etched. The depth of the trench 18 needs to be sufficient for the insulating layer inserted therein to electrically isolate two adjacent components. The area of the mask layer 12 left behind is the area of the substrate 10 as the active area. Thereafter, an insulating layer 20 is formed in the isolation trench 18 and on the mask layer 12 (Fig. 2C). The insulating layer 20 is, for example, a silicon oxide film formed by a conventional CVD (chemical vapor deposition) or HDP (high-density plasma deposition) method. The insulating layer 20 shown in Fig. 2C is formed by a CVD method. Thereafter, a nitride pattern layer 22 is formed on the wide trench ISb in the isolation trench 18. The honing rate of the nitrided pattern layer 22 is lower than that of the insulating layer 20, and the minimum width of the wide trench 18b is larger than a predetermined ridge. The predetermined width is the limit width when a honing pad reaches the surface of the cover layer 12 when the insulating layer 20 flattening step is performed. This limit width is obtained experimentally, and is defined as 10 microns in this example. Therefore, the nitride pattern layer 22 is formed on the wide trench 18b having a width greater than 10 microns. The nitride pattern layer 22 is formed by, for example, forming a nitride film (Si3N4 film) on the surface of the insulating layer 20 by a CVD method (shown for illustration), and then etching the nitride film by lithography and dry etching to provide A nitride pattern layer 22 is formed on the trenches 18b larger than 10 microns in width. After that, the surface of the honing insulating layer 20 'to the mask layer 12 is exposed (FIG. 3B). In this example, the honing method is CMP (Chemica 丨 Mechanical Polish). A silicon nitride film with a honing rate of 50 microns / minute is slower than a silicon oxide film. Therefore, the honing rate where the nitrided pattern layer 22 is formed becomes slower. According to the film thickness and shape of the nitrided pattern layer 22, the nitrided 11 paper size is applicable to the Chinese Standard for Household Standards (CNS) A4 (21〇 «297mm * Ϊ ---- (Please read the note on the back ^^ item first Zai Lang writes this page > V. 'Installation-Line · Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4-3839.
6055pif.doc/00S 五、發明說明（q) 圖案層22係作爲硏磨終止層或調整被硏磨區域的硏磨速 率之用。在第3B圖中’氮化圖案層22係用以調整寬溝渠 18b與窄溝渠Isa之絕緣層20的硏磨速率。因此，寬溝渠 18b上被硏磨的絕緣層20χ ’其被硏磨的深度低於基底1〇 其表面的高度的情況將可以避免。在此較佳實施例中，在 窄溝渠18a上方的絕緣層20以及位在寬溝渠18b之上的氮 化圖案層22係先被硏磨，當氮化圖案層22被硏磨殆盡之 後，其下方的絕緣層2〇將繼續被硏磨。在硏磨終點之際， 絕緣層20x的硏磨速率將因此而得以調整。 其後，去除剩餘的罩幕層12(第3C圖）。在此實施例中 覃幕層12係以墊氧化層14以及氮化矽層16所構成。因 此’以例如爲濕式蝕刻的方式去除氮化矽層16之後，再以 HF濕式蝕刻法或乾式蝕刻法去除墊氧化層14。 位於罩幕層:12下方之基底1〇係作爲主動區^僅沉積 於溝渠18的絕緣膚+、2〇x、係作爲隔離區，其可以分離兩相鄰 的主動區。 第一實施例 請參照第2A圖至第2C圖，第4A圖至第4C圖以及 第5A圖至第5C圖說明以氮化圖案層作爲硏磨圖案層之第 一實施例。第4A圖至第4C圖以及第5A圖至第5C圖係 繪示第一與第二實施例之製造流程結構的剖面示意圖。 在攝氏85〇度，含有濕氧的環境中，在基底10上形成 一層墊氧化層Wx。接著，在墊氧化層14x上形成氮化矽 層16x。氮化矽層16x係以CVD方式形成者，其厚度爲150 至200nm。作爲罩幕層12x的圖案化墊氧化層與氮化矽層 ---------------裝！---訂_1-------線 {請先閲讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家標準（CNS)A4規格（2玉〇 X 297公釐） 449839 6055pif.doc/008 A7 B7 經濟部智慧財產局貝工消費合作社印製 五、發明說明（(〇 ) 係以微影技術形成者。接著，以罩幕層12x爲罩幕，利用 RIE触刻基底10(第2B圖），以形成高度爲〇.2至〇.6微米 的溝渠18。此例中，窄溝渠18a之寬度小於1〇微米，寬 溝渠18b之寬度大於10微米。接著，使溝渠18的側壁氧 化，以在溝渠I8的內側形成氧化層3〇(第4A圖）。 其後’在溝渠18之中以及剩餘的罩幕層12上形成絕 緣層20。氧化矽層20係以HDp法形成，其高度約與溝渠 18等咼。被塡入於溝渠18之中的氧化矽層2〇，其被塡入 的闻度約與罩幕層I2其表面的高度相等。而且，氧化矽層 20亦會嵌入於氮化矽層ι6(第4B圖）之中。 在此實施例中’氮化圖案層將接續被形成於寬度大於 10微米的18b之上。其步驟係先以CVD法在整個氧化矽 層20的表面上形成一層厚度爲5〇111^至2〇〇ηηι的氮化圖案 層22x(第4C圖）。接著’以微影與蝕刻步驟去除其他區域 上的氮化圖案層22x’僅留下寬度大於10微米之寬溝渠i8b 上之氮化圖案層22x(第5A圖），以形成氮化圖案層22。考 慮微影的調整容許度，作爲氮化圖案層22的氮化矽層，其 高度以低於寬溝渠l8b(寬度大於1〇微米)其表面高度〇.5 微米較佳。 其後’硏磨絕緣層20,至罩幕層12的表面裸露出來(第 5B圖）。在此實施例中，係以相同於傳統之化學機械硏磨 法施行硏磨製程。由於氮化圖案層22作爲硏磨終止層，因 此，當罩幕層I2的表面裸露出來時，位於寬度大於1〇微 米之寬溝渠18b之中的絕緣層20x(氧化矽膜)並未被硏磨。 接著’去除罩幕層12。此實施例，在去除罩幕層12 13 ——--— I---------«5. I (請先閱讀背面之注奋？事項再填寫本頁) -^-°6055pif.doc / 00S V. Description of the Invention (q) The pattern layer 22 is used as a honing stop layer or for adjusting the honing rate of the honing area. In FIG. 3B, the 'nitridation pattern layer 22 is used to adjust the honing rate of the insulating layer 20 of the wide trench 18b and the narrow trench Isa. Therefore, the honing of the insulating layer 20x 'on the wide trench 18b can be avoided if the honing depth is lower than the height of the surface of the substrate 10. In this preferred embodiment, the insulating layer 20 above the narrow trench 18a and the nitrided pattern layer 22 above the wide trench 18b are first honed. After the nitrided pattern layer 22 is honed, The underlying insulating layer 20 will continue to be honed. At the end of the honing, the honing rate of the insulating layer 20x will be adjusted accordingly. Thereafter, the remaining mask layer 12 is removed (FIG. 3C). In this embodiment, the Qin curtain layer 12 is composed of a pad oxide layer 14 and a silicon nitride layer 16. Therefore, after the silicon nitride layer 16 is removed by, for example, wet etching, the pad oxide layer 14 is removed by HF wet etching or dry etching. The substrate 10 located below the mask layer 12 is used as an active area ^, and the insulating skin +, 20x, which is only deposited on the trench 18 is used as an isolation area, which can separate two adjacent active areas. First Embodiment Referring to FIGS. 2A to 2C, FIGS. 4A to 4C, and FIGS. 5A to 5C, a first embodiment in which a nitride pattern layer is used as a honing pattern layer will be described. Figures 4A to 4C and Figures 5A to 5C are schematic cross-sectional views showing the manufacturing process structures of the first and second embodiments. A pad oxide layer Wx is formed on the substrate 10 in an environment containing 85 ° C and wet oxygen. Next, a silicon nitride layer 16x is formed on the pad oxide layer 14x. The silicon nitride layer 16x is formed by a CVD method, and has a thickness of 150 to 200 nm. 12x patterned pad oxide layer and silicon nitride layer as mask layer --------------- install! --- Order_1 ------- line {Please read the precautions on the back before filling this page) The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (2 jade 〇X 297 mm) 449839 6055pif .doc / 008 A7 B7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The description of the invention ((〇) is based on lithography technology. Then, the mask layer 12x is used as the mask, and the substrate 10 is etched by RIE. (Figure 2B) to form a trench 18 having a height of 0.2 to 0.6 microns. In this example, the width of the narrow trench 18a is less than 10 microns, and the width of the wide trench 18b is greater than 10 microns. Next, the trench 18 is formed. The sidewall of the substrate is oxidized to form an oxide layer 30 on the inside of the trench I8 (FIG. 4A). Thereafter, an insulating layer 20 is formed in the trench 18 and the remaining mask layer 12. The silicon oxide layer 20 is formed by the HDp method. The thickness of the silicon oxide layer 20 is about the same as that of the trench 18. The silicon oxide layer 20 inserted into the trench 18 is about equal to the height of the surface of the mask layer I2. Furthermore, the silicon oxide layer 20 will also be embedded in the silicon nitride layer ι6 (Figure 4B). In this embodiment, the 'nitridation pattern layer will be successively formed in the wide Above 18b larger than 10 microns. The steps are to first form a nitride pattern layer 22x (Fig. 4C) with a thickness of 5011 ^ to 200nm on the entire surface of the silicon oxide layer 20 by CVD method. 'Remove the nitrided pattern layer 22x on other areas by lithography and etching steps' Only the nitrided pattern layer 22x (FIG. 5A) on the wide trench i8b with a width greater than 10 microns is left to form the nitrided pattern layer 22. Considering the adjustment tolerance of the lithography, as the silicon nitride layer of the nitride pattern layer 22, its height is preferably lower than that of the wide trench 18b (width greater than 10 microns) and the surface height thereof is 0.5 microns. The insulation layer 20 is exposed to the surface of the mask layer 12 (FIG. 5B). In this embodiment, the honing process is performed in the same manner as the conventional chemical mechanical honing method. Since the nitride pattern layer 22 is used as the honing The termination layer, therefore, when the surface of the mask layer I2 is exposed, the insulating layer 20x (silicon oxide film) located in the wide trench 18b having a width greater than 10 micrometers is not honed. Next, 'remove the mask layer 12 In this embodiment, after removing the cover layer 12 13 —————— I --------- «5. I (Please first ? Read the back of the note and then fill Fen matter of this page) - ^ - °
T 本紙張及度適用中國國家標準（CNSU4'規格（210 X 297公釐） ^4 經濟部智慧財產局員工消费合作社印製 449839 A7 6055pif.doc/008 \\η -------------------- 五、發明說明（（丨） 之氮化矽層I6的過程中，氮化圖案層22亦將被去除(第5C 圖）。其後，去除墊氧化層U(第5D圖）。氮化矽層16與氮 化圖案層22係以例如爲磷酸等之濕式蝕刻法去除者。墊氧 化層〗4係以HF之濕式蝕刻法或乾式蝕刻法去除者。 因此，較佳的氮化圖案層22x並未以虛擬主動區 (Dummy AC)的方式形成。 另一個修改的較佳實施例，係以相同於第〜實施例的 方法，透過HDP的方式在隔離溝渠IS中塡入一層高度約 與罩幕層12表面高度相當的氧化矽層(第一層絕緣層。 接著，作爲氮化圖案層22的氮化矽層再形成於寬度大於1〇 微米的寬溝渠18b之上。 以CVD法在氧化矽層20上形成另一層厚度爲3〇〇nm 至4〇Onm的氧化矽層(第二絕緣層），以覆蓋氮化圖案層 22。 在以CMP法施行平坦_程之後，以相同於第—實施 力所述之方法去除罩幕層12。 依此方式則可行成隔離區。 第二實施例 請參照第6A圖至第6D _明第二實施例，以硏磨的 方式去除氮化圖案層。第6A ®至第6D圖爲第二實施例中 主要製程中各個流程的結構剖面圖。 以下將說明第一與弟一實施例的不同之處，而其相同 之處則省略其說明。 如同第一實施例，在基底1〇上形成罩幕層Πχ，之後 形成隔離溝渠I8。與第一實施例相同的是，窄溝渠1Sa係 本紙張用中國國家標準（CNS)A4規格（210 X 297公^---~~ ------- ------------------，—訂-------— 丨 . C請先閲讀背&之涑意事項再填寫本頁) A7 B7 ^49839 6〇55pif.doc/(K)8 五、發明說明（) 寬度小於10微米者，寬溝渠18b係寬度大於10微米者。 之後，使溝渠18的側壁氧化，然後，以HDP法在溝 渠18之中形成絕緣層20(氧化矽膜）。在此實施例中，絕緣 層20的厚度大於第一實施例所述者，其厚度大於X，小於 Y。此處之X，其値爲溝渠18的深度加上50nm，Y之値爲 溝渠18的深度加上罩幕層12x之深度。 在寬度大於10微米的寬溝渠18b上形成氮化圖案層 22。在此實施例中，係以CVD法在整個氧化矽層20的表 面上形成厚度約爲20nm至50nm的氮化圖案層22x(第6B 圖）。其後，進行微影與蝕刻製程，以在作爲氮化圖案層22 之氮化矽層僅形成於寬度大於10微米的寬溝渠18b之上 (第6C圖）。 其後，硏磨氧化矽層20至罩幕層12的表面裸露出來。 在此實施例中，係以CMP法進行硏磨製程。由於其硏磨的 速率低於氧化矽層20，而氮化圖案層22的厚度又非常地 薄，約爲20至5Onm，因此，氮化圖案層22逐漸被硏磨， 而當罩幕層12裸露出來之際，氮化圖案層U將消失。因 此，可避免位於寬度大於10微米之寬溝渠18b之中的氧化 層20被過度硏磨的現象(第6D圖）。 以相同於第一實施例的方法，去除氮化矽層16與墊氧 化層14(第5C圖與第5D圖）。 在此實施例中，氮化圖案層2：2係用以調整硏磨速率之 用，使位於寬溝渠18b之絕緣層20與窄溝渠18a之絕緣層 20具有相同的速率。此外，由於氮化圖案層22可能被硏 磨去除，因此，在硏磨製程之後可以節省去除氮化圖案層 气紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公蜚） --------------裝---I--1 I 訂·！ ----線 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟邨智慧財產局員工消费合作社印製 449839 6055pif.doc/008 五、發明說明) 22所需要的時間^ 氮化圖案層22可以爲任意的形狀，且當罩幕層12表 面裸露出來之後，此氮化圖案層22將會被去除。 第三實施例 請參照第7A圖至第7D圖，說明第三實施例在隔離溝 渠上的絕緣層形成氮化圖案層。第7A圖至第7D圖爲第三 實施例中主要製程中各個流程的結構剖面圖。 在以下將說明與第二、第一實施例不同之處，而與第 一、第二實施例相同之處則省略其說明 以相同於第一實施例之方式，在基底10上形成罩幕層 12x，之後形成隔離溝渠18。在此實施例中，窄溝渠ISa 與寬溝渠18b係分別是基底10之中寬度小於10微米之溝 渠與寬度大於10微米之溝渠。當溝渠18的內側壁被氧化 之後，以傳統的CVD方法在溝渠18之中形成氧化矽層 20。此氧化矽層20係被塡入溝渠18之中至其表面的高度 等高而具有平坦的表面。其平坦的程度係指在電子顯微鏡 下無法偵測出氧化層受硏磨的區域。在此實施例中，氧化 矽層20的膜厚爲700nm至900nm(第7A圖）。 以微影與蝕刻技術在寬溝渠18b上的氧化矽層20形成 寬度大於l〇nm的溝渠40，以用以形成氮化圖案。後續以 CMP技術施行平坦化的過程中，用以形成氮化圖案之溝渠 40的深度、溝渠40其開口與底部的面積以及溝渠40其彼 此之間的距離，可以調整寬度大於10微米之寬溝渠18b上 的氧化矽層20的硏磨速率以及寬度小於10微米的窄溝渠 18a上之氧化矽層20的硏磨速率。因此，溝渠4〇的深度 --------------裝--------訂--- ----線 (請先闉讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS)A4鈮格（210 X 公釐） A7 B7 α 9 83 9 6055pif.doc/008 五、發明說明（(li ) 係由實驗而定。在實驗中，氮化層被塡入溝渠40中，且氧 化矽層中被嵌入氮化層的區域以及未嵌入氮化層的區域均 被硏磨。當硏磨之後，在電子顯微鏡下觀測，各區域的表 面高度相等則結束實驗。但是，溝渠40的深度不能低於罩 幕層I2的表面高度(第7B圖）。 在溝渠4〇之中塡入氮化層22x，以形成氮化圖案層。 在此例中，係以CVD法所形成之氮化砂層作爲塡入於溝渠 40之中的氮化層22x，以用以形成氮化圖案層。氮化層22x 中塡入於溝渠4〇之中的部分爲氮化圖案層22(第7C圖）。 接著，以CMP法硏磨氮化層22x與氧化砂層20，至 罩幕層12的表面裸露出來。此例中，嵌入氮化圖案層22 的區域，其硏磨速率低於沒有嵌入氮化圖案層22之區域。 當硏磨製程結束，罩幕層12裸露出來之際，氮化層22已 完全被硏磨殆盡。而且，位於寬溝渠18b之上、嵌入氮化 圖案層22之氧化矽層20’其硏磨的速率與位於窄溝渠18a 之上、位嵌入氮化圖案層22之氧化層2〇的硏磨速率相等。 因此，位於寬溝渠18b之上的氧化矽層20不會被硏磨至使 其之表面高度低於基底10的表面高度(第7D圖）。 之後，以相同於第一實施例(第5C圖與第5D圖）的方 法去除氮化矽層16與墊氧化層14。 因此，在此實施例中，氮化圖案層22係用以調整硏磨 速率，使位於寬溝渠18b之上的氧化矽層20與位於窄溝渠 18a之上的氧化矽層2〇具有相同的硏磨速率。而且，由於 氮化圖案層22可以硏磨去除，因此，可以節省硏磨製程之 後去除氮化圖案層22的時間。 本紙張尺度適用中舀國家標準（CNS)A4.規格（210 * 297公釐） -------------裝--------訂---------線 (諳先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 經濟部智慧財產局員工消费合作社印製 肩39 . . A7 6055pif.doc/008 五、發明說明) 第四實施例 請參照第8A圖至第8D圖，說明第四實施例於平坦化 製程時，在寬隔離溝渠的絕緣層上形成氮化圖案層。第SA 圖至第8D圖爲第四實施例中主要製程中各個流程的結構 剖面圖。 在以下的說明中，將說明與第一、第二、第三實施例 不同之處，而與第一、第二、第三實施例相同之處則省略 其說明。 以相同於第一實施例之方式，在基底10上形成罩幕層 12x(墊氧化層14x與氮化矽層16x)，之後形成隔離溝渠 18。在此實施例中，窄溝渠18a與寬溝渠18b係基底1〇之 中寬度小於10微米之溝渠與寬度大於10微米之溝渠。 當溝渠18的內側壁被氧化之後，以相同於第三實施例 所述之傳統的CVD方法在溝渠18之中形成膜厚爲7〇〇nm 至900nm的氧化矽層，以作爲絕緣層20(第8A圖）。 接著，硏磨絕緣層20,此過程並未裸露出罩幕層12(此 定義爲第一平坦化製程）。 此例中，係以CMP的方法硏磨氧化矽層20至氧化層 20距離罩幕層12的厚度爲50至lOOnm。在第一平坦化製 程結束時，氧化矽層20具有平坦的表面（第8B圖）。 接著，在隔離溝渠18之中，寬度大於10微米的18b 的絕緣層20上形成一層氮化圖案層22。 此例中，係以LPCVD法在氧化矽層20上形成厚度爲 50至lOOnm的氮化矽層(未繪出）。在此實施例中，其膜厚 爲lOOrnn。以微影與蝕刻技術，使氮化圖案層22僅形成於 -------------裝 - ---I--訂·！1!·線 ' < (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 五 經濟部智慧財產局貴工消費合作杜印敦 4 49839 6055pif,doc/008 發明說明（+) 寬度大於10微米的寬溝渠18b之上。施行第二道平坦化製 程’以去除氮化圖案層22。氮化圖案層22之形狀與尺寸 可以使得位於寬溝渠18b之氧化矽層20，其在第二平坦化 製程中的硏磨速率相等於位於窄溝渠ISa之氧化層2〇的硏 磨速率。（第8C圖）。 然後’硏磨剩餘的絕緣層20，至罩幕層12的表面裸 露出來(此定義爲第二平坦化製程）。此例中，係以CMP法 施行硏磨製程。由於位於寬溝渠18b上的氮化圖案層22其 硏磨的速率低，因此，在第二平坦化製程中，位於寬溝渠 18b之上的絕緣層20不會被硏磨至使其之表面高度低於基 底10的表面高度(第8D圖）。 之後，以相同於第一實施例(第5C圖與第5D圖)的方 法去除氮化矽層16與墊氧化層14d 因此，在此實施例中，氮化圖案層22係用以調整硏磨 速率，使位於寬溝渠18b之上的絕緣層20與位於窄溝渠 18a之上的絕緣層20具有相同的硏磨速率。而且，由於氮 化圖案層22可以硏磨去除，因此，可以節省硏磨製程之後 去除氮化圖案層22的時間。 依照第一至第四實施例所述，本發明能解決晶片，例 如是半導體元件在施行CMP製程所面臨的硏磨問題。由於 以CMP之方式可以硏磨較大的區域，因此，當一晶片的表 面被硏磨，例如是硏磨過程中硏磨墊的壓力分布或速度分 布不均時，則會有過度硏磨的區域產生。本發明於可能會 被過度硏磨的區域上形成氮化圖案層，可以使得晶片上的 硏磨速率均勻。 1----------- --裝 i !!1 訂·! ― 線' <請先閱讀背面之注音ΐ項再填寫本頁) 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公嫠) 9839 6055pif.doc/008 Λ7 B7 經濟部智慧財產局員工消費合作社印y 五、發明說明（丨1) 從以上的說明可以明白，本發明之半導體元件的製造 方法的特徵包括在基底上形成一層罩幕層，接著，在罩幕 層與其下方的基底中形成預定深度之溝渠，以用以形成隔 離區。其後，在溝渠之中與罩幕層上形成一層絕緣層，再 硏磨絕緣層並使其平坦化至裸露出罩幕層。之後，去除罩 幕層，再於形成絕緣層與施行平坦化步驟之間，在最小寬 度大於一預定値的溝渠上形成一層氮化圖案層。溝渠例如 是寬溝渠與窄溝渠，其係在同一基底中，用以製造半導體 元件結構之隔離區的溝渠。爲了將絕緣層塡入於溝渠之 中，以形成隔離區，當絕緣層塡入溝渠之後，絕緣層必須 被硏磨與平坦化。而在進行硏磨製程之前，於溝渠以外的 基底上形成之罩幕層，其材質的硏磨速率低於絕緣層的硏 磨速率。當罩幕層在硏磨的過程中裸露出來之際，則結束 硏磨製程。硏磨製程結束時，罩幕層中，具有高密度的區 域，也就是窄溝渠上之絕緣層以及具有低密度的區域，也 就是寬溝渠上之絕緣層的硏磨速率將有所改變。寬溝渠上 的絕緣層容易快速被硏磨，係因爲位於寬溝渠上之硏磨墊 形變所造成。本發明在寬溝渠的絕緣層上形成一層硏磨速 率低於絕緣層的氮化圖案層，可以同時硏磨寬溝渠上之絕 緣層與窄溝渠上的絕緣層，避免硏磨製程結束時寬溝渠上 之絕緣層被過度硏磨。 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範®所界定者爲準。 20 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 ------^-------I ύΛ.-- (請先閱讀背面之生意事項再填寫本頁> ί 言 ΓT This paper is suitable for the Chinese national standard (CNSU4 'specification (210 X 297 mm) ^ 4 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 449839 A7 6055pif.doc / 008 \\ η -------- ------------ 5. In the process of the invention ((丨) silicon nitride layer I6, the nitride pattern layer 22 will also be removed (Figure 5C). After that, the pad is removed Oxide layer U (Fig. 5D). The silicon nitride layer 16 and the nitride pattern layer 22 are removed by a wet etching method such as phosphoric acid. The pad oxide layer 4 is a wet etching method or a dry etching method by HF. Therefore, the preferred nitrided pattern layer 22x is not formed in the form of a dummy active area (Dummy AC). Another modified and preferred embodiment uses the same method as in the first to third embodiments through HDP In the isolation trench IS, a silicon oxide layer (first insulating layer) having a height approximately equal to the height of the surface of the mask layer 12 is inserted. Next, a silicon nitride layer as the nitrided pattern layer 22 is formed again with a width greater than 1. 0 μm wide trench 18b. Another layer of silicon oxide having a thickness of 300 nm to 400 nm is formed on the silicon oxide layer 20 by CVD (No. Two insulating layers) to cover the nitrided pattern layer 22. After the planarization process is performed by the CMP method, the mask layer 12 is removed in the same manner as described in the first embodiment. In this way, an isolation region is feasible. For the second embodiment, please refer to Figs. 6A to 6D.-The second embodiment removes the nitrided pattern layer by honing. Figs. 6A ® to 6D are structural sections of each process in the main process in the second embodiment. The following will describe the differences between the first embodiment and the first embodiment, and the same points will be omitted. Like the first embodiment, a mask layer Πχ is formed on the substrate 10, and then an isolation trench I8 is formed. The same as the first embodiment, the narrow trench 1Sa is a Chinese National Standard (CNS) A4 specification for this paper (210 X 297 mm) ---------------------------- ----------, —Order -------— 丨. C Please read the notes on the back & then fill out this page) A7 B7 ^ 49839 6〇55pif.doc / ( K) 8 V. Description of the invention () The width of the trench is less than 10 microns, and the width of the wide trench 18b is greater than 10 microns. Then, the sidewall of the trench 18 is oxidized, and then formed in the trench 18 by the HDP method. Edge layer 20 (silicon oxide film). In this embodiment, the thickness of the insulating layer 20 is greater than that described in the first embodiment, and its thickness is greater than X and less than Y. Here, X, where 値 is the depth of the trench 18 plus At 50nm, Y is the depth of the trench 18 plus the depth of the mask layer 12x. The nitride pattern layer 22 is formed on the wide trench 18b having a width greater than 10 microns. In this embodiment, the entire oxidation is performed by CVD. A nitride pattern layer 22x is formed on the surface of the silicon layer 20 to a thickness of about 20 nm to 50 nm (FIG. 6B). Thereafter, a lithography and etching process is performed to form the silicon nitride layer as the nitride pattern layer 22 only on the wide trench 18b having a width greater than 10 micrometers (FIG. 6C). Thereafter, the surface of the honing silicon oxide layer 20 to the mask layer 12 is exposed. In this embodiment, the honing process is performed by the CMP method. Since the rate of honing is lower than that of the silicon oxide layer 20, and the thickness of the nitrided pattern layer 22 is very thin, about 20 to 5 nm, the nitrided pattern layer 22 is gradually honed, and when the mask layer 12 When exposed, the nitrided pattern layer U will disappear. Therefore, the phenomenon that the oxide layer 20 in the wide trench 18b having a width greater than 10 micrometers is excessively honed can be avoided (Fig. 6D). In the same manner as in the first embodiment, the silicon nitride layer 16 and the pad oxide layer 14 are removed (FIGS. 5C and 5D). In this embodiment, the nitride pattern layer 2: 2 is used to adjust the honing rate so that the insulating layer 20 located in the wide trench 18b and the insulating layer 20 in the narrow trench 18a have the same rate. In addition, since the nitrided pattern layer 22 may be removed by honing, it is possible to save the removal of the nitrided pattern layer after the honing process. The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) --- ----------- install --- I--1 I order! ---- Line {Please read the notes on the back before filling this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Economic Consumers' Cooperatives of the Intellectual Property Bureau 449839 6055pif.doc / 008 V. Description of Invention 22 The required time ^ The nitrided pattern layer 22 can be of any shape, and after the surface of the mask layer 12 is exposed, the nitrided pattern layer 22 will be removed. Third Embodiment Referring to FIGS. 7A to 7D, a third embodiment is described to form a nitride pattern layer on an insulating layer on an isolation trench. Figures 7A to 7D are cross-sectional views showing the structures of the main processes in the third embodiment. In the following, the differences from the second and first embodiments will be described, and the same points as the first and second embodiments will be omitted. The description is the same as that of the first embodiment, and a mask layer is formed on the substrate 10. 12x, after which the isolation trench 18 is formed. In this embodiment, the narrow trench ISa and the wide trench 18b are a trench with a width of less than 10 microns and a trench with a width of greater than 10 microns in the substrate 10, respectively. After the inner wall of the trench 18 is oxidized, a silicon oxide layer 20 is formed in the trench 18 by a conventional CVD method. The silicon oxide layer 20 is inserted into the trench 18 to a height equal to the surface thereof and has a flat surface. The degree of flatness refers to the area where the abrasion of the oxide layer cannot be detected under the electron microscope. In this embodiment, the film thickness of the silicon oxide layer 20 is 700 nm to 900 nm (Fig. 7A). A trench 40 having a width greater than 10 nm is formed on the silicon oxide layer 20 on the wide trench 18b by lithography and etching techniques to form a nitride pattern. During the subsequent planarization by CMP technology, the depth of the trench 40 used to form the nitride pattern, the area of the opening and bottom of the trench 40, and the distance between the trenches 40 can be adjusted. Wide trenches with a width greater than 10 microns can be adjusted. The honing rate of the silicon oxide layer 20 on 18b and the honing rate of the silicon oxide layer 20 on the narrow trench 18a having a width of less than 10 microns. Therefore, the depth of the ditch 4〇 -------------- installed -------- order --- ---- line (Please read the precautions on the back before filling (This page) The paper size is subject to the national standard (CNS) A4 niobium (210 X mm) A7 B7 α 9 83 9 6055pif.doc / 008 V. The description of the invention ((li) is determined by experiments. In the experiments In the process, the nitrided layer is inserted into the trench 40, and the regions in which the nitrided layer is embedded and the regions in which the nitrided layer is not embedded in the silicon oxide layer are honed. After honing, each region is observed under an electron microscope. The end of the experiment is the same as the surface height. However, the depth of the trench 40 cannot be lower than the surface height of the mask layer I2 (Fig. 7B). A nitride layer 22x is inserted into the trench 40 to form a nitride pattern layer. In this example, the nitrided sand layer formed by the CVD method is used as the nitrided layer 22x inserted into the trench 40 to form a nitrided pattern layer. The nitrided layer 22x is inserted into the trench 40. The middle part is the nitrided pattern layer 22 (FIG. 7C). Next, the nitrided layer 22x and the oxide sand layer 20 are honed by the CMP method to the surface of the mask layer 12. The nitrided layer is embedded in this example. The area of the case layer 22 has a lower honing rate than the area where the nitride pattern layer 22 is not embedded. When the honing process is over and the mask layer 12 is exposed, the nitride layer 22 has been completely honed. The honing rate of the silicon oxide layer 20 'on the wide trench 18b and embedded in the nitride pattern layer 22 is equal to the honing rate of the oxide layer 20 embedded in the nitride pattern layer 22 on the narrow trench 18a. Therefore, the silicon oxide layer 20 on the wide trench 18b will not be honed so that its surface height is lower than the surface height of the substrate 10 (FIG. 7D). After that, the same as the first embodiment (5C) (See Figure 5D) to remove the silicon nitride layer 16 and the pad oxide layer 14. Therefore, in this embodiment, the nitride pattern layer 22 is used to adjust the honing rate so that the oxidation on the wide trench 18b is performed. The silicon layer 20 has the same honing rate as the silicon oxide layer 20 located on the narrow trench 18a. In addition, since the nitride pattern layer 22 can be removed by honing, the nitride pattern layer 22 can be removed after the honing process can be saved. The paper size applies to China National Standard (CNS) A4. Grid (210 * 297 mm) ------------- install -------- order --------- line (谙 read the precautions on the back first (Fill in this page) Printed by the Intellectual Property Bureau of the Ministry of Economy, Shellfish Consumer Cooperative, printed by the Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumer Cooperative, printed by 39.. A7 6055pif.doc / 008 V. Description of the invention) For the fourth embodiment, please refer to Figure 8A to FIG. 8D illustrates the formation of a nitride pattern layer on the insulating layer of the wide isolation trench during the planarization process in the fourth embodiment. Figures SA to 8D are cross-sectional views showing the structures of the main processes in the fourth embodiment. In the following description, differences from the first, second, and third embodiments will be described, and descriptions of the same points from the first, second, and third embodiments will be omitted. In the same manner as the first embodiment, a mask layer 12x (a pad oxide layer 14x and a silicon nitride layer 16x) is formed on the substrate 10, and then an isolation trench 18 is formed. In this embodiment, the narrow trench 18a and the wide trench 18b are trenches with a width of less than 10 micrometers and trenches with a width of more than 10 micrometers in the substrate 10. After the inner wall of the trench 18 is oxidized, a silicon oxide layer having a film thickness of 700 nm to 900 nm is formed in the trench 18 by the conventional CVD method described in the third embodiment as the insulating layer 20 ( Figure 8A). Next, the insulating layer 20 is honed. This process does not expose the cover layer 12 (this is defined as a first planarization process). In this example, the thickness of the silicon oxide layer 20 to the oxide layer 20 by the CMP method is 50 to 100 nm from the mask layer 12. At the end of the first planarization process, the silicon oxide layer 20 has a flat surface (FIG. 8B). Next, a nitride pattern layer 22 is formed on the insulating layer 20 in the isolation trench 18 with a width greater than 10 microns. In this example, a silicon nitride layer (not shown) having a thickness of 50 to 100 nm is formed on the silicon oxide layer 20 by the LPCVD method. In this embodiment, the film thickness is 100 rnn. With lithography and etching technology, the nitrided pattern layer 22 is formed only on the ------------- equipment---- I--ordered! 1! · Line '(Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 Consumption by Noble Workers, Intellectual Property Bureau, Ministry of Economic Affairs Cooperation Du Indun 4 49839 6055 pif, doc / 008 Description of the invention (+) Above the wide trench 18b with a width greater than 10 microns. A second planarization process is performed to remove the nitrided pattern layer 22. The shape and size of the nitride pattern layer 22 can make the honing rate of the silicon oxide layer 20 in the wide trench 18b in the second planarization process equal to the honing rate of the oxide layer 20 in the narrow trench ISa. (Figure 8C). Then, the remaining insulating layer 20 is honed, and the surface of the mask layer 12 is exposed (this is defined as the second planarization process). In this example, the honing process is performed by the CMP method. Because the rate of honing of the nitrided pattern layer 22 on the wide trench 18b is low, in the second planarization process, the insulating layer 20 on the wide trench 18b will not be honed to its surface height. Below the surface height of the substrate 10 (Figure 8D). Thereafter, the silicon nitride layer 16 and the pad oxide layer 14d are removed in the same manner as in the first embodiment (FIGS. 5C and 5D). Therefore, in this embodiment, the nitride pattern layer 22 is used to adjust the honing Rate so that the insulating layer 20 above the wide trench 18b and the insulating layer 20 above the narrow trench 18a have the same honing rate. Moreover, since the nitrided pattern layer 22 can be removed by honing, the time for removing the nitrided pattern layer 22 after the honing process can be saved. According to the first to fourth embodiments, the present invention can solve the problem of honing of wafers, such as semiconductor devices, during the CMP process. Since a large area can be honed by CMP, there will be excessive honing when the surface of a wafer is honed, for example, when the pressure distribution or speed distribution of the honing pad is uneven. Area generated. The present invention forms a nitride pattern layer on an area that may be excessively honed, so that the honing rate on the wafer can be made uniform. 1 ------------Install i !! 1 Order ·! ― Line '< Please read the phonetic note on the back before filling out this page) This paper size applies Chinese National Standard (CNS > A4 specification (210 X 297 gong) 9839 6055pif.doc / 008 Λ7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (丨 1) As can be understood from the above description, the method of manufacturing the semiconductor device of the present invention The features include forming a mask layer on the substrate, and then forming a trench of a predetermined depth in the mask layer and the substrate below it to form an isolation zone. Thereafter, a layer is formed in the trench and on the mask layer. Insulating layer, and then honing and flattening the insulating layer to expose the mask layer. After that, remove the mask layer, and then between the formation of the insulating layer and the planarization step, on a trench with a minimum width greater than a predetermined width A layer of nitride pattern is formed. The trenches are, for example, wide trenches and narrow trenches, which are in the same substrate, and are used to manufacture the trenches of the isolation region of the semiconductor device structure. In order to insert the insulating layer into the trenches to form the isolation region , When the insulating layer penetrates into the trench After that, the insulating layer must be honed and flattened. Before the honing process is performed, the mask layer formed on the substrate outside the trench has a material with a lower honing rate than the insulating layer. When the mask When the layer is exposed in the honing process, the honing process is ended. At the end of the honing process, the mask layer has a high-density area, that is, an insulating layer on a narrow trench and a low-density area. That is, the honing rate of the insulating layer on the wide trench will be changed. The insulating layer on the wide trench is easy to be honed quickly because of the deformation of the honing pad located on the wide trench. The insulation of the present invention in the wide trench A nitride pattern layer with a lower honing rate than the insulating layer can be formed on the layer, and the insulating layer on the wide trench and the insulating layer on the narrow trench can be honed at the same time to prevent the insulating layer on the wide trench from being excessively honed at the end of the honing process Although the present invention has been disclosed above with a preferred embodiment, 'but it is not intended to limit the present invention, any person skilled in the art' can be used in various ways without departing from the spirit and scope of the present invention. Changes and Retouching 'Therefore, the scope of protection of the present invention shall be defined as defined in the attached Patent Application®. 20 Private paper standards are applicable to China National Standard (CNS) A4 (210 X 297 mm) ----- -^ ------- I ύΛ .-- (Please read the business matters on the reverse side before filling out this page > ί 言 Γ