415016 A7 !____ B7 五、發明説明（/ ) 技術領域： 本發明係關於一種積體電路製程中製作平坦之淺渠溝隔 離（STI)的方法，特別是關於一種以高密度電漿化學氣相 沉積法（HDPCVD)沉積，再以化學機械研磨法（CMP) 進行平坦化處理之淺渠溝隔離（STI)的製作方法。 發明背景： 在VLSI及ULSI積體電路的製造技術中，完全嵌入的隔 離的使用，例如淺渠溝（sallow trench)技術已被用於次微 米製程中不平坦的表面問題上，以降低表面結構起伏的現 象。 下述方法爲一典型結構的形成： 1. 微影蝕刻出渠溝區域； 2. 利用介電材料使絕緣並填滿渠溝，典型的有氧化結構，例 如：二氧化矽； 3. 晶片表面平坦化處理。 ~ 積體電路製程中有許多已知的晶片平坦化的方法，例 如：利用塊狀電阻及電阻回蝕或塊狀電阻及旋塗式玻璃 (SOG)。其中化學機械研磨法（Chemical Mechanical Polishing; CMP)是一種大有可爲而且簡單的方法，CMP可 提供整片晶片的平坦化處理’而且不需額外的光罩或塗層步 驟，然而，一項渠溝之CMP平坦化的困難是寬渠溝（10μη〇 上會發生的”碟形凹陷”效應，其爲一種典型完全凹入的結 構。”碟形凹陷”的情形在大於2〇 μιη的渠溝中非常嚴重，而 因研磨形成的”碟形凹陷”效應只發生在寬渠溝中，很多研究 努力的嘗試直接修改研磨製程、設備及材料試圖降低和控制 本紙诔纽適财關家鮮（CMS ) A4ft#· ( 2ΐ0χψ公釐) " - 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明説明（>) 碟形凹陷的效應。 此外，發明家已發現窄渠溝中的凹陷問題，因爲研磨終 止層的缺乏，使基板凹陷效應更嚴重，導致研磨終點更不清 楚，而形成過度研磨的問題β 由相關專利或技術文獻發現，征服上述不同的缺點的重 要性已成爲技術開發直接的目標，可收集專利文獻中最接近 及較相關技術發展，如：美國專利第S362669號中揭露了一 種針對平坦化順著角度（conformal) _的隔離層的方法； 美國專利第5494857號中揭露一種STI CMP製程；美國專利 第5173439號中揭露一種STI CMP製程；美國專利第5242853 號中揭露一種ECRCVD SI1充填和平坦化的製程；美國專 利第5728621號中揭露一種利用HDP氧彳Μ形成STI，並利用 回蝕SOG的平坦化製程；美國專利第54441094號中揭露一種 利用自行對準複晶矽光罩的STI平坦化製程；美國專利第 5721172號中揭露另一種利用蝕刻的自行對準STI^程；以及 C.Y. Chang, S.M. Sze, in ULSI Technology, by The McGraw-Hill Company, INC. copyright 1997, pp. 422-423,介紹高密度電 漿化學氣相沉積（HDPCVD)氧化層製程》 發明之概述： 本發明之主要目的爲提供一種利用化學機械研磨 (CMP)處理製作非順著角度沉積的高密度電漿化學氣相 沉積（HDPCVD)淺渠溝隔離（STI)的方法。 本發明之另一目的爲提供一種平坦化剕頃著角度（non-conformal)沉積的HDPCVD ST1氧化層隔離區（包含窄渠溝 丨— ------装—：----訂------線 (請先閲I面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210>329·?公釐） 經濟部智慧財產局員工消費合作社印製 415016 A7 _ B7 五、發明説明（> ) 及寬渠溝）的方法，並避免窄渠溝及寬渠溝產生凹陷的現象。 本發明之又一目的爲提供一種利用覆蓋的氮化層爲研@ 終點，平坦化HDPCVD SI1氧化層隔離區的方法，氮化層研 磨終止於窄渠溝的中心位置，藉此爲窄STI渠溝及寬 的研磨終點。 爲了達到上述之各項目的，本發明提供一種平坦化非順 著角度沉積的HDPCVD STI氧化層隔離區（包含窄渠溝及寬 渠溝）的方法，利用覆蓋的第二氮化層爲研磨終止層’由於 HDPCVD氧化層的沉積，窄渠溝中心位置的第二氮化層研 磨終點與第一氮化層會在同一平面，所以第一氮化層及胃^ 氮化層皆爲窄STI渠溝及寬STI渠溝的研磨終點。 本發明利用低壓化學氣相沉積法（LPCVD)形成第> 氮化層於基板上，並定義基板形成窄渠溝及寬渠溝β接^胃 一個重要的步驟，即沉積HDPCVD氧化層填滿渠溝至基板 表面上約500 A，而填滿渠溝至基板表面上約500 Α對移除® 化層或再氧化反應很重要的步驟，幾百埃（Α)的厚度是必 要的，用來當作緩衝區以避免STI氧化層因矽基板表面的氧 化而失去；再接著，於所述HDPCVD氧化層上形成第二氣 化層，利用CMP向下研磨至第一氮化層及第二氮化層’然 後利用稀釋的氫氟酸（DHF)或緩衝氧化蝕刻液（BOE)触 刻移除第二氮化層·，最後，蝕刻移除第一氮化層。 本發明具有以下之關鍵點： 1. HDPCVD氧化層可充填窄渠溝及寬渠溝至基板表面上約 500A 〇 ! ------參--.----tr------線‘ (請先閲讀背面之注意事項再填寫本 本紙張尺度適用中國國家標準（CNS ) A4規格（2104 297公釐） Α7 Β7 五、發明説明（I) 2. 第一氮化層16與第二氮化層40之裸露面積大於乃％基板 面積時爲蝕刻終點，若大於85%基板面積更佳，如此可 避免渠溝中的凹陷現象，同時提供CMP設備一較佳的CMP 終止訊號以降低過度研磨的情形，DHF對PECVD第一氮 化層與對HDPCVD氧化層的濕蝕刻速率幾乎相同’故可 移除剩餘氧化層並保持好的圖形，如圖六所示。 3. LPCVD形成的第一氮化層及PECVD形成的第二氮化層， 其PE-氮化層與HDPCVD氧化層的CMP研磨速率比爲 2.5:1，而LP-氮化層與HDPCVD氧化層的研磨速率比爲 4:：1。 較高的CMP選擇比會有較好的圖形，然而，LPCVD氮 化層不同於PECVD氮化層，其與HDPCVD氧化層有幾乎相 當的DHF触刻速率，經DHF剝除之後的結構如圖六所示。 後續會描述本發明其他的內容及優點，由描述或實施例 可詳細瞭解本發明。 圖式簡要說明： 經由本發明實施例中之圖示說明將可更清楚的瞭解本發 明之特色和優點。 圖一爲本發明實施例中於半導體基板上形成一墊氧化層 及第一氮化層之剖面示意圖《 圓二爲本發明實施例中於基板上定義數個渠溝以形成主 動元件區之剖面示意圚。 圖三爲本發明實施例中形成一非順著角度沉積的 HDPCVD氧化層之剖面示意圖。 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X397公釐） (請先閲讀背面之注意事項再填寫本頁) -a 經濟部智慧財產局員工消費合作社印製 415016 A7 B7 五、發明説明（卜） 圖四爲本發明實施例中於HDPCVD氧化層上形成第二 氮化層之剖面示意圖。 圖五爲本發明實施例中第二氮化矽層及HDPCVD氧化 層經CMP研磨後之剖面示意圖。 圖六爲本發明實施例中蝕刻移除剩餘HDPCVD氧化層 及剩餘第二氮化層之剖面示意圖。 圖七爲本發明實施例中蝕刻移除第一氮化矽層16之剖面 示意圖。 圖八爲利用順角度沉積的淺渠溝隔離（STI)氧化層實 施本發明所形成較不佳的STI突起結構之剖面示意 圖。 I----------裝-- (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 訂 26_氧化層高出基板厚度 29-寬主動元件區上之氧化層厚度40-第二氮化層 發明詳細說明： 本發明實施例係利用高密度電漿化學氣相沉積法 (HDPCVD)及化學機械研磨法（CMP)製作淺渠溝隔離 圖號說明： 10-基板 12-窄的主動元件區 14-墊氧化層 20-窄渠溝 22-寬渠溝 24A-剩餘HDPCVD氧化層 24C-順著角度沉積的氧化層 11-寬的主動元件區 13-窄的主動元件區寬度 16·第一氮化層 21-渠溝深度 24- HDPCVD氧化層 24B-突起結構 24D-氧化層突起 28-窄主動兀件區上之氧化層摩 本紙张尺度適用中國國家標準（CNS ) A4规格（2丨0x697公嫠） 415016 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（b) (STI)區域’以下爲本實施例之詳細說明，請同時參閱圖 式以便瞭解本發明。 在後序的說明中會就流速、壓力值、厚度等數值加以界 定，幫助詳細的瞭解本發明具體實施的情形，熟知半導體技 藝之人士皆能明瞭，本發明並不侷限於該實施情形，因此， 在本發明之原則和範圍之下作細微上的改變皆應視爲本發明 之進一步實施狀況》 A.本發明具體實施之概觀 本發明之具體實施係包含下列步驟： 1. 提供一已开多成有一塾氧化層（pad oxide layer) 14及一第 一氮化層16的半導體基板10，並於所述基板10上定義數 個渠溝以形成主動元件區11,12，其中所述主動元件區係 包含窄的主動元件區Π及寬的主動元件區11，而所述渠 溝係包含窄渠溝20及寬渠溝22。 2. 此爲一重要步驟，即形成一非順著角度沉積的HDPCVD 氧化層24覆蓋在第一氮化層16上，並填滿渠溝20,22，所 述HDPCVD氧化層24於渠溝上之中心位置高於半導體基 板10表面，高出之厚度26介於300 A至700人之間》 3. 在HDPCVD氧化層24上，利用PECVD形成一第二氮化層 40 » 4. 利用CMP研磨第二氮化矽層40及HDPCVD氧化層24，並 以第一氮層16及第二氮化層40爲研磨終點’而經CMP 研磨之後，寬的主動元件區11上會留下一剩 氧化層24A。 (請先閲請背面之注意事項再填寫本頁) 裝- 訂 線 本紙張尺度適用中國國家標隼（CNS ) A4规格（210X397公釐) 經濟部智慧財產局員工消費合作社印製 415016 A7 B7 五、發明説明（^ ) a 5. 蝕刻移除寬的主動元件區11上之剩餘HDPCVD氧化層 24A及剩餘PECVD第二氮化層40。 6. 選擇性蝕刻並移除第一氮化矽層16，使填於渠溝中之 HDPCVD氧化層24與基板10同高。 根據本發明的積體電路製程方法，提供一P型<1〇〇>半 導體矽基板1〇，如圖一所示。所述基板10已形成有一墊氧化 層（pad oxide layer) Μ及第一氮化層16的基板，其中所述 墊氧化層14厚度係介於50人至250 Α之間。 Β.第一氮化層16 (LPCVDE化層） 利用LPCVD沉積第一氮化層16，所述LPCVD第一氮化 層16係由矽甲烷與氨於大氣壓下700°C至900°C間反應形成或 由二氯矽甲烷與氣於較低壓力下接近700°C時反應形成。所 述第一氮化層16厚度係介於1000 A至3000 A之間，而利用 CMP研磨氮化矽層與HDPCVD氧化層之研磨速率比係介於 3··1至5:1之間，最佳情形爲4:1。此外，利用稀釋的氫氟酸 (DHF )飩刻第一氮化層16的速率在蝕刻HDPCVD氧化層 速率的10%之內。 C.窄渠溝與寬渠溝 請參閱圖二，於所述基板1〇上定義數個渠溝以形成主動 元件區11,12，其中所述渠溝係包含窄渠溝20及寬渠溝22 ’ 而所述主動元件區係包含窄的主動元件區12及寬的主動元件 區11。可以利用習知的微影技術在基板上定義出渠溝隔離區 域，其中所述微影之步驟係包括光阻塗佈及形成光阻圖案’ 而陡直的渠溝20,22側壁是利用習知的非均向蝕刻方法蝕刻 ----------^--,----ΐτ------0 <請先閲讀背面之注$項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Α4规格（210XS97公釐） 415016 A7 B7____ 五、發明説明（？） 基板10形成。 所述窄渠溝20之寬度係介於0.05 μιη至0.35 μιη之間，而 所述寬渠溝22之寬度係介於0.4 μιη至20 μπι之間，其中較佳 之值係介於2 μιη至10 μπι之間。所述窄渠溝20及寬渠溝22的 深度21最好介於500 Α至3500 Α之間。所述窄的主動元件區12 之寬度13最好介於0.05 μιη至0.35 μπι之間，而所述寬的主動 元件區11之寬度最好大於2 μιη。 上述渠溝中可自由選擇是否形成一氧化薄層（圖中未畫 出），所述渠溝中之氧化薄層係利用LPCYD沉積，厚度介於 5〇 Α至500 Α之間"隨後進行HDPCVD氧化層24沉積時，所 述氧化薄層可以保護渠溝中之矽邊牆，此即爲形成上述之氧 化薄層的目的》 D·非順著角度沉漬之HDPCVDg化層24 請參閱圖三，形成一非順著角度沉積的HDPCVD氧化 層24覆蓋在第一氮化層16上並填滿渠溝20,22，所述HDPCVD 氧化層24於渠溝上之中心位置高於半導體基板10表面，高出 之厚度26介於300人至800 A之間。所述HDPC\T^>fb®24沉 積時，沉積與濺射之速率比係介於2.5:1至7:1之間。 所述HDPCVD氧化層24於寬的主動元件區11上之厚度29 係介於3300A至3700A之間，預期得到厚度爲3500A，而 HDPCVD氧化層24於窄的主動元件區Π上之厚度28係介於 300 A至800 A之間。 ---τ--.-----^-------1T------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局具工消費合作社印製 本發明之HDPCVD氧化層24形成# 1件如下： 製程過程中之參數 單位 低 HDPCVD 高 本紙張尺度逋用中國國家搮隼（CNS ) A4規格（210竽297公釐〉 經濟部智慧財產局員工消費合作社印製 415016 A7 __B7 五、發明説明（?） 氬氣（Ar) seem 20 90 160 氧氣（〇2)， seem 10 90 160 矽甲烷（SiHJ seem 5 55 120 壓力 mtorr 2 8 10 偏壓（biaspower) W 1500 2500 4000 側RF功率 W 1500 2600 4000 頂RF功率 W 500 1500 3000 沉積與濺射之速率比 2.8:1 5:1 7:1 本發明之發明人發現利用此條件得到之結果出乎意料的 好。 E. 非強制執行之再氧化反應 接著，可自由選擇是否進行再氧化反應，所述再氧反 應提供兩個功能：第一，再氧化反應爲HDPCVD製程步驟 之後的回火處理，第二，再氧化反應使HDPCVD氧化層在 熱與壓力下形成一如同熱氧化層的結構。 F. 第二氮化層40 請參閱圖四，在HDPCVD氧化層24上，利用PECVD形 成一第二氮化層40，並利用CMP研磨PE-氮化層與氧化層之 研磨速率比介於2:1至3:1之間，而當所述第一氮化層16與第 二氮化層40之裸露面積大於75%基板面積時爲蝕刻終點，若 大於85%基板面積更佳，最好大於90%基板面積。因爲本發 明中非順著角度沉積之HDPCVD氧化層24的形成，使得氮 化層16,40能有如此高的覆蓋面積，如圖五所示，第—氮化 層16與第二氮化層40爲蝕刻終點時可涵蓋大部份的基板1〇表 本紙張尺度逋用中國國家標準（CNS ) Α4ΪΪ格（210柏29"7公釐） ' ----------^1 —----tr------^ (請先閲讀背面之注意事項再填寫本頁) 五、發明説明 面。 利用PECVTD形成第二氮化矽層40，而非以LPCVD形成 第二氮化矽層40是很重要的，而如此選擇係爲本發明的關鍵 之一，這是因爲利用稀釋的氫氟酸（DHF)蝕刻PE-氮化層40 與HDPCVD氧化層24時，兩者的蝕刻速率幾乎相同。 G·化學機械研磨 請參閱圖五’利用CMP研磨第二氮化矽層40及HDPCVD 氧化層24，並以第一氮化層16及第二氮化層40爲研磨終點， 而經CMP研磨之後，寬的主動元件區11上會留下一剩餘 HDPCVD氧化層24A。圖五顯示在CMP之後，HDPCVD氧化 層24的突起結構24B。相較於順著角度沉積的氧化層，本發 明形成之非順著角度沉積的HDPCVD氧化層24可降低突起 結構24B的寬度，而這是本發明的一個主要優點。 H·非強制執行之再氧化反應 接著，可自由選擇是否進行再氧化反應，若進行砍基板 的再氧彳版應可移除缺陷層，所述再氧彳ΙΛ厚度係介於5〇 A 至250 A之間。 I.蝕刻第二氮化層40及HDPCVD®化層24 請參閱圖六，同時触刻移除寬的主動元件區11上的剩餘 HDPCVD氧化層24A及PECVD氮化層（第二氮化層）4〇 ’ 所述鈾刻係利用稀釋的氫氟酸（DHF)浸餓或利用緩衝氧化 蝕刻液（BOE)進行触刻’而且PECVD氮化層40與HDPCVD 氧化層24有相當的蝕刻速率（±10%之內）。所述蝕刻亦移 除第一氮化層16及第二氮化層40間的小突起24B ’而由於形 諳 先 閲 背415016 A7! ____ B7 V. INTRODUCTION (/) TECHNICAL FIELD: The present invention relates to a method for making flat shallow trench isolation (STI) in integrated circuit manufacturing processes, and particularly to a high-density plasma chemical vapor phase. Shallow trench isolation (STI) manufacturing method by HDPCVD and planarization by chemical mechanical polishing (CMP). Background of the Invention: In the manufacturing technology of VLSI and ULSI integrated circuits, the use of fully embedded isolation, such as shallow trench technology, has been used on uneven surface problems in sub-micron processes to reduce surface structure. Fluctuations. The following method is the formation of a typical structure: 1. Lithography etches the trench area; 2. Dielectric material is used to insulate and fill the trench, and typically has an oxidized structure, such as: silicon dioxide; 3. The surface of the wafer Flattening process. There are many known methods for wafer planarization in integrated circuit manufacturing processes, such as using block resistors and resist etch back or block resistors and spin-on-glass (SOG). Among them, Chemical Mechanical Polishing (CMP) is a promising and simple method. CMP can provide a planarization process for the entire wafer, and requires no additional photomask or coating steps. However, one The difficulty of CMP planarization of trenches is the "dish-shaped depression" effect that occurs on wide trenches (10 μη〇), which is a typical completely concave structure. The situation of "dish-shaped depressions" is in channels larger than 20 μηη The groove is very serious, and the "dish-shaped depression" effect formed by grinding only occurs in wide channels. Many research efforts have attempted to directly modify the grinding process, equipment and materials in an attempt to reduce and control the quality of the paper. CMS) A4ft # · (2ΐ0χψmm) "-Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (>) The effect of the dish-shaped depression. In addition, the inventors have found The depression problem is caused by the lack of the grinding stop layer, which makes the substrate depression effect more serious, leading to the uncertainty of the polishing end point, and the problem of excessive grinding is formed by the relevant patent or technical literature At present, the importance of conquering the above-mentioned different shortcomings has become the direct goal of technological development. The closest and more relevant technological developments in the patent literature can be collected. For example, U.S. Patent No. S362669 discloses a conformal angle of conformation (conformal ) _ Method of isolation layer; U.S. Patent No. 5,494,857 discloses a STI CMP process; U.S. Patent No. 5,173,439 discloses an STI CMP process; U.S. Patent No. 5,242,853 discloses an ECRCVD SI1 filling and planarization process; U.S.A. Patent No. 5786221 discloses a planarization process using HDP oxygen to form STI and etch back SOG; US Patent No. 54441094 discloses an STI planarization process using self-aligned polycrystalline silicon photomask; US patent No. 5211172 discloses another self-aligned STI process using etching; and CY Chang, SM Sze, in ULSI Technology, by The McGraw-Hill Company, INC. Copyright 1997, pp. 422-423, introducing high-density electrical Process of HDPCVD Oxidation Layer Summary of the Invention: The main purpose of the present invention is to provide a chemical Mechanical polishing (CMP) process for making high-density plasma chemical vapor deposition (HDPCVD) shallow trench isolation (STI) that is not deposited along an angle. Another object of the present invention is to provide a planarization angle ( Non-conformal) HDPCVD ST1 oxide isolation zone (including narrow trenches) —-------- install —: ---- order ------ line (please read the precautions on the I side before (Fill in this page) This paper size applies Chinese National Standard (CNS) A4 specifications (210 > 329 ·? Mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 415016 A7 _ B7 V. Description of the invention (>) and wide channel Ditch) method, and avoid the phenomenon of depressions in narrow trenches and wide trenches. Another object of the present invention is to provide a method for flattening the isolation region of HDPCVD SI1 oxide layer by using a covered nitride layer as a research endpoint. The grinding of the nitride layer ends at the center of a narrow trench, thereby narrowing the STI trench. Groove and wide grinding finish. In order to achieve the above-mentioned objects, the present invention provides a method for planarizing a HDPCVD STI oxide layer isolation region (including a narrow trench and a wide trench) that is not deposited at an angle, and uses a covered second nitride layer for polishing termination. Layer 'Due to the deposition of the HDPCVD oxide layer, the grinding end point of the second nitride layer at the center of the narrow trench and the first nitride layer will be on the same plane, so the first nitride layer and the stomach ^ nitride layers are narrow STI channels. Grinding ends for trenches and wide STI trenches. The present invention uses a low pressure chemical vapor deposition (LPCVD) method to form a > nitride layer on a substrate, and defines an important step for the substrate to form a narrow channel and a wide channel β, which is to deposit the HDPCVD oxide layer and fill it. The trench is about 500 A on the surface of the substrate, and filling the trench to about 500 A on the surface of the substrate is an important step for removing the formation layer or the reoxidation reaction. A thickness of several hundred angstroms (A) is necessary. As a buffer to prevent the STI oxide layer from being lost due to the oxidation of the surface of the silicon substrate; then, a second vaporization layer is formed on the HDPCVD oxide layer, and the first nitride layer and the second nitride layer are polished down by CMP The nitride layer is then removed by etching with dilute hydrofluoric acid (DHF) or buffered oxide etching solution (BOE). Finally, the first nitride layer is removed by etching. The present invention has the following key points: 1. The HDPCVD oxide layer can fill narrow trenches and wide trenches to about 500A on the surface of the substrate 〇! ------ 参 --.---- tr ----- -Line '(Please read the precautions on the back before filling in this paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2104 297 mm) A7 B7 V. Description of the invention (I) 2. The first nitride layer 16 and the first When the exposed area of the dinitride layer 40 is greater than or equal to the substrate area, the end point is etched. If the exposed area is greater than 85%, the substrate area is better. This can avoid sinking in the trenches and provide a better CMP termination signal to reduce In the case of excessive grinding, the wet etching rate of the first nitrided layer of PECVD by DHF and that of HDPCVD oxide layer is almost the same, so the remaining oxide layer can be removed and a good pattern can be maintained, as shown in Figure 6. A nitride layer and a second nitride layer formed by PECVD. The CMP polishing rate ratio between the PE-nitride layer and the HDPCVD oxide layer is 2.5: 1, and the polishing rate ratio between the LP-nitride layer and the HDPCVD oxide layer is 4 :: 1. Higher CMP select ratio will have better pattern, however, LPCVD nitride layer is different from PECVD This layer has a DHF etch rate almost equal to that of the HDPCVD oxide layer, and the structure after DHF stripping is shown in Figure 6. The other contents and advantages of the present invention will be described later, and the present invention can be understood in detail by description or example. Brief Description of the Drawings: The features and advantages of the present invention will be more clearly understood through the illustrations in the embodiments of the present invention. Fig. 1 shows an oxide layer and a first layer formed on a semiconductor substrate in an embodiment of the present invention. Sectional diagram of the nitride layer "Circle 2 is a cross-sectional diagram of defining several trenches on the substrate to form an active element region in the embodiment of the present invention. Figure 3 is a HDPCVD forming an off-angle deposition in the embodiment of the present invention. Schematic diagram of the cross section of the oxide layer. This paper size applies to the Chinese National Standard (CNS) M specifications (210X397 mm) (Please read the precautions on the back before filling out this page) -a Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 415016 A7 B7 V. Description of the invention (b) Figure 4 is a schematic cross-sectional view of forming a second nitride layer on the HDPCVD oxide layer in the embodiment of the present invention. A schematic cross-sectional view of the second silicon nitride layer and the HDPCVD oxide layer after CMP grinding in FIG. 6 is a schematic cross-sectional view of the remaining HDPCVD oxide layer and the remaining second nitride layer in the embodiment of the present invention. FIG. In the embodiment, the cross-sectional view of the first silicon nitride layer 16 is removed by etching. FIG. 8 is a cross-sectional view of a poorly formed STI protrusion structure formed by using a shallow trench isolation (STI) oxide layer deposited at an angle to implement the present invention. I ---------- Install-- (Please read the precautions on the back before filling out this page) Du Yin Formulation of Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 26_ Oxide layer is higher than substrate thickness 29-wide active The thickness of the oxide layer on the device area is 40-second nitride layer. Detailed description of the invention: The embodiment of the present invention uses high-density plasma chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) to make a shallow trench isolation map. Description: 10-substrate 12-narrow active device area 14-pad oxide layer 20-narrow trench 22-wide trench 24A-remaining HDPCVD oxide layer 24C-oxide layer deposited along an angle 11-wide active device area 13-Narrow active device region width Layer 21-trench depth 24-HDPCVD oxide layer 24B-protrusion structure 24D-oxide layer protrusion 28-oxide layer on the narrow active element area The paper size is applicable to Chinese National Standard (CNS) A4 specification (2 丨 0x697 cm) ) 415016 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of Invention (b) (STI) Area 'The following is a detailed description of this embodiment. Please also refer to the drawings to understand the invention. In the following description, the values of flow velocity, pressure value, and thickness will be defined to help understand the specific implementation of the present invention in detail. Those skilled in semiconductor technology will understand that the present invention is not limited to this implementation, so Minor changes under the principles and scope of the present invention should be regarded as further implementation of the present invention. A. Overview of the specific implementation of the present invention The specific implementation of the present invention includes the following steps: 1. Provide an opened A semiconductor substrate 10 having a pad oxide layer 14 and a first nitride layer 16 is formed. A plurality of trenches are defined on the substrate 10 to form active device regions 11 and 12. The element system includes a narrow active device region II and a wide active device region 11, and the trench system includes a narrow trench 20 and a wide trench 22. 2. This is an important step, that is, forming an HDPCVD oxide layer 24 that is not deposited at an angle to cover the first nitride layer 16 and fill the trenches 20, 22. The HDPCVD oxide layer 24 is formed on the trenches. The center position is higher than the surface of the semiconductor substrate 10, and the thickness 26 is between 300 A and 700 people. 3. On the HDPCVD oxide layer 24, a second nitride layer 40 is formed by PECVD »4. Using CMP polishing After the silicon nitride layer 40 and the HDPCVD oxide layer 24 are polished by CMP with the first nitrogen layer 16 and the second nitride layer 40 as the polishing end point, a residual oxide layer will be left on the wide active device region 11 24A. (Please read the notes on the back before filling in this page.) Binding-Binding paper size applies to China National Standard (CNS) A4 specification (210X397 mm). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 415016 A7 B7 Explanation of the invention (^) a 5. The remaining HDPCVD oxide layer 24A and the remaining PECVD second nitride layer 40 on the wide active device region 11 are removed by etching. 6. Selectively etch and remove the first silicon nitride layer 16 so that the HDPCVD oxide layer 24 filled in the trench is the same height as the substrate 10. According to the integrated circuit manufacturing method of the present invention, a P-type < 100 > semiconductor silicon substrate 10 is provided, as shown in FIG. The substrate 10 has a substrate with a pad oxide layer M and a first nitride layer 16, wherein the thickness of the pad oxide layer 14 is between 50 and 250 A. Β. The first nitrided layer 16 (LPCVDEized layer) The first nitrided layer 16 is deposited by LPCVD. The LPCVD first nitrided layer 16 is reacted between 700 ° C and 900 ° C of silicon methane and ammonia at atmospheric pressure. Formed or formed by the reaction of dichlorosilane and gas near 700 ° C at a lower pressure. The thickness of the first nitride layer 16 is between 1000 A and 3000 A, and the polishing rate ratio between CMP polishing of the silicon nitride layer and HDPCVD oxide layer is between 3 ·· 1 and 5: 1. The best case is 4: 1. In addition, the rate of etching the first nitride layer 16 with diluted hydrofluoric acid (DHF) is within 10% of the rate of etching the HDPCVD oxide layer. C. Narrow canal and wide canal Please refer to FIG. 2, a plurality of canals are defined on the substrate 10 to form active device regions 11 and 12, wherein the canal system includes a narrow canal 20 and a wide canal. 22 ′, and the active device region includes a narrow active device region 12 and a wide active device region 11. The trench isolation area can be defined on the substrate by the conventional lithography technology, wherein the steps of the lithography include photoresist coating and photoresist pattern formation. Known non-uniform etching method ---------- ^-, ---- ΐτ ------ 0 < Please read the note on the back before filling this page) The paper size applies the Chinese National Standard (CNS) A4 specification (210XS97 mm) 415016 A7 B7____ 5. Description of the invention (?) The substrate 10 is formed. The width of the narrow trench 20 is between 0.05 μm and 0.35 μm, and the width of the wide trench 22 is between 0.4 μm and 20 μm, and the preferred value is between 2 μm and 10 μm between. The depth 21 of the narrow trench 20 and the wide trench 22 is preferably between 500 A and 3500 A. The width 13 of the narrow active device region 12 is preferably between 0.05 μm and 0.35 μm, and the width of the wide active device region 11 is preferably greater than 2 μm. The above trenches are free to choose whether to form a thin oxide layer (not shown in the figure). The thin oxide layer in the trenches is deposited using LPCYD with a thickness between 50 and 500 Å. &Quot; When HDPCVD oxide layer 24 is deposited, the thin oxide layer can protect the silicon sidewalls in the trench. This is the purpose of forming the above-mentioned oxide thin layer. D · HDPCVDg layer 24 that is not deposited at an angle, please refer to the figure Third, an HDPCVD oxide layer 24 deposited at a non-slanted angle is formed to cover the first nitride layer 16 and fill the trenches 20 and 22, and the center position of the HDPCVD oxide layer 24 on the trench is higher than the surface of the semiconductor substrate 10. The thickness 26 is between 300 and 800 A. When HDPC \ T ^ > fb®24 is deposited, the rate ratio of deposition to sputtering is between 2.5: 1 to 7: 1. The thickness 29 of the HDPCVD oxide layer 24 on the wide active device region 11 is between 3300A and 3700A, and the thickness is expected to be 3500A. The thickness of the HDPCVD oxide layer 24 on the narrow active device region Π is 28. Between 300 A and 800 A. --- τ --.----- ^ ------- 1T ------ ^ (Please read the notes on the back before filling out this page) Intelligent Property Bureau, Industrial and Consumer Cooperatives, Ministry of Economic Affairs The HDPCVD oxide layer 24 formed by printing the present invention is formed in one piece as follows: The parameter unit during the manufacturing process is low HDPCVD high paper size, using China National Standard (CNS) A4 (210 竽 297 mm) Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 415016 A7 __B7 V. Description of the invention (?) Argon (Ar) seem 20 90 160 oxygen (〇2), seem 10 90 160 silicon methane (SiHJ seem 5 55 120 pressure mtorr 2 8 10 bias voltage ( biaspower) W 1500 2500 4000 side RF power W 1500 2600 4000 top RF power W 500 1500 3000 rate ratio of deposition and sputtering 2.8: 1 5: 1 7: 1 The inventors of the present invention found that the results obtained using this condition are beyond E. Non-enforced reoxidation reaction. Next, you can choose whether to carry out the reoxidation reaction. The reoxidation reaction provides two functions: First, the reoxidation reaction is the tempering treatment after the HDPCVD process step. Second, the reoxidation reaction makes the HDPCVD oxide layer under heat and pressure. A structure similar to a thermal oxide layer is formed. F. Second nitride layer 40 Please refer to FIG. 4. On the HDPCVD oxide layer 24, a second nitride layer 40 is formed by PECVD, and the PE-nitride layer is polished by CMP. The polishing rate ratio of the oxide layer is between 2: 1 and 3: 1. When the exposed area of the first nitride layer 16 and the second nitride layer 40 is greater than 75% of the substrate area, the etching end point is reached. 85% substrate area is better, it is better to be larger than 90% substrate area. Because the formation of HDPCVD oxide layer 24 not deposited at an angle in the present invention, the nitride layer 16,40 can have such a high coverage area, as shown in Figure 5. As shown, the first nitride layer 16 and the second nitride layer 40 can cover most of the substrate when the etching end point is 10. The paper size of the paper is in accordance with the Chinese National Standard (CNS) A4 grid (210K 29 " ^) '---------- ^ 1 —---- tr ------ ^ (Please read the notes on the back before filling out this page) 5. The description of the invention. Formed by PECVTD It is important to form the second silicon nitride layer 40 instead of forming the second silicon nitride layer 40 by LPCVD. Such selection is one of the key points of the present invention. When the diluted hydrofluoric acid (DHF) is used to etch the PE-nitride layer 40 and the HDPCVD oxide layer 24, the etch rate is almost the same. G · Chemical Mechanical Polishing Please refer to Figure 5 'Polishing the second silicon nitride layer 40 by CMP And HDPCVD oxide layer 24, with the first nitride layer 16 and the second nitride layer 40 as the polishing end point, and after CMP polishing, a remaining HDPCVD oxide layer 24A will be left on the wide active device region 11. Fig. 5 shows the protruding structure 24B of the HDPCVD oxide layer 24 after CMP. The non-angle-deposited HDPCVD oxide layer 24 formed by the present invention can reduce the width of the protruding structure 24B, which is a major advantage of the present invention, compared to the oxide layer deposited at an angle. H. Non-mandatory reoxidation reaction. Next, you can freely choose whether to carry out the reoxidation reaction. If the substrate is reoxygenated, the defect layer should be removed, and the thickness of the reoxygenated ΙΙΛ is between 50 and 50. Between 250 A. I. Etching the second nitride layer 40 and the HDPCVD® chemical layer 24 Please refer to FIG. 6, and simultaneously remove the remaining HDPCVD oxide layer 24A and the PECVD nitride layer (second nitride layer) on the wide active device region 11 by etching. 4 ′ The uranium engraving is performed by diluting with dilute hydrofluoric acid (DHF) or by using a buffered oxide etching solution (BOE). Moreover, the PECVD nitride layer 40 and the HDPCVD oxide layer 24 have comparable etching rates (± Within 10%). The etching also removes the small protrusions 24B 'between the first nitride layer 16 and the second nitride layer 40, and due to the shape,
I 經濟部智慧財產局員工消费合作社印製 本紙浪尺度適用中國國家標準（CNS ) A4规格（2丨0不]297公釐） 415016 A7 B7 經濟部智慧財產局員工消骨合作社印製 五、發明説明（f f ) 成非順著角度沉積的HDPCVD氧化層24的關係，所述小突 起24B乃爲一窄的突起，故可被蝕刻移除，若爲順著角度沉 積的STI氧化層則形成的突起較寬而且不可被完全的蝕刻 掉，會留下一不平坦的表面。 X触刻第一氮化層16 請參閱圖七，選擇触刻移除第一氮化層16，使充填渠溝 之HDPCVD氧化層24與基板10表面同高，所述第一氮化層16 係利用熱的磷酸（Hot Η3Ρ04 )進行蝕刻。 圖八係繪示若經由順著角度沉積的STI氧化層24C結構 會留有一寬的氧化層突起24D，以Η3Ρ04剝除氮化層之後， 形成氧化層突起24D形成一不平坦的表面，與本發明中形成 非順著角度沉積的HDPCVD氧化層24的結果不同，所以相 較於本發明，氧化層突起24D爲形成順著角度沉積的STI氧 化層24C的缺點。 K本發明之益處優點 本發明有下述之關鍵點： 1 ·非順著角度沉積的HDPCVD氧化層24可充填窄渠溝20及 寬渠溝22至基板10上約500A厚。 2.第一氮化層16及第二氮化層40之裸露面積大於75%基板 10面積時爲蝕刻終點，若大於85%基板10面積更佳。 3·利用PECVD形成的第二氮化層40，其PE-氮化層40與 HDPCVD氧化層24的CMP研磨速率比爲25:1，相較於LP-鐵化層（LPCVD)與HDPCVD氧化層24的研磨速率比4:1， PE-氮化層40與HDPCVD氧化層24有幾乎相當的蝕刻速 (請先聞讀背面之注意事項再填寫本頁) t. -a τ 良 本紙張尺度適用中國國家揉準（CNS ) Μ規格（公釐） 415016 A7 五、發明説明（（>) 率0 較高的CMP選擇比會有較好的圖形，因爲PE-氮化層的 濕蝕刻速率幾乎與HDPCVD氧化層相當，故作爲第二氮化 矽層40時PE-氮化層較LP-氣化層爲佳，這也是因爲高選擇 性的CMP法LP-氮化層（4:1)的蝕刻速率比高於PE-氮化層 (2.5:1)。 4.本發明中之非順著角度沉積的HDPCVD氧化層優於順著 角度沉積的氧化層結構。順著角度沉積的氧化層結構經 過Η3Ρ04剝除氮化層後會有較寬的突起形成，而本發明可 使突起減至最小。 必須要承認確認有許多刊物描述了一般的積體電路製程 技術，這些技術可以被應用在本發明的結構製作上，此外， 程序中的特殊步驟可以利用業界中可得的積體電路機械裝置 製作’本發明特殊之處來自於提供現今技術可作規範的製程 數值，本發明未來的發展性對熟知半導體技藝之人士皆能明 瞭。 上述說明係以較佳實施例來闡述本發明，而非限制本發 明，並且熟知半導體技藝之人士皆能明瞭，適當而作些微的 改變及調整，仍將不失本發明之要義所在，亦不脫離本發明 之精神和範圍。 本紙張尺度適用中國國家標率（CMS ) A4規格（210择97公釐） 0¾ (請先閲讀背面之注§項再填寫本頁) r 經濟部智慧財產局員工消費合作社印製I The paper printed by the Consumers ’Cooperative of the Ministry of Economic Affairs’ Intellectual Property Bureau applies the Chinese paper standard (CNS) A4 specifications (2 丨 0 not] 297 mm) 415016 A7 B7 Explanation (ff) The relationship of the HDPCVD oxide layer 24 deposited at an angle other than the angle. The small protrusion 24B is a narrow protrusion, so it can be removed by etching. If it is an STI oxide layer deposited at an angle, The protrusions are wide and cannot be completely etched away, leaving an uneven surface. X-etching the first nitride layer 16 Please refer to FIG. 7. Selecting the etching to remove the first nitride layer 16 makes the HDPCVD oxide layer 24 filling the trenches the same height as the surface of the substrate 10. Etching is performed using hot phosphoric acid (Hot 3P04). FIG. 8 shows that if the structure of the STI oxide layer 24C deposited through an angle is left with a wide oxide layer protrusion 24D, the oxide layer protrusion 24D is formed after the nitride layer is stripped with 3P04 to form an uneven surface. In the invention, the results of forming the HDPCVD oxide layer 24 deposited at different angles are different. Therefore, compared with the present invention, the oxide layer protrusion 24D has the disadvantage of forming the STI oxide layer 24C deposited at an angle. K. Benefits and Advantages of the Invention The present invention has the following key points: 1. HDPCVD oxide layer 24 deposited at an angle other than the narrow trench 20 and the wide trench 22 to the substrate 10 is about 500A thick. 2. The exposed area of the first nitride layer 16 and the second nitride layer 40 is greater than 75% of the substrate 10 area, which is the end point of the etching. If the exposed area is greater than 85% of the substrate 10 area, it is better. 3. The second nitride layer 40 formed by PECVD has a CMP polishing rate ratio of 25: 1 between PE-nitride layer 40 and HDPCVD oxide layer 24, compared with LP-ironized layer (LPCVD) and HDPCVD oxide layer. The polishing rate ratio of 24 is 4: 1. The PE-nitride layer 40 and the HDPCVD oxide layer 24 have almost the same etching rate (please read the precautions on the back before filling this page) t. -A τ Good paper size applies China National Standard (CNS) M specification (mm) 415016 A7 V. Description of the invention (>) A higher CMP selection ratio will have a better pattern, because the wet etching rate of the PE-nitride layer is almost It is equivalent to the HDPCVD oxide layer, so when the second silicon nitride layer 40 is used, the PE-nitride layer is better than the LP-gasification layer. This is also because of the high selectivity of the CMP method LP-nitride layer (4: 1). The etch rate ratio is higher than that of the PE-nitride layer (2.5: 1). 4. The HDPCVD oxide layer deposited at an angle other than in the present invention is superior to the oxide layer structure deposited at an angle. The oxide layer structure deposited at an angle After the 3P04 stripped of the nitrided layer, a wide protrusion is formed, and the present invention can minimize the protrusion. It must be acknowledged that there are many publication descriptions General integrated circuit manufacturing techniques. These techniques can be applied to the fabrication of the structure of the present invention. In addition, special steps in the program can be made using integrated circuit mechanical devices available in the industry. Today's technology can be used as a standard process value, and the future development of the present invention will be clear to those who are familiar with semiconductor technology. The above description is based on the preferred embodiment to illustrate the invention, but not to limit the invention, and those who are familiar with semiconductor technology. It can be understood that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention. This paper standard is applicable to the Chinese National Standard (CMS) A4 specification (210 to 97) Mm) 0¾ (Please read the note § on the back before filling out this page) r Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs