440997 五、發明說明（l) 本發明係有關於半導體元件製造。較特別地，本發明 係闕於在一個半導體元件中一種獲得狹窄的凹槽隔離之方 法。 為了在元件之間分佈操作電壓、操作電流、和訊號的 目的，半導體元件被製造具有表面的導體。而表面的導體 藉由一絕緣材料彼此絕緣。如果絕緣層被做得相關地厚， 電容的耦合效應將被減少。然而’最佳的絕緣效果是使絕 緣材料在表面上形成凹狀以及保持基板的表面平坦。所 以’利用蝕刻基板的表面形成凹槽隔離，並以諸如二氧化 石夕之絕緣材料填滿凹槽，已成為目前最新的隔離技術。 形成這些隔離結構的習知方法，即如所謂局部矽氧化 法（Local Oxidation of silicon，簡以L0C0S 稱之）。在 這個製程中’窗口被開在基板中，且使.用一氮化矽層當作 一罩幕，矽基板之選擇的區域被氧化。然而，局部矽氧化 法並不能符合0.25微来以下製程與設計的要求。在這小尺 寸’對於局部矽氧化法有些限制例如鳥嘴形成，絕緣層變 薄效應’平坦性不佳和應力引起的矽缺陷等。例如，絕緣 層變薄效應會減少元件的隔離效果。除此之外，鳥嘴長度 限制可以被獲得之最小的隔離寬度。 另一種形成隔離結構之習知方法，係為淺凹槽隔離 (Shallow Trench Isolation，簡以STI 稱之）者。然而， 用淺凹槽隔離同樣有限制。例如，使用淺凹槽隔離所形成 最小的隔離寬度為光學微影術（photolithography)設備之 解析度所限制。440997 V. Description of the invention (l) The present invention relates to the manufacture of semiconductor elements. More particularly, the present invention resides in a method for obtaining narrow groove isolation in a semiconductor device. For the purpose of distributing operating voltage, operating current, and signals between components, semiconductor components are manufactured with surface conductors. The surface conductors are insulated from each other by an insulating material. If the insulation is made relatively thick, the coupling effect of the capacitor will be reduced. However, the best insulation effect is to make the insulating material concave on the surface and keep the surface of the substrate flat. Therefore, the formation of groove isolation by etching the surface of the substrate, and filling the groove with an insulating material such as dioxide, has become the latest isolation technology. The conventional method for forming these isolation structures is the so-called Local Oxidation of Silicon (referred to as L0C0S). In this process, the 'window' is opened in the substrate and a silicon nitride layer is used as a mask, and a selected area of the silicon substrate is oxidized. However, the partial silicon oxidation method cannot meet the requirements of processes and designs below 0.25 micron. In this small size, there are some restrictions on the local silicon oxidation method such as bird's beak formation, thinning of the insulating layer effect, poor flatness, and silicon defects caused by stress. For example, the thinning effect of the insulating layer reduces the isolation effect of the component. In addition, the beak length limits the smallest isolation width that can be obtained. Another conventional method for forming an isolation structure is Shallow Trench Isolation (referred to as STI). However, isolation with shallow grooves is also limited. For example, the minimum isolation width formed using shallow groove isolation is limited by the resolution of photolithography equipment.
第5頁 4 4 0 9 9 7 五、發明說明（2) 因此，本發明目的之一 之缺點的方法。 本發明提供一種方法， 需的凹槽隔離結構。 一不旎被氧化之絕緣層 上。然後，在絕緣區的邊壁 石夕間隔物係藉經沈積一氮化 刻法飯刻而得。在矽基板之 —薄氧化層。其後，利用乾 氮化矽間隔物，因而決定出 層區之下的區域是擴散區， 區域形成一罩幕。然後，利 基板形成凹槽。再除去絕緣 被成長在石夕表面上以除去由 保護下層的矽。結果的凹槽 (Chemical Vapor Depositi 地，化學機械研磨法（Chemi Pol ishing/CMP)被應用來磨 作一研磨停止詹。 ’在於提供一種克服先前技術 可得到0. 2 5微米及以下製程所 ，係沈積並經成型在發 上形成氮化發間隔物。 矽層和以非等方向性氮 暴洛出的部份利用熱氧 式或濕式氮化發餘刻法 隔離區。在絕緣層區與 而留下的絕緣層區域與 用非等方向性的石夕银刻 層與氧化層。其次，一 矽凹槽蝕刻所引起的損 被以——厚的化學氣相沈 on/CVD)氧化層所填滿 cal Mechanical 平基板表面，且利用石夕 基板 此氮化 化矽蝕 化法長 ，除去 熱氧化 氧化層 法在石夕 氧化層 傷以及 積 •最後 基板當 為讓本發明之上述和其他目的、特徵、和優點能 顯易懂’下文特舉一較佳實施例，並配合所附圖式& 細說明如下： $ ’ # 圖式之簡單說明： 第1圖到第8圖係顯示用以形成根據本發明之實施例之Page 5 4 4 0 9 9 7 V. Description of the invention (2) Therefore, one of the disadvantages of the object of the present invention is the method. The invention provides a method for a required groove isolation structure. Not oxidized on the insulating layer. Then, the Shi Xi spacer on the side wall of the insulation area is obtained by depositing a nitriding method. On the silicon substrate-a thin oxide layer. Thereafter, a dry silicon nitride spacer was used, and it was determined that the area below the layer area was a diffusion area, and the area formed a mask. Then, the substrate is formed into a groove. The insulation is then removed and grown on the surface of Shi Xi to remove the underlying silicon. The resulting groove (Chemical Vapor Depositi, Chemical Mechanical Polishing (Chemi Pol ishing / CMP) is used to grind as a polishing stop.) 'The purpose is to provide a process that overcomes the previous technology to obtain 0.2 5 microns and below, It is deposited and shaped on the hair to form nitrided hair spacers. The silicon layer and the portion exposed by non-isotropic nitrogen bursts are separated by thermal oxygen or wet nitrided epitaxial method. In the insulating layer The remaining insulating layer area is etched with a non-isotropic lithography layer and oxide layer. Second, the damage caused by the etching of a silicon groove is oxidized with a thick chemical vapor deposition on / CVD). The layer fills the surface of the cal Mechanical flat substrate, and the silicon nitride substrate is etched by the nitrided silicon etch method to remove the thermal oxidation and oxidation layer method to damage and accumulate the oxide layer in the stone. Other objects, features, and advantages can be clearly understood. 'A preferred embodiment is given below, and the detailed description in conjunction with the attached drawings & is as follows: $' # Brief description of the drawings: Figures 1 to 8 Display to form according to the invention Examples of
第6頁 440997 五、發明說明（3) 狹窄凹槽隔離的製程。 符號說明： 1 0〜矽基板；1 2〜絕緣閘極；1 4〜氮化矽間隔物；1 5 ~凹 槽/隔離區；1 6〜氧化層；1 8〜氧化層。 實施例： 用以形成本發明的一實施例的製程被顯示在第1圖到 第8圖中。起始點是一片石夕基板。一絕緣層（它不能被氧 化）’例如二氧化矽（si02) ’被沈積至厚度大概地300ηπ1 在梦基板1 0上，再利用光學微影術與蝕刻製程形成了絕緣 閘極12 ’如顯示在第}圖中。在第二圖中，氮化矽以“叱） 間隔物14被形成在絕緣閘極12的邊壁上。這步驟係藉由先 沈積一，度約為2〇〇〇nm之氮化矽層後，施行例如一非等 方向性氮化矽蝕刻法，以獲致所欲之間隔物1 4。 外尾ή用熱氧化法成長一氧化層1 6於矽基板1 0上。氧 ★個度約為5〇nm，它是較小於絕緣閘極12的高度。 您個步驟顯示在第3圓中。 物14其2法：用乾式或濕式氮化矽蝕刻法除去氮化矽間隔 物14，而決定出隔離區15。注 ’间隔 化層16之下的區域是擴散 疋在絕緣閘極12和熱氧 隔物14之門S 2 因為在氧化層16和氮化矽間 m…刻選擇性，故氮化…物η可2 地被去除，而不影響到氧化、 易 -個具有高的氮化石夕蝕刻選擇性。也被選擇為 去，導致絕緣閘極12和氧化層 虱化矽間隔物14的除 被顯示在第4圖中。 4形成—罩幕。結果的罩幕 I. 4 4 0 9 9 7 , 五、發明說明（4) 然後，應用一非等方向性矽蝕刻，蝕刻矽基板1 0，而 絕緣閘極1 2和氧化層1 6被當做一硬罩幕，供在石夕基板1 〇钱 刻中形成凹槽15時做為罩幕之用，即如第5圖所示。然 後’除去由絕緣閘極1 2和氧化層1 6所組成硬罩幕，即如第 6圖所示。其後’一熱氧化層（未圖示）被成長在矽基板1〇 上’以除去由矽蝕刻所引起的損傷與保護下層的矽。 在第7圖中所示，用化學氣相沈積法（CVD)沈積厚度約 為0.4 ym之一氧化層18。化學氣相沈積法氧化層18完全地 填滿在ί夕基板1 0中的凹槽。然後，施行化學機械研磨法 (CMP)磨平基板表面，而以石夕基板1〇做為研磨停止層。化 學機械研磨法研磨的結果是狹窄的凹槽隔雕形成在梦基板 中’如顯示在第8圖中。凹槽的寬度被決定於氮化石夕間隔 物的寬度。使用以上所描述發明的方法，一個〇1#m或 更小的凹槽寬度可以被獲得。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作更動與潤飾，因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。 §Page 6 440997 V. Description of the invention (3) Narrow groove isolation process. Explanation of symbols: 10 to silicon substrate; 12 to insulated gate; 14 to silicon nitride spacer; 15 to groove / isolation region; 16 to oxide layer; 18 to oxide layer. Example: The process used to form an example of the present invention is shown in Figures 1 to 8. The starting point is a piece of Shixi substrate. An insulating layer (it cannot be oxidized) 'such as silicon dioxide (si02)' is deposited to a thickness of approximately 300ηπ1 on the dream substrate 10, and then an optical gate 12 and an etching process are used to form an insulating gate 12 'as shown In picture}. In the second figure, silicon nitride is formed on the side wall of the insulating gate 12 with "叱" spacers 14. This step is performed by first depositing a silicon nitride layer having a degree of about 2000 nm. Then, for example, a non-isotropic silicon nitride etching method is performed to obtain the desired spacer 14. The thermal oxidation method is used to grow an oxide layer 16 on the silicon substrate 10. Oxygen It is 50nm, which is smaller than the height of the insulating gate 12. Your step is shown in the third circle. Object 2 and 2 methods: removing silicon nitride spacers 14 by dry or wet silicon nitride etching The isolation region 15 is determined. Note: The area under the spacer 16 is diffused, and is located at the gate S 2 of the insulating gate 12 and the thermal oxygen spacer 14. Because the oxide layer 16 and the silicon nitride are m ... Therefore, the nitride η can be removed without affecting the oxidation, and it has a high etching selectivity of nitride. It is also selected to go, which causes the insulating gate 12 and the oxide layer to siliconize. The division of the spacer 14 is shown in Fig. 4. 4 forms-the mask. The resulting mask I. 4 4 0 9 9 7 V. Description of the invention (4) Then, apply a NOT Directional silicon etching, etching the silicon substrate 10, and the insulating gate 12 and the oxide layer 16 are used as a hard mask for the formation of the recess 15 in the stone etch of the substrate 10 That is, as shown in Figure 5. Then 'remove the hard mask consisting of the insulating gate 12 and the oxide layer 16, as shown in Figure 6. Thereafter,' a thermal oxide layer (not shown) is removed. Grow on a silicon substrate 10 'to remove damage caused by silicon etching and protect the underlying silicon. As shown in Figure 7, an oxide layer with a thickness of about 0.4 μm is deposited by chemical vapor deposition (CVD). 18. The chemical vapor deposition method oxide layer 18 completely fills the grooves in the substrate 10. Then, a chemical mechanical polishing (CMP) method is used to smooth the substrate surface, and the stone substrate 10 is used as a polishing Stop layer. As a result of CMP grinding, narrow grooves are formed in the dream substrate 'as shown in Figure 8. The width of the groove is determined by the width of the nitride spacer. Use the above description With the inventive method, a groove width of 0 # m or less can be obtained. Although the present invention has been The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be attached as follows. The ones defined in the scope of patent application shall prevail.