Α7 Β7 經濟部中央標準局貝工消費合作社印製 五、發明説明（l ) 〔發明所靥之技術部門〕 本發明乃關於半導體記憶裝置者。 〔以往之技術〕 從以往，乃有使用NAND型格（Ce 1 1 )或 NOR型格之罩式ROM ( masked R 〇 Μ )爲一般所知 。通常在罩式ROM，乃將位元線電位略爲預充電（precharge) 至一定電位， 此檢出被選擇之記憶格按資料成爲 ON或OFF所引起電流引入（iead in)之有無。在進行 此資料檢出之讀出放大器初段，乃使用負反饋型之放大器 ，故不必使位元線電位從預充電電位作太大之變動，即可 檢出例如10 Omv程度之信號振幅 。 〔本發明擬解決之問題〕 惟在以往之罩式ROM之資料讀出方式，由於爲將數 元線之微小振幅之類比放大器來檢出，放耐噪音性極差。 例如，由於多數之輸出緩衝器同時開關而所發生之所謂同 時開關噪音，極容易發生誤動作。並且，臏出放大器初段 由於爲免位元線電位有大變化，乃一面使其作負及饋動作 一面進行信號檢出，故输入讀出放大器後段之差動放大器 之信號之上升邊（leadi n edge)較遲；此將進一步成爲 謀求高速化之障礙。 本發明乃有鑑於上述情形所提出者，其目的乃在提供 :可提高其耐噪音性及高速性能之半導體記億裝置者* (請先閱讀背面之注意事項再填寫本頁) t -§ Γ 本紙張尺度適用中國國家棣準（CNS ) Λ4規格（2丨0 X 297公釐） -4 — A7 A7 經濟部中央標準局負工消費合作社印製 B7 五、發明説明（2 ) 〔解決上述問題之方法〕 本發明之半導體記憶裝置，乃備有：複數之局部數 元線；及被配設成與此局部位元線交叉之複數支之字元線 ;及被配置在此等字元線與前述局部位元線之各交叉部而 各寫入有規定之資料，並由前述字元線被選擇性地驅動之 記憶格等，並且有：前述各記憶格之基準端子被連接於第 1基準電位之第1記憶塊；及形成與前述第1記憶塊對稱 之模式（pattern)，而有各個複數支之局部位元線與字 元線，以及複數之記憶格被佈置（layout);在各記憶格 亦有與第1記憶塊內相對應之住址之記憶格之資料相反之 資料被寫入，且基準端子亦被連接在與前述第1基準電位 不同之第2基準電位之第2記憶塊；及同時選擇前述第1 、第2之記憶塊內之相對應之位址之記憶格，將此被選擇 之兩個記億格之輸出端子各經由被選擇之局部位元線連接 於一個輸出位元線之選擇機構；及由此選擇機構被選擇之 兩個記憶格亦被串聯連接在前述第1:第2之基準電位之 間，而進行一方成爲ON，另一方成爲OFF之互補性動 作，由此來檢出前述輸出位元線之電位變化之差動型謓出 機構；等爲特徵者。 在本發明中，最好乃爲：前述第1 、第2之記憶塊之 各記憶格，乃由各不同之字元線所驅動之複數之MO S電 晶體串聯連接所構成；此等MO S電晶體亦爲前述字元線 在非選擇狀態時成爲ON之NAND型格，前述選擇機構 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 (請先閲讀背而之注意事項再填寫本頁) •裝·Α7 Β7 Printed by Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (l) [Technical Department of the Institute of Invention] The present invention relates to semiconductor memory devices. [Conventional Technology] From the past, a masked ROM (masked R 〇 Μ) using NAND type (Ce 1 1) or NOR type is generally known. Normally, in the mask ROM, the bit line potential is precharged to a certain potential. This detects the presence or absence of current induced by the selected memory cell according to whether the data becomes ON or OFF. In the early stage of the sense amplifier for this data detection, a negative feedback type amplifier is used, so it is possible to detect, for example, a signal amplitude of about 10 Omv without making the bit line potential change too much from the precharge potential. [Problems to be Solved by the Invention] However, in the conventional data readout method of the mask ROM, since the analog amplitude amplifier of the minute amplitude of the digital line is detected, the noise resistance is extremely poor. For example, the so-called simultaneous switching noise that occurs when most output buffers switch at the same time is extremely prone to malfunction. In addition, in order to prevent the bit line potential from changing greatly at the first stage of the amplifier, the signal detection is performed while making it negative and feeding, so the rising edge of the signal of the differential amplifier input to the latter stage of the sense amplifier (leadi n edge); this will further become an obstacle to speeding up. The present invention is proposed in view of the above circumstances, and its purpose is to provide: a semiconductor billion device that can improve its noise resistance and high-speed performance * (please read the precautions on the back before filling this page) t -§ Γ This paper scale is applicable to China National Standards (CNS) Λ4 specification (2 丨 0 X 297 mm) -4 — A7 A7 Printed B7 by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description (2) [Solve the above problems Method] The semiconductor memory device of the present invention includes: a plurality of local number lines; and a plurality of word lines arranged to intersect the local bit line; and the word lines arranged on these lines Each of the intersections with the local bit lines is written with predetermined data, and memory cells, etc., which are selectively driven by the word lines, and the reference terminals of the memory cells are connected to the first The first memory block of the reference potential; and the formation of a pattern symmetrical to the aforementioned first memory block (pattern), and the local bit lines and character lines of each complex branch, and the complex memory grids are arranged (layout); Each memory cell also has the first The opposite data of the memory cell of the corresponding address in the memory block is written, and the reference terminal is also connected to the second memory block of the second reference potential different from the aforementioned first reference potential; 2. The memory cell of the corresponding address in the second memory block connects the selected two output terminals of 100 million cells to the selection mechanism of an output bit line through the selected local bit line; And the two memory cells selected by the selection mechanism are also connected in series between the aforementioned first and second reference potentials, and the complementary action that one becomes ON and the other becomes OFF, thereby detecting the aforementioned Differential type output mechanism for output bit line potential change; etc. In the present invention, it is preferable that: the memory cells of the first and second memory blocks are composed of a plurality of MOS transistors connected in series driven by different character lines; these MOS Transistor is also the NAND type that the character line turns ON when the character line is not selected. The paper size of the aforementioned selection agency is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions before reading Fill in this page)
、1T -5 - A7 B7 經濟部中央梯準局MK；工消費合作社印製 五、發明説明（3 ) 則具有：選擇前述第1'第2之記憶塊內相對應之 N A N D型格群，將此被選擇之N A N D型格群之輸出端 子’經由各被選擇之前記局部位元線，同時連接於前述輸 出位元線之記憶格選擇機構；及同時選擇與前述第1 、第 2之記憶塊相對應之字元線之字元線選擇機構等；而前述 輸出位元線亦在前述字元線選擇機構所作字元線選擇之確 定前，經由前述第1、第2之記憶塊內之被選擇之 NAND型格，被預充電成前述第1、第2之基準電位之 中間電位，等爲特徵者。 依據此發明，乃準備有在同位址同時被選擇之相對應 之一對記憶格中寫入有相反之資料之第1、第2之記憶塊 :而第1記憶塊之記憶格之基準端子乃被設定在第1基準 電位（例如接地電位），第2記憶塊之記億格之基準端子 則被連接在與前述第1基準電位不同之第2基準電位（例 如電線電位）。因此，由某位址輸入來讀出資料時，與第 1 '第2之記憶塊相對應之記憶格，乃一方爲ON而另一 方則爲0 F F。此等記憶格將被串聯連接在電源電位與接 地電位之間，而進行與CMO S同樣之互補性動作。由此 ，此等記憶格經由局部位元線被連結之輸出位元線，將變 化至電源電位或接地電位。爲此，使用差動讀出放大器， 在不致受到同時開關噪音等之影響之下，進行確實之資料 讀出（data sense )將成爲可能。並且，與使用放大微小 振幅之負及饋放大器之以往方式比較，高速之讀出（sense) 將成爲 可能。 (，請先閲讀背而之注f項再填寫本頁) 裝. -δ 铢 本紙张尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） -6 - 糾2433 A7 經濟部中央標準局貝工消费合作社印製 ____B7_五、發明説明（4 ) 在此發明之理想之實施形態中，作爲第1 、第2之記 億塊之記憶格，將使用在字元線非選擇時所有之記憶電晶 體將ON之NAND型格群。並且，記億格選擇機構及字 元線選擇機構，將被構造成對由某位址被指定之兩個 N A N D型格群經由被選擇之局部位元線被連接在輸出位 元線之定時（timing)，字元線選擇之確定定時將延遲 之構成。依據此種形態，在字元線選擇之確定前，第1記 憶塊側之接地端子及第2記憶塊之電源端子，乃經由各爲 〇 N狀態之N A N D型格群及選擇位元線被連接在輸出位 元線，而輸位元線則自動地被預充電成電源電位之中間電 位。由此種字元線確定以前之過渡狀態下之自動預充電機 能，將不必設置特別之均衡電路，即可使高速且確實之讀 出（sense)動作成爲可能。 〔發明之實施形態〕 下面參照附圖來說明本發明之實施例。 圊1乃表示：本發明之一實施例之4M數元罩式 ROM (2048列* 1 28行* 1 6數元並聯）之區塊 電路圖。記憶格陣列1 3含有：具有同位址之第1記憶塊 1 a及第2記憶塊1 b。記憶格陣列之驅動電路則具有： 提取（fetch)外部位址之位址緩衝器2，及將被提取之 位址加以解碼以進行字元線選擇之列解碼器3 ，及將被提 取之位址加以解碼以進行位元線選擇之行解碼器4，以及 行選擇電路5 a 、5b，及讀出被選擇之位元線資料之差 本紙張尺度適用中國國家橾準（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意，事項再填寫本頁) -裝· •-° -7 - 30C483 A7 B7 經濟部中央橾準局員工消费合作社印製 五、發明説曰/ ( 5 ) 1 1 動 型 讀 出 放 大 電 路 6 及 輸 出 電 路 7 等 〇 丨 第 1 第 2 之 記 憶 塊 1 a ' 1 b 乃 如 後 述 在 相 對 應 1 I 之 同 一 位 址 寫 入 有 互 爲 相 反 之 資 料 〇 可 謂 互 爲 相 反 乃 指 ; 請 1 1 | 對 0 爲 1 對 1 爲 0 之 關 係 亦 即 互 爲 相 反 之 關 係 〇 列 編 先 閱 讀 1 1 I 碼 器 3 行 解 碼 器 4 及 行 選 擇 器 5 a 、 5 b 乃 同 時 選 擇 背 之 1 1 並 讀 出 兩 個 記 憶 塊 1 a 、 1 b 之 同 位 址 之 資 料 〇 注 意 1 1 事 I t 圖 2 乃 表 示 第 1 、 第 2 之 記 憶 塊 1 a 、 1 b 行 選 項 再： I 填 1 ά. 1 擇 電 路 5 a 5 b 及 讀 出 放 大 電 路 6 之 部 分 之 具 體 構 成 例 本 百 者 0 記 憶 塊 1 a 1 b 乃 各 向 橫 方 向 被 分 割 成 1 6 個 之 行 1 1 I 塊 C B 0 C B 1 5 各 行 塊 C B 0 C B 1 5 亦 各 向 縱 1 1 方 向 被 割 成 6 4 個 之 列 塊 R B 0 R B 6 3 〇 記 憶 塊 1 a 1 及 記 憶 fj+j 塊 1 b 關 於 其 上 下 方 向 1 亦 互 相 被 佈 置 成 對 稱 性 訂 1 之 模 式 ( pa 11 e r η ) C 第1記憶塊] L a內之記憶格之基準 1 I 端 子 乃 被 連 接 在 作 爲 第 1 基 準 電 位 之 接 地 電 位 V S 8 第 1 I 2 記 憶 塊 1 b 內 之 記 憶 格 之 基 準 端 子 則 被 連 接 在 作 爲 第 2 1 •〆 基 準 電 位 之 電 線 電 位 V D D 〇 其 評 細 情 形 將 後 述 〇 1 行 選 擇 電 路 5 a > 5 b 亦 與 1 6 個 之 行 塊 C B 0 1 1 C Β 1 5 相 對 應 含 有 1 6 個 之 行 選 擇 器 C S 0 C S 1 1 1 5 〇 讀 出 放 大 電 路 6 亦 同 樣 由 1 6 個 之 讀 出 放 大 器 1 | S A 0 S A 1 5 所 構 成 〇 I 圖 3 乃 將 圖 2 之 1 個 行 塊 C B 0 進 一 步 加 以 分 解 後 表 1 1 1 示 者 〇 如 圖 所 示 在 1 個 行 塊 C B 0 乃 配 設 有 資 料 讀 出 1 1 用 之 6 4 支 之 局 部 位 元 線 B L 0 B L 6 3 及 與 其 交 叉 1 1 之 記 憶 格 選 擇 用 之 2 0 4 8 支 之 字 元 線 W L 0 1 1 準 標 冢 國 國 Τ 度 尺 張 紙 Μ 公 7 9 2 A7 B7 經濟部中央標隼局員工消费合作社印製 五、發明説明（ 6 ) 1 1 W L 2 0 4 7 以 及 將 各 1 6 個 之 記 憶 格 加 以 彙 集 之 1 1 N A N D 型 格 群 選 擇 用 之 2 5 6 支 之 選 擇 閘 線 S L 0 1 | S L 2 5 5 〇 沿 各 局 部 位 元 線 B L 乃 有 每 1 列 塊 R B 兩 if 1 先 1 段 之 N A Ν D 型 格 群 Μ C 各 被 配 置 在 左 右 而 在 行 塊 C B 閱 讀 1 I 內 則 在 1 局 部 位 元 線 Β L 有 N A N D 型 格 群 Μ C 被 設 置 背 而 之 1 1 成 各 2 隊 列 ( queue ) 共1 2 8段 >由挾持v S s線之 注 意 事 1 1 每 上 下 2 段 之 N A N D 型 格 Μ C 乃 構 成 6 4 個 之 列 塊 項： 再 填 1 I R B 0 R B 6 3 〇 各 字 元 線 W L 乃 爲 選 擇 1 個 Ν A N D 寫 本 頁 .裝 | 型 格 群 Μ C 由 之 1 個 記 億 器 Μ 0 S 電 晶 體 所 用 者 而 選 擇 1 I 閘 線 S L 則 進 行 列 塊 R Β 之 選 擇 及 挟 持 各 列 塊 R B 內 1 1 I 之 局 部 位 元 線 B L 在 左 右 鄰 接 之 兩 個 N A N D 型 格 群 Μ C 1 1 之 群 訂 選 擇 以 及 挾 持 V S S 在 上 下 鄰 接 之 兩 個 N A Ν D 型 格 1 Μ C 之 選 擇 等 所 用 者 〇 1 1 圖 4 乃 將 圖 3 之 一 個 列 Xcfcl 塊 R B 0 之 -· 部 分 更 詳 細 地 加 1 1 以 表 示 者 0 N A N D 型 格 群 Μ C 乃 各 如 圖 4 所 示 由 與 1 一 1 I 局 部 位 元 線 B L 交 叉 配 置 之 字 元 線 W L 來 驅 動 閘 而 被 1 6 段 串 聯 連 接 之 η 通 道 Μ 0 S 電 晶 體 ( 記 億 格 ) Μ 0 Μ 1 1 1 5 Μ 1 6 Μ 3 1 … … … 等 所 構 成 〇 字 元 線 W L 0 1 1 W L 2 0 4 7 乃 每 按 各 Ν A N D 型 格 群 Μ C 被 各 配 設 1 1 1 6 支 0 Ν A Ν D 型 格 群 之 基 準 端 子 在 此 第 1 記 憶 Xtfa 塊 1 1 1 a 乃 全 被 連 接 在 接 地 電 位 V S S 〇 在 列 塊 內 上 下 之 1 I Ν A N D 型 格 群 Μ C 乃 共 有 V S S 線 並 挾 持 V S S 線 以 對 稱 1 I 性 模 式 ( pa t t e r η ) 被配置。 1 1 I 與 各 N A Ν D 型 格 群 Μ C 之 基 準 端 子 相 反 側 之 輸 出 端 1 1 本紙張尺度適用中國國家標準（CNS ) Λ4说格（2丨0X 297公釐） -9 - 經濟部中央梂準局貝工消費合作社印製 A7 一__B7_ 五、發明説明（7 ) 子，乃經由以控制閘線S L來驅動閘之2段之選擇閘 MOS 電晶體（S11、S21) 、( S 1 2 ' S 2 2 ) 、(S 3 1 ' S 4 1 ) 、( S 3 2 ' S 4 2 ).........等， 而被連接在局部位元線B L »此等選擇閘MO S電晶體， 則由對於自橫方挪列之N A N D型格群M C爲共用之選擇 阐 SLO、SL1 、SL2、SL3 ..........等形驅動。 由挾持局部位元線B L而鄰接之記憶格μ C之同樣之選擇 閘線S L所驅動之選擇閘MO S電晶體，一方乃爲增加型 (enhancement type) (Ε型），另一方則爲減低型（ depletion type) (D型）（閘部附以斜線來表示）。將 E型及D型之選擇閘加以串聯連接，由此，可選擇左右任 何一方之N A N D型記憶格群，均將成爲可能。 將第2記億塊1 b與圖3相對應，就一個行塊C B 0 加以表示，則將成爲圖5所示者。以與第1記憶塊1 a在 上下方向方面對稱之相反模式（pattern) ，N AND型 格MC將被佈置。並且，在第2記憶塊lb，NAND型 格M C群之基準端子，將被連接在第2基準電位之電線電 位 V 。 在第1 、第2之記憶塊la、lb，將由罩式程式 (mask program)，在互爲相對應之位址之記憶Μ 0 S電 晶體，固定地被寫入互爲相反之資料。其資料模式（dat-a pattern)將模式性地表示於圖6。圖中圓圈所示記億 器電晶體之空圓圈，乃爲E型（例如資料)，有斜 線者則爲D型（資料* 0 ");在第1 '第2之記億塊 本紙張尺度適用中國國家梂準（CNS ) Λ4規格（210X297公釐> -in - (請先閱讀背而之注$項再填寫本頁) •裝- *νβ 302483 A7 B7 經濟部中央#準局負工消費合作社印製 五、發明説明（8 ) la 、lb之同一位址，寫入有相反之資料。然後，如後 述，第1 、第2之記憶塊la、lb，乃被同時選擇相對 應之字元線及位元線，而互爲讀出相反之資料· 在本實施例中，表示於圖3. 5之選擇閘線SLO〜 SL255,乃爲非選擇狀態而全爲^1^ :此時所有之 NAND型格群MC，乃從局部位元線BL被切離。由圖 1所示行解碼器4，在各記憶塊1 a、lb，相對應之一 個選擇閘線S L將同時被選擇，而成爲'。例如，在 圖4中，SLO = 時，各局部位元線BL之左上之 NAND型格將被連接在局部位元線B L ;而S L 1 = 時，則各局部位元線BL之右上側之NAND型格 將被連接在局部位元線BL。同樣地，SL2 = 時 ，各局部位元線B L之左下之NAND型格將被連接在局 部位元線BL，而SL3 = 時，各局部位元線BL 之右下之NAND型格亦將被連接在局部位元線BL。 字元線WLO〜WL2047，在非選擇狀態乃全部 爲。此，在非選擇狀態，記憶MOS電晶體將不管 資料如何均爲ON狀態。由圖1所示列解碼器3 ，在記憶 塊1 a 、1 b相對應之一個字元線WL將被選擇，同時成 爲'。並且，局部位元線BL亦由行解碼器4及行選 擇器5 a 、5b ，仍在記憶塊la 、lb，從各行塊CB 一支一支逐支同時被選擇1 6支，而此等亦經由輸出位元 線被連接在讀出放大電路6。 圖7乃爲選擇上述選擇閘線SL、字元線WL以及局 (锖先閱讀背而之注意事項#填窩本頁) -裝. 訂 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） -11 - A7 B7 趣涛部中央榡準局負工消費合作杜印製 一’ 五、發明説明 丨（9 ) 1 I 部 位 元 線 Β L 等 之 列 解 碼 器 3 及 行 解 碼 器 4 之 具 體 例 子 〇 1 罩 式 R 0 Μ 乃 爲 例 如 4 Μ 數 元 ( 1 6 數 元 並 聯 輸 出 ) : 而 1 1 I 在 位 址 A 0 A 7 之 中 之 A 0 A 6 將 進 行 行 選 擇 在 請 1 1 A 7 A 1 7 則 進 行 列 選 擇 0 列 解 碼 器 3 及 行 解 碼 器 4 > kj 閱 ik 1 1 如 前 述 在 第 1 、 第 2 之 記 憶 塊 1 a 1 b 乃 被 共 用 e 背 面 之 1 1 列 解 碼 器 3 乃 在 第 1 段 配 設 有 將 選 擇 1 6 段 意 1 事 1 N A N D 型 格 群 Μ C 之 中 之 一 個 電 晶 體 US. 所 用 之 位 址 A 7 項 再 1 1 裝 I A 1 0 加 以 解 碼 之 解 碼 器 R D 1 ( 輸 出 乃 爲 1 6 支 ) 及 本 將 選 擇 6 4 個 之 列 塊 R Β 〇 R B 6 3 所 用 之 下 位 位 址 1 1 | A 1 2 A 1 4 及 上 位 位 址 A 1 5 A 1 7 各 加 以 解 碼 之 1 I 解 碼 器 R D 2 ( 輸 出 爲 8 支 ) 及 R D 3 ( 輸 出 爲 8 支 ) « > 1 第 2 段 則 因 有 解 碼 器 R D 2 、 R D 3 之 輸 出 被 輸 入 而 爲 訂 1 選 擇 6 4 個 之 列 塊 R B 0 R B 6 3 之 一 個 乃 配 置 有 解 碼 1 1 器 R D 4 ( 輸 出 爲 6 4 支 ) ; 在 第 3 段 則 配 設 有 爲 選 擇 1 1 2 0 4 8 支 之 字 元 線 之 . 個 所 用 之 解 碼 器 R D 1 R D 4 · 線 之 輸 出 以 及 位 址 A 1 1 將 被 輸 入 之 解 碼 器 R D 5 ( 輸 出 1 1 爲 2 0 4 8 支 ) 0 1 1 解 碼 器 R D 1 乃 由 檢 出 A 7 A 1 0 之 1 6 個 之 組 1 1 合 所 用 之 反 相 器 群 及 全 同 檢 出 ( id en t i ty d e t e c t ) 用之 1 1 N A N D 閘 群 ( 或 A N D 閘 群 ) 所 構 成 « 解 碼 器 R D 2 | R D 3 亦 被 同 樣 構 成 0 解 碼 器 R 0 4 則 由 進 行 R D 2 1 I R D 3 之 各 8 支 輸 出 之 全 同 檢 出 之 6 4 個 之 N A N D 閘 群 1 1 I ( 或 A Ν D 閘 群 ) 所 構 成 0 並 且 > A 1 1 亦 爲 進 行 各 列 塊 1 1 內 之 上 下 之 N A Ν D 型 格 群 之 選 擇 亦 即 選 擇 挾 持 圖 3 之 1 1 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） ~ 12 - 經濟部中央標準局貝工消費合作社印製 A7 __ B7五、發明説明（10 ) V ss線或圖5之V DD線在上下鄰接之NAND型格群之任 何一個所用者；解碼器RD 5亦由；爲檢出解碼器RD 1 之1 6支之輸出及RD 4之6支之輸出之及A 1 1之組合 所用之反相器群，及NAND閘群（或AND閘群）所構 成。解碼器RD5之2048支之輸出在選擇狀態下，一 個將成爲。此解碼器RD 5之輸出，乃經由反相器 形式之字元線驅動器WD被供給至字元線WL Ο〜 WL 2 0 4 7，並在選擇$態下，一支字元線將成爲 # . 行解碼器4，乃具有：爲進行局部位元線選擇，將位 址A1 、A2加以解碼之解碼器CD1 (輸出爲4支）， 及將A3〜A6加以解碼之解碼器CD2 (輸出爲16支 )。此等解碼器CD1 、CD2之輸出將被送至行選擇器 5 a 、5 b β 行選擇器5a 、5b乃如圖8所示，由：將位址A1 、A 2加以解碼之解碼器CD 1之4支之輸出，及將位址 A 3〜A 6加以解碼之解碼器CD 2之1 6支之輸出等各 被控制之2段之行閘Q21、Q22以及Qll、Q12 等所構成》由此行選擇器5a、5b，各在第1 、第2之 記憶塊1 a 、lb ，將從行塊CB內之6 4支之局部數元 線B LO〜B L 6 3被選擇1支，而被連接在輸位元線B β由此，從各記憶塊1 a、1 b被選擇之局部位元線（全 體有16支），將經由輸出位元線B被連接在差動型讀出 放大器S A。在差動型讀出放大器S A之基準輸出端子， 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閱靖背而之注意事項再填窍本頁) -裝- *va 線 一 13 - 經濟部中央標準局貝工消费合作社印製 A7 ________ΒΊ___ 五、發明説明（11 ) 將被供給基準電壓VREF = V DD/ 2。 並且，行解碼器4爲選擇2 5 6支之選擇閘線S L之 中之一個，乃具有解碼器R04之輸出，及AO、A 1 1 將被輸入之解碼器CD3。在此，最下位位址A〇乃爲決 定選擇沿局部位元線B L之左右2隊列之NAND型格群 之任何一個所使用者。更具體言，乃爲決定究竟選擇：選 擇閘線（SL0、SL2 ..........)之組及（SL1 、 S L 3..........）之組之任何一個所使用者。位址A 1 1 乃與列解碼器3側同樣，爲決定選擇挾持圖3之V ss線或 圖5之V DD線之上下之NAND 型格群之任何一個所使 用者。具體言，以列塊R Β Ο來看，乃爲決定選擇：選擇 閘線（SL0、SL1)之組及（SL2、SL3)之組 之任何一組所使用者。解碼器CD3 ，乃將以上邏輯由反 相器群及全同檢出用之NAND閘群（或AND閘群）來 加以組入，由此使其在選擇狀態下使2 5 6支之輸出之1 個成爲•此解碼器CD3之輸出，將經由非及轉（ non-inverting)之選擇閘驅動器S D被供給至2 5 6支 之選擇閘線SL1〜SL256，在非選擇狀態下使選擇 閘線SL1〜SL256成爲，而在選擇狀態下將 使1支選擇閘線成爲'"Η"。 下面說明此種構成之NAND型罩式ROM之資料讀 出動作。如前述，字元線WL在非選擇狀態下乃全爲* Η 歸，而選擇閘線S L則在非選擇狀態下全爲' L 〃 ：故字 元線選擇之確定定時與選擇閘線選擇之確定定時將發生分 本紙張尺度適用中國國家標準（CNS > Λ4規格（210Χ297公釐） ' -14 - (請先閱讀背面之注意事項再填将本頁) -裝. Μ •經濟部中央梯準局負工消費合作社印製 3GC483 A7 B7 _ 五、發明説明（12 ) 岐（不吻合）。此分岐將具有重要之意義；惟首先如無視 此分岐，先來說明其基本動作。當位址資料被輸入’則將 由列解碼器3選擇一支字元線。例如，先著眼於圖3 ，假 定列塊RBO將被選擇，其中之字元線WLO〜WL15 之一支亦被選擇。此時，由行解碼器4，選擇閘線S L 〇 'SL1之任何一方將成爲，選擇閘線SL2、 SL3將均成爲。字元線WL1 6〜WL3 1側之 一支字元線被選擇時，SL2、SL3之一方將成爲 "，而成爲SL0 = SL1=。在記憶塊lb亦同 樣。由此，各記憶塊1 a 、lb之一個列塊之沿各局部位 元線B L之6 4個之NAND型格群將被選擇而被連接在 局部位元線。並且，由行解碼器4，在各記憶塊1 a、1 b ’從各行塊CB將有各1支共16支之局部位元線被選 擇並被連接在輸出位元線B。 具體言，假定與第1 、第2之記憶塊la 、lb相對 應之字元線W L 〇及.局部位元線B L 〇將同時被選擇，及 各記憶電晶體M0亦被選擇。則在NAND型ROM，因 使選擇字元線成爲，由此，將檢出被選擇之記億電 晶體是否爲E型抑或D型。 圖9 ( a ) ( b )乃爲被選擇之資料之讀出動作例子 。如圖9 ( a )所示，假定第1記憶塊1 3側之記億塊 1 b側之記憶電晶體Μ Ο爲E型，亦即爲資料，i，，則 與第2記億塊1 b側相對應之記憶電晶體！^〇乃爲ρ型。 此等資料將同時經由局部位元線B L 0被轉送至一個輸出 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） ' -- (請先閱讀背而之注意事項再填寫本頁) •裝. 訂 線 -15 - A7 B7 五、發明説明（13 ) 位元線B。此時，在輸出位元線B，乃如圖9 ( a )所示 ’第1記憶塊1 a側之E型之記憶電晶體M0及第2記憶 塊1 b側之D型之記憶電晶體M0，將從串聯連接在電源 V 與接地Vss間。然後，因選擇字元線WL 0將爲 ，，V DD側記憶電晶體MO將成爲ON，V ss側記憶電晶 體MO則將成爲Ο F F ;故將流動箭頭所示之充電電流’ 輸出位元線B則將上昇至電源電位VDD。 若資料爲相反，則如圖9 ( b )所示，V DD側記憶電 晶體M0將成OFF，V ss側記憶電晶體MO則成爲Ο N ，故將流動箭頭所示之電流，而輸出位元線B將降低至接 地電位V SS。 如上述，在本實施例，由於將被進行··二個記憶塊 1 a 、1 b所選擇之記億電晶體所示之互補性動作；放將 輸出位元線B之電位，由將VRE F = V DD/ 2作爲參照 (基準）電位來使用之差動型讀出放大器SA來加以檢出 ，則將可作資料> 1 ^ 之判定。 因此，依據此實施例，乃與以微小振幅之信號來進行 資料讀出（data sense)之以往方式不同，而將可進行不 容易受到同時開關噪音或外部噪音之影響，且無誤動作之 穗定之資料讀出。而且，輸出位元線B亦可提昇大振幅至 V DD或Vss，並將此以差動型讀出放大器來檢出；故與使 用負及饋放大器來進行微小信號檢出之方式比較，髙速動 作將成爲可能· 在此實施例之情形，由於如前述，在字元線選擇之確 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） (請先閱讀背而之注意事項再填寫本頁) .裝 -St 線 -經濟部中央梯準局員工消費合作社印製 -16 - -經濟部中央標隼局貝工消费合作社印製 30Z4Q3 A1 B7五、發明説明（14 ) 定及選擇閘線選擇之確定之定時（timing)將發生分岐（ 不吻合），故將自動地進行輸出位元線B之預充電（precharge) 。 將此 預充電動作’ 參照圖 1 〇 來說明 。圖 1 〇 乃爲表示：被選擇之字元線WL及被選擇之選擇閘線S L 之電位變化，以及輸出位元線B之電位變化者》在時刻 t 〇位址被閂鎖（latch)，在時刻t 1由行解碼器4及 行選擇器5 a 、5b，將進行局部位元線選擇。局部位元 線選擇乃如圖7所示，由行解碼器4之1段之解碼器CD 1 、CD2及行選擇器5a 、5b所進行；故比字元線及 選擇閘線之選擇確定較快，而在時刻t 1被選擇之局部位 元線BL乃被連接在輸出位元線B。 字元線選擇及選擇閘選擇，在圖7之解碼器構成中乃 均由3段之解碼器所進行；故其時刻假定爲t 2。從此時 刻t2，如圖1〇所示，被選擇之字元線WL乃從 開始遷移至，而被選擇之選擇閘線SL乃從 開始遷移至。以選擇閘MOS電晶體爲首。E型 MOS電晶體之閥值V t h，通常乃較V DD/ 2爲小，而 從設定在0· 7V左右，因此，對選擇閘線SL上昇至 V t h而選擇閘MOS電晶體成爲ON之時刻t3 (選擇 閘線SL之選擇確定定時），字元線WL降低至Vth之 時刻t 4(字元線WL之選擇確定定時）將延遲》 此時刻t 3至t 4爲止之延遲時間t 1乃成爲預充電期 間。亦即，在此延遲時間t α之間，被選擇之兩之個 NAND型格群之輸出端子，將經由已經ON之選擇閘 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 裝· I I訂— I I I —線 (請先閱讀背面之注意事項再填寫本頁) ， -17 - 經濟部中央標準局貝工消費合作社印製 A7 ___B7_五、發明説明（15 ) MO S電晶體，亦經由局部位元線B L，被連接在輸出數 元線B。在此期間，此等兩個NAND型格群之所有記憶 電晶體將仍然全被保持在ON狀態（非選擇狀態）。由此 ，第1記億塊1 a之接地電位Vss，及第2記憶塊1 b之 電源電位VDD，將經由輸出位元線B被短路，並將由前循 環之讀出資料維持著或而成爲浮動（floating) 之輸出 位元線 B ， 預充電成 V DD/ 2 。 此後 ，在時 刻14，字元線選擇將確定，被選擇之兩個NAND型格 群內之一方之記憶電晶體將成爲OFF，而由前述之互補 性動作，輸出位元線將遷移至V DD或V ss。 如上述，在字元線確定之前，自動地，輸出位元線及 局部位元線將被預充電至V DD/ 2;由此，將可進行高速 而確實之資料讀出。 圖1 1乃表示列解碼器3之其他之構成例者。此乃爲 將圖7之解碼器作成RD 5 1〜RD 5 2之兩段構成，而 將列解碼器3整體作成兩段構成者。若行解碼器與先前之 實施例一樣，則與行解碼器比較，於列解碼器之延遲將趨 大。結果，如圔1 2所示，將可獲得：列選擇之確定將較 行選擇延遲t 2之定時（timing)關係》因此，在此延遲 時間t 2之間，與先前之實施例相同，將可進行輸出數元 B之預充電。 上面已說明NAND型罩式ROM之實施例’惟同樣 之技術概念亦可適用於NOR型罩式ROM。圖1 3乃表 示本發明之其他實施例之N 0 R型罩式R 0M之要部構成 本紙張尺度適用中國國家標準（CNS ) Λ4規格（21〇><297公釐） I I I I I I 裝— I 1 I I 訂 I I I I * 絲 (請先閲讀背而之注意事項再填寫本頁) ， 一 18 _ 經濟部中央標隼局負工消費合作社印製 A 7 B7五、發明説明（16 ) 者。其亦設有：由列解碼器及行解碼器來共同進行位址選 擇之第1記憶塊1 a、第2記憶塊1 b »在NOR型格群 MC，乃於相對應之位址寫入有相反資料成爲：能記憶在 第1 、第2之記憶塊1 a、1 b之間反轉（inverting) 之資料模式之狀態。並且，在第1記億塊la、記憶格基 準端子將被設定在Vss，而在第2記憶塊1 b、記憶格基 準端子則將被設定在V DD。 在NOR型罩式MOM之情形，字元線WL乃在非選 擇狀態下成爲t L # (例如V ss )，在選擇狀態則成爲^ （例如VDD5。並且，格群之二進資料（binary data )將作爲字元線之·•位準之間之第1閾值狀 態，及較位準爲髙之第2閾值狀態之任何一方來加 以記憶。資料讀出，乃由檢出被選擇之記憶格按資料成爲 ON、OFF所作之電流引入之有無來進行。因此，將第 1，第2之記憶塊la、lb之相對應之位址之格，同時 加以選擇並連接於輸出位元線，則與先前之實施例同樣之 互補性動作所作之資料讀出將成爲可能。 本發明將不限於上述實施例、亦可適用於各種 PROM、EPROM 等。 〔發明之效果〕 如上所述，在本發明之半導體記憶裝置，由於準備有 寫入及轉模式（invert pattern)之資料之第1 、第2之 記億塊，並將各記憶塊之基準端子設定在互爲不同之第1 I ·1 I I I I I I I 裝— I H —訂— -^ I 線 (請先閲讀背而之注意事項再填寫本頁) · 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210 X 297公釐） -19 - A7 B7 經濟部中央標準局員工消费合作社印製 i、發明説明（17 ) 、第2之基準電位，來進行此等記憶塊之互補性動作所作 資料讀出；故由此，將可謀求耐噪音性及高速性能之提升 〇 〔附圖之簡單說明〕 〔圖1〕 表示本發明之一實施例之罩式ROM之塊 構成者β 〔圖2〕 表示該實施例之記憶塊已具體構成者。 〔圖3〕 表示第1記憶塊之一部分之詳細構成者。 〔圖4〕 表示圖3之電路之一部分之進一步詳細構 成者。 〔圖5〕 表示與圖3相對應已第2記憶塊之詳細構 成者。 〔圖6〕 表示該實施例之資料模式例者· 〔圖7〕 表示該實施例之解碼器已構成者。 〔圖8〕 表示該實施例之行選擇器已構成者。 〔圖9 (a) (b)〕 表示該實施例之資料讀出動 作者。 〔圖1 0〕 說明該實施例之預充電動作所用之圖。 〔圖1 1〕 表示該實施例之列解碼器構成者。 〔圖1 2〕 表示該實施例之動作定時者。 〔圖13〕 表示其他實施例之罩式ROM之要部構 成者， 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝. ,ar 镍 -20 - A7 B7 五、發明説明（18 ) [附圖內編號之說明〕 la .........第1記憶塊 2 4 6 位址緩衝器， 行解碼器， 5 a 差動讀出放大電路 lb 3 5 b 7 第2記憶塊 列解碼器， 行選擇電路 輸出電路。 (請先閱讀背面之注意事項再填寫本頁) .裝. 、va 叙 經濟部中央標準局員工消費合作社印裂 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） -21， 1T -5-A7 B7 Central Bureau of Economic Development MK; printed by the Industrial and Consumer Cooperatives. 5. Description of invention (3) It has: select the corresponding NAND type cluster in the first 1 'second memory block, The output terminals of the selected NAND cell group are connected to the memory cell selection mechanism of the output bit line through the selected local bit lines before being selected; and simultaneously select the first and second memory blocks The word line selection mechanism of the corresponding word line, etc .; and the output bit line is passed through the memory blocks in the first and second memory blocks before the determination of the word line selection by the word line selection mechanism The selected NAND cell is precharged to the intermediate potential of the first and second reference potentials, etc., which are characteristic. According to this invention, it is prepared to write the first and second memory blocks with the opposite data in the corresponding one of the corresponding pairs selected at the same address at the same time: and the reference terminal of the memory cell of the first memory block is It is set at the first reference potential (for example, ground potential), and the reference terminal of the second memory block is connected to a second reference potential (for example, wire potential) that is different from the first reference potential. Therefore, when reading data from an address input, the memory cell corresponding to the 1st, 2nd memory block is one on and the other on 0 F F. These memory cells will be connected in series between the power supply potential and the ground potential, and perform the same complementary actions as CMOS. Thus, the output bit lines to which these memory cells are connected via the local bit lines will change to the power supply potential or the ground potential. For this reason, it is possible to use a differential sense amplifier to perform a reliable data sense without being affected by simultaneous switching noise or the like. In addition, compared with the conventional method using a negative feed amplifier that amplifies a small amplitude, a high-speed sense will be possible. (Please read item f on the back of this page before filling in this page) Pack. -Δ Baht This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) -6-D 2433 A7 Central Standards Bureau of the Ministry of Economic Affairs Printed by the industrial and consumer cooperative ____B7_V. Description of the invention (4) In the ideal embodiment of this invention, as the memory cells of the 1st and 2nd billionth memory blocks, all of them will be used when the character line is not selected. The memory transistor will turn on the NAND type lattice group. In addition, the gigabyte selection mechanism and the word line selection mechanism will be constructed to connect the two NAND-type lattice groups designated by a certain address to the output bit line at the timing via the selected local bit line ( timing), the determined timing of the word line selection will be delayed. According to this form, before the determination of the word line selection, the ground terminal on the first memory block side and the power supply terminal on the second memory block are connected via the NAND cell group and the selected bit line which are in the ON state On the output bit line, the input bit line is automatically precharged to the middle potential of the power supply potential. This kind of character line determines the automatic pre-charging function in the previous transition state, and it is possible to make high-speed and reliable sense operation without setting a special equalizing circuit. [Embodiment of the invention] An embodiment of the present invention will be described below with reference to the drawings. Bit 1 is a block circuit diagram of a 4M digital mask ROM (2048 columns * 1 28 lines * 16 digital parallel) according to an embodiment of the present invention. The memory cell array 13 includes: a first memory block 1 a and a second memory block 1 b with the same address. The driving circuit of the memory cell array has: an address buffer 2 that fetches external addresses, and a column decoder 3 that decodes the extracted addresses for word line selection, and the bits to be extracted The row decoder 4 to decode the address for bit line selection, as well as the row selection circuits 5a, 5b, and read the difference between the selected bit line data. The paper size is applicable to China National Standard (CNS) Λ4 specifications ( 210X 297mm) (please read the notes on the back and fill in this page) -Installed • •-° -7-30C483 A7 B7 Printed by the Central Consumer ’s Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative V. The invention says / (5 ) 1 1 Dynamic readout amplifier circuit 6 and output circuit 7 etc. The first and second memory blocks 1 a ′ 1 b are written with the opposite data at the same address corresponding to 1 I as described later. It can be said that they are opposite to each other; please 1 1 | for 0 to 1 to 1 to 0 is also the relationship with each other. Column coding first read 1 1 I encoder 3 row decoder 4 The row selectors 5 a and 5 b simultaneously select the back 1 1 and read the data at the same address of the two memory blocks 1 a and 1 b. Note 1 1 matter I t Figure 2 shows the first and second memories Block 1 a, 1 b line options: I fill in 1 ά. 1 selection circuit 5 a 5 b and read out the amplification circuit 6 part of the specific configuration example of the original one 0 memory block 1 a 1 b is laterally Divided into 16 rows 1 1 I block CB 0 CB 1 5 Each row block CB 0 CB 1 5 is also divided into 6 4 column blocks RB 0 RB 6 3 〇 Memory block 1 a 1 And memory fj + j block 1 b with respect to its up and down directions 1 are also arranged in a symmetrical 1 mode (pa 11 er η) C 1st memory block] the reference of the memory cell in L a 1 I terminal is connected The ground potential VS 8 as the first reference potential is the reference terminal of the memory cell in the first I 2 memory block 1 b Connected to the wire potential VDD as the second 1 • 〆 reference potential. The evaluation will be described later. 1 Row selection circuit 5 a & 5 b also corresponds to 16 row blocks CB 0 1 1 C Β 1 5 Contains 16 row selectors CS 0 CS 1 1 1 5 〇 The sense amplifier circuit 6 is also composed of 16 sense amplifiers 1 | SA 0 SA 1 5 〇I Figure 3 is shown in Figure 2 1 After the row block CB 0 is further decomposed, the table 1 1 1 is shown. As shown in the figure, one row block CB 0 is equipped with 6 4 local bit lines BL 0 BL 6 for data reading 1 1 3 and the cross 1 1 memory grid for selection 2 0 4 8 Zigzag line WL 0 1 1 Standard mark Tsukukuni country T ruler sheet paper M public 7 9 2 A7 B7 Central Ministry of Economic Affairs Staff consumption Printed by the cooperative. 5. Description of the invention (6) 1 1 WL 2 0 4 7 and add 16 memory cells each 2 5 6 selection gate lines SL 0 1 | SL 2 5 5 ○ used for selection of the aggregated 1 1 NAND grid group. There are two if 1 NAs per first row block RB along each local bit line BL N D type lattice groups M C are each arranged on the left and right, and in the row block CB read 1 I, there is a local bit line B L in the NAND type lattice group M C is set to the contrary 1 1 into 2 each queue (queue ) A total of 1 2 8 segments > Notes on holding the v S s line 1 1 Each of the upper and lower 2 segments of the NAND grid M C is composed of 6 4 block items: fill in 1 IRB 0 RB 6 3 〇 Element line WL is for selecting 1 Ν AND to write this page. Install | Type group mc Choose from one megameter Μ 0 S transistor 1 I gate line SL to select the block R Β And holding the group selection of the two NAND type lattice groups mc 1 1 of the 1 1 I local bit line BL in each column block RB adjacent to the left and right Select and hold VSS in the selection of two NA ND patterns 1 M C adjacent to each other above and below. ○ 1 1 Figure 4 is a row of Figure 3 where the Xcfcl block RB 0 is added by 1 1 in more detail. The denominator 0 NAND lattice groups M C are each n-channel Μ 0 S connected in series by 16 segments driven by a word line WL arranged as a cross with 1-1 I local bit line BL as shown in FIG. 4. Transistor (100 million grids) Μ 0 Μ 1 1 1 1 5 Μ 1 6 Μ 3 1…… etc. constitute the 〇 word line WL 0 1 1 WL 2 0 4 7 is according to each N AND type lattice group mc 1 1 1 6 sets of reference terminals of 0 Ν Α Ν D type group are allocated here. The first memory Xtfa block 1 1 1 a is all connected to the ground potential VSS 〇 1 I Ν AND above and below the column block The pattern group MC is shared with the VSS line and is held in a symmetrical 1 I sex mode (pa tter η) by holding the VSS line. 1 1 I Output end opposite to the reference terminal of each NA ND grid group mc 1 1 The paper size is applicable to the Chinese National Standard (CNS) Λ4 said grid (2 丨 0X 297mm) -9-The Ministry of Economic Affairs Printed by the quasi-bureau Beigong Consumer Cooperatives A7 _B7_ V. Description of invention (7) The MOS transistors (S11, S21), (S 1, S21) and (S 1 2 'S 2 2), (S 3 1' S 4 1), (S 3 2 'S 4 2) ... etc., but connected to the local bit line BL »These choices The gate MOS transistors are driven by SLO, SL1, SL2, SL3, etc. for the common selection of the NAND-type lattice group MC shifted from the horizontal direction. The selection gate MOS transistor driven by the same selection gate line SL holding the local bit line BL and the adjacent memory cell μC, one side is an enhancement type (E type) and the other side is a reduction Type (depletion type) (D type) (the gate is indicated by a slash). By connecting the selection gates of the E type and D type in series, it is possible to select either of the left and right N A N D type memory cell groups. Corresponding to the second billion block 1 b and FIG. 3, and expressing one row block C B 0, it will become the one shown in FIG. 5. In the opposite pattern symmetrical to the first memory block 1 a in the up-down direction, the N AND pattern MC will be arranged. In addition, in the second memory block lb, the reference terminal of the NAND type MC group is connected to the wire potential V of the second reference potential. In the first and second memory blocks la and lb, a mask program (memory M 0 S transistors at the corresponding addresses) is fixedly written with mutually opposite data. The data pattern (dat-a pattern) is shown schematically in FIG. 6. The empty circles of the transistors with billions of dollars shown in the figure are E-type (for example, data), and those with slashes are D-type (data * 0 "); in the 1st, 2nd, 100 million pieces of paper The standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm> -in-(please read the back-note $ item and then fill in this page) • Installed-* νβ 302483 A7 B7 Central Ministry of Economics # quasi-bureau negative Printed by the industrial and consumer cooperatives. 5. Description of invention (8) The same addresses of la and lb are written with the opposite information. Then, as will be described later, the memory blocks la and lb of the first and second are selected at the same time. The word line and bit line, and the opposite data is read from each other. In this embodiment, the selection gate lines SLO ~ SL255 shown in Figure 3.5 are in the non-selected state and are all ^ 1 ^: At this time, all the NAND cell groups MC are cut away from the local bit line BL. By the row decoder 4 shown in FIG. 1, at each memory block 1 a, lb, the corresponding one of the selection gate lines SL will be simultaneously Is selected and becomes'. For example, in Fig. 4, when SLO =, the upper left NAND grid of each local bit line BL will be connected to the local bit line BL; and SL 1 = when , Then the NAND pattern on the upper right side of each local bit line BL will be connected to the local bit line BL. Similarly, when SL2 =, the lower left NAND pattern of each local bit line BL will be connected to the local bit line BL, and SL3 =, the lower right NAND grid of each local bit line BL will also be connected to the local bit line BL. The word lines WLO ~ WL2047 are all in the non-selected state. State, the memory MOS transistor will be in the ON state regardless of the data. By the column decoder 3 shown in FIG. 1, a word line WL corresponding to the memory blocks 1 a and 1 b will be selected and become '. , The local bit line BL is also selected by row decoder 4 and row selectors 5a, 5b, still in memory blocks la, lb, one by one from each row block CB, and 16 at the same time, and so on It is connected to the sense amplifier circuit 6 through the output bit line. Figure 7 is to select the above-mentioned selection gate line SL, word line WL and bureau. (Read the back first note #fill nest page)-Installation. Order The size of this paper is applicable to the Chinese National Standard (CNS & A4 specifications (210X297mm) -11-A7 B7 Central Ministry of Fun Tao The bureau's labor cooperation and consumption cooperation Du Printing 1 'V. Description of the invention 丨 (9) 1 Specific examples of column decoders 3 and row decoders 4 such as the line I B of the I part. 1 The mask R 0 Μ is for example 4 Μ digital (1 6 digital parallel output): and 1 1 I in the address A 0 A 7 A 0 A 6 will be selected for row selection 1 1 A 7 A 1 7 for column selection 0 column decoding 3 and row decoder 4 > kj read ik 1 1 As mentioned above, the first and second memory blocks 1 a 1 b are shared e The back 1 column 1 decoder 3 is equipped with Select one of the 6 segment ideas 1 event 1 one of the transistors US in the NAND lattice group MC. The address A 7 used is then 1 1 installed IA 1 0 to decode the decoder RD 1 (the output is 16 ) And I will choose 6 4 block R Β 〇RB 6 3 to use the lower address 1 1 | A 1 2 A 1 4 and the upper address A 1 5 A 1 7 Decoded 1 I decoder RD 2 (8 outputs) and RD 3 (8 outputs) «> 1 The second segment is because the outputs of the decoders RD 2 and RD 3 are input. Set 1 to select 6 4 column blocks RB 0 RB 6 3 is equipped with a decoder 1 1 RD 4 (the output is 6 4); in the third segment is equipped with the option 1 1 2 0 4 8 The word line. The decoder RD 1 RD 4 used · The output and address of the line A 1 1 will be input to the decoder RD 5 (output 1 1 is 2 0 4 8) 0 1 1 decoder RD 1 is composed of 16 groups of detected A 7 A 1 0 1 1 Inverter group used in conjunction with 1 1 NAND gate group (or AND gate group) for id en ti ty detect The «decoder RD 2 | RD 3 is also constituted 0 decoder R 0 4 is detected by the identical detection of 8 outputs of each of RD 2 1 IRD 3 6 4 NAND gate groups 1 1 I (or A ND gate group) constitute 0 and> A 1 1 is also used to select the NA ND type lattice group within each row block 1 1 Figure 3 of 1 1 This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) ~ 12-Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative A7 __ B7 V. Description of invention (10) V ss line or The V DD line of Fig. 5 is used by any one of the NAND type lattice groups adjacent to each other above and below; the decoder RD 5 is also composed of: the sum of the output of 16 branches of the decoder RD 1 and the output of 6 branches of the RD 4 The inverter group used in the combination of A 1 1 and the NAND gate group (or AND gate group) are formed. When the output of 2048 branches of decoder RD5 is selected, one will become. The output of this decoder RD 5 is supplied to the word line WL Ο ~ WL 2 0 4 7 through the word line driver WD in the form of an inverter, and with the $ state selected, a word line will become # The row decoder 4 has: a decoder CD1 (output 4) that decodes the addresses A1 and A2 for local bit line selection, and a decoder CD2 that decodes A3 ~ A6 (output is 16). The output of these decoders CD1, CD2 will be sent to the row selectors 5a, 5b. The row selectors 5a, 5b are as shown in FIG. 8, which is: the decoder CD that decodes the addresses A1, A2 The output of 1 of 4 branches, and the output of 16 branches of decoder CD 2 that decodes addresses A 3 to A 6 are composed of two stages of controlled gates Q21, Q22, Qll, Q12, etc. " Thus, the row selectors 5a, 5b, one in each of the first and second memory blocks 1a, lb, will select one branch from the 64 local partial lines B LO ~ BL 6 3 in the row block CB, The local bit lines (16 in total) selected from each memory block 1 a, 1 b will be connected to the differential reading via the output bit line B. Out amplifier SA. At the reference output terminal of the differential sense amplifier SA, the paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) (please read the precautions before filling in this page) -install- * va Line 13-A7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. V. Invention Description (11) The reference voltage VREF = V DD / 2 will be supplied. In addition, the row decoder 4 is one of the selection gate lines S L that selects 256, and has the output of the decoder R04, and the decoder CD3 where AO and A 1 1 are to be input. Here, the lowermost address A is for deciding to select any one of the NAND type lattice groups along the left and right two lines of the local bit line BL. More specifically, it is to decide the choice: choose the group of gate lines (SL0, SL2 .........) and the group of (SL1, SL 3 ..........) Any user. The address A 1 1 is the same as that of the column decoder 3 side, and is used for deciding to select any one of the NAND type lattice groups holding the V ss line in FIG. 3 or the V DD line in FIG. 5. Specifically, in view of the column block R Β Ο, it is to decide the choice: select any group of gate lines (SL0, SL1) and (SL2, SL3) group of users. The decoder CD3 integrates the above logic from the inverter group and the NAND gate group (or AND gate group) for identical detection, thereby making it output 2 5 6 branches in the selected state One becomes the output of this decoder CD3, which will be supplied to the 256 selection gate lines SL1 ~ SL256 via the non-inverting selection gate driver SD, and the selection gate line is enabled in the non-selected state SL1 ~ SL256 become, and in the selection state, one selection gate line will become "" Η ". The following describes the data reading operation of the NAND-type mask ROM of such a structure. As mentioned above, the word line WL is all * H returned in the non-selected state, and the selection gate line SL is all 'L 〃 in the non-selected state: so the determination timing of the character line selection and the selection gate selection Determine the timing when the subdivision paper size is applicable to the Chinese National Standard (CNS> Λ4 specification (210Χ297mm) '-14-(please read the precautions on the back before filling this page)-installed. Μ • Ministry of Economic Affairs Central Ladder Printed 3GC483 A7 B7 by the quasi-bureau consumer cooperative. V. Description of the invention (12) Qi (does not match). This divergence will have important significance; but first of all, if you ignore this divergence, let ’s explain its basic actions first. If the data is input, a character line will be selected by the column decoder 3. For example, focusing on FIG. 3, assume that the column block RBO will be selected, and one of the word lines WLO ~ WL15 is also selected. The row decoder 4 selects either one of the selection gate lines SL ′ 'SL1 and the selection gate lines SL2 and SL3 become both. When one of the word lines WL1 6 to WL3 1 is selected, SL2 , SL3 will become ", and become SL0 = SL1 =. In memory The same is true for lb. Thus, the NAND-type lattice groups of 6 to 4 along each local bit line BL of each memory block 1 a and one column block of lb will be selected to be connected to the local bit line. And, by row Decoder 4, in each memory block 1 a, 1 b ′, from each row block CB, a total of 16 local bit lines will be selected and connected to the output bit line B. Specifically, suppose the first , The word line WL 〇 corresponding to the second memory block la, lb and the local bit line BL 〇 will be selected at the same time, and each memory transistor M0 is also selected. In the NAND type ROM, the word is selected The element line becomes, from this, it will be detected whether the selected memory transistor is E-type or D-type. Figure 9 (a) (b) is an example of the action of reading the selected data. See Figure 9 (a ), Assuming that the memory transistor Μ Ο on the 1st memory block 13 side 3 billion block 1 b side is E-type, that is, the data, i, corresponds to the 2nd memory block 1 b side Memory transistor! ^ 〇 is ρ type. These data will be transferred to an output through the local bit line BL 0 at the same time. The paper size is applicable to China National Standard (CNS) Λ4 specifications 210X 297 mm) '-(Please read the precautions before filling in this page) • Binding. Binding line-15-A7 B7 5. Description of the invention (13) Bit line B. At this time, the output bit Element B, as shown in Fig. 9 (a), 'E type memory transistor M0 on the first memory block 1 a side and D type memory transistor M0 on the second memory block 1 b side will be connected in series Between the power supply V and ground Vss. Then, since the selected word line WL 0 will be, the memory transistor MO on the V DD side will be ON, and the memory transistor MO on the V ss side will be Ο FF; therefore, the charging current shown by the arrow will flow out. Line B will rise to the power supply potential VDD. If the data is reversed, as shown in FIG. 9 (b), the memory transistor M0 on the V DD side will be OFF, and the memory transistor MO on the V ss side will become Ο N, so the current indicated by the arrow will flow, and the output bit Element B will drop to ground potential V SS. As described above, in this embodiment, since the complementary operation shown by the two billion transistors selected by the two memory blocks 1 a and 1 b will be performed; the potential of the output bit line B will be released, and the VRE F = V DD / 2 is used as a reference (reference) potential to detect the differential sense amplifier SA, then it can be used for data> 1 ^ judgment. Therefore, according to this embodiment, it is different from the conventional method of performing data sense with a signal of a small amplitude, and it can be carried out without being easily affected by simultaneous switching noise or external noise, and without error operation. Data reading. Moreover, the output bit line B can also increase the large amplitude to V DD or Vss, and this is detected by a differential sense amplifier; therefore, compared with the method of using a negative and feed amplifier to detect small signals, Quick action will become possible. In the case of this embodiment, as mentioned above, the paper size is indeed selected in the character line. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) (please read the opposite first (Notes and then fill out this page). Installation-St line-Printed by the Employee Consumer Cooperative of the Central Escalation Bureau of the Ministry of Economic Affairs -16--Printed by the Ministry of Economy Central Standard Falcon Bureau Beigong Consumer Cooperative 30Z4Q3 A1 B7 V. Description of the invention (14) The timing of the determination of the selection and selection of the gate line will diverge (do not match), so the precharge of the output bit line B will be performed automatically. This pre-charging operation will be described with reference to FIG. 10. FIG. 1 〇 is a diagram showing that: the potential change of the selected word line WL and the selected selection gate line SL, and the potential change of the output bit line B》 the address is latched at time t 〇 At time t 1, the row decoder 4 and the row selectors 5 a and 5 b perform local bit line selection. The local bit line selection is shown in FIG. 7 and is performed by the decoders CD 1 and CD 2 of the one stage of the row decoder 4 and the row selectors 5 a and 5 b; Fast, and the local bit line BL selected at time t 1 is connected to the output bit line B. The word line selection and the selection gate selection are all performed by the three-segment decoder in the decoder configuration of FIG. 7; therefore, the time is assumed to be t2. From this time t2, as shown in FIG. 10, the selected word line WL is shifted from the beginning, and the selected gate line SL is shifted from the beginning. Take the selection gate MOS transistor as the head. The threshold V th of the E-type MOS transistor is usually smaller than V DD / 2 and is set from about 0.7V. Therefore, the selection gate line SL rises to V th and the selection gate MOS transistor turns ON At time t3 (the timing of selection and selection of the selection gate line SL), the time t 4 at which the word line WL is lowered to Vth (the timing of selection and determination of the word line WL) will be delayed ". The delay time t 1 from this time t 3 to t 4 It becomes the precharge period. That is to say, between this delay time t α, the output terminals of the two selected NAND cell groups will be applied to the Chinese standard (CNS) Λ4 specification (210X297 mm) through the selection gate standard that has been turned on. Installation · II order-III-line (please read the precautions on the back before filling in this page), -17-A7 ___B7_ printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (15) MOS transistor Is also connected to the output digit line B via the local bit line BL. During this period, all memory transistors of these two NAND cell groups will still be kept in the ON state (non-selected state). As a result, the ground potential Vss of the first memory block 1 a and the power supply potential VDD of the second memory block 1 b will be short-circuited through the output bit line B, and the read data from the previous cycle will be maintained or become The floating output bit line B is pre-charged to VDD / 2. Thereafter, at time 14, the word line selection will be confirmed, and the memory transistor in one of the two selected NAND cell groups will become OFF, and by the aforementioned complementary action, the output bit line will migrate to V DD Or V ss. As described above, before the word line is determined, automatically, the output bit line and the local bit line will be precharged to V DD / 2; thus, high-speed and reliable data reading can be performed. 11 shows another example of the configuration of the column decoder 3. This is for the decoder of FIG. 7 to be composed of two stages of RD 5 1 to RD 5 2 and the column decoder 3 as a whole is composed of two stages. If the row decoder is the same as the previous embodiment, the delay at the column decoder will become larger compared to the row decoder. As a result, as shown in Fig. 12, it will be obtained that the determination of column selection will be delayed by t 2 from the row selection. Therefore, between this delay time t 2 and the previous embodiment, the same It can pre-charge the output number B. The embodiment of the NAND-type mask ROM has been described above, but the same technical concept can also be applied to the NOR-type mask ROM. Fig. 13 shows the main parts of the N 0 R type hood type R 0M constituting other embodiments of the present invention. The paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (21〇 < 297 mm) IIIIII package— I 1 II Order IIII * silk (please read the precautions before filling in this page), a 18 _ printed by A 7 B7, the invention description (16) by the Central Standard Falcon Bureau of the Ministry of Economic Affairs. It also includes: the first memory block 1 a and the second memory block 1 b, which are jointly selected by the column decoder and the row decoder »in the NOR type lattice group MC, written at the corresponding addresses The opposite data becomes: the state of the data mode that can be inverted between the first and second memory blocks 1 a and 1 b. Also, in the first memory block la, the memory cell reference terminal will be set to Vss, and in the second memory block 1b, the memory cell reference terminal will be set to V DD. In the case of the NOR type masked MOM, the word line WL becomes t L # (for example, V ss) in the non-selected state, and becomes ^ (for example, VDD5 in the selected state. Also, the binary data of the grid group (binary data ) It will be remembered as the first threshold state between the character line and the second threshold state with the higher level. The data is read out by detecting the selected memory cell According to whether the data is turned ON and OFF, the current is introduced. Therefore, the corresponding address grids of the first and second memory blocks la and lb are selected and connected to the output bit line at the same time, then The reading of data by the same complementary action as the previous embodiment will become possible. The present invention will not be limited to the above-mentioned embodiment, but can also be applied to various PROMs, EPROMs, etc. [Effects of the Invention] As described above, in the present invention The semiconductor memory device has the 1st and 2nd billion blocks for writing and inverting pattern data, and the reference terminals of each memory block are set to be different from each other in the first I · 1 IIIIIII Pack — IH — Order —-^ I line (Please read the precautions before filling in this page) · This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specifications (210 X 297 mm) -19-A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs i , Invention description (17), the second reference potential, to perform the data reading of the complementary operations of these memory blocks; therefore, it will be possible to improve noise resistance and high-speed performance. [Simple description of the drawings 〕 [FIG. 1] shows the block structure of the mask ROM according to an embodiment of the present invention [FIG. 2] shows the specific structure of the memory block of this embodiment. [FIG. 3] shows the details of a part of the first memory block Constructor. [Figure 4] A further detailed structure of a part of the circuit of FIG. 3. [FIG. 5] A detailed structure of the second memory block corresponding to FIG. 3. [FIG. 6] Data showing the embodiment Mode example · [Figure 7] indicates that the decoder of this embodiment has been constructed. [Figure 8] indicates that the row selector of this embodiment has been constructed. [Figure 9 (a) (b)] indicates that of this embodiment The actor who reads the data. [Fig. 10] Say This figure shows the precharge operation of this embodiment. [Figure 11] shows the structure of the column decoder of this embodiment. [Figure 12] shows the operation timing of this embodiment. [Figure 13] shows other embodiments The main part of the cover ROM is composed of this paper. The standard of this paper is the Chinese National Standard (CNS) Λ4 specification (210X297mm) (please read the precautions on the back and fill in this page) • Install., Ar Ni-20-A7 B7 5. Description of the invention (18) [Explanation of numbering in the drawings] la ......... 1st memory block 2 4 6 address buffer, line decoder, 5 a differential readout amplifier circuit lb 3 5 b 7 second memory block column decoder, row selection circuit output circuit. (Please read the precautions on the back before filling in this page). 装., Va Syria Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative Printed This paper standard is applicable to China National Standards (CNS) Λ4 specifications (210X 297 mm) -21