KR20010092073A - Verify read method for use in a nand-type flash memory device - Google Patents

Abstract

PURPOSE: A verify read method of a NAND type flash memory device is provided, which supports a 1K read verify operation without increasing a memory area. CONSTITUTION: The flash memory device includes a memory cell array(100), a row decoder circuit(120), the first page buffer circuit(140) and the second page buffer circuit(160). The memory cell array includes a plurality of bit lines, for example, 1K bit lines and redundant bit lines. The even-numbered bit lines(BLm, m=0,2,4,...,1023) among the above bit lines are connected electrically to the first page buffer circuit arranged on an upper part of the memory cell array, and the other bit lines(BLn, n=1,3,4,...,1022) are connected electrically to the second page buffer circuit arranged on a lower part of the memory cell array. String corresponding to each bit line includes a string select transistor(SST), a plurality of floating gate memory cell transistors(M0-M15) and a ground select transistor(GST). A drain of the string select transistor is connected to a corresponding bit line, and its gate is connected to a string select line(SSL). The ground select transistor has a source connected to a common source line and a gate connected to the gate of the ground select line. Drain-source channels of the above memory cell transistors are connected serially between the source of the string select transistor and the drain of the ground select transistor, and their gates are connected to corresponding word lines(WL0-WL15) respectively. The string select line and the word lines and the ground select line are connected to the row decoder circuit electrically. The first and the second page buffer circuit include page buffers corresponding to each bit line.

Description

VERIFY READ METHOD FOR USE IN A NAND-TYPE FLASH MEMORY DEVICE}

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a read verification method of a NAND type flash memory device.

Among the electrically erasable and programmable nonvolatile semiconductor memories, the cell array structure of the NAND flash memory device is an incremental transistor for selecting a string, and a string select transistor and a ground select transistor for selecting ground. The plurality of floating gate memory cell transistors connected in series are configured in string units. Each string of memory cells is generally comprised of sixteen floating gate memory cell transistors. When the string is selected, a power supply voltage is applied to the gate of the string select transistor and the gate of the ground select transistor, and a ground voltage of 0 V is applied to the word line connected to the selected memory cell transistor during a read operation, and the remaining memory cell transistors are applied to the gate line of the string select transistor. A power supply voltage is applied to each of the connected word lines.

The read operation of the NAND flash memory device is performed in units of pages, and the data stored in the memory cells of the selected word line arranged in the selected block is read by the page buffer circuit in the NAND flash memory device, and the read data is stored in pages. Each is stored in the latches in the buffer circuit and then sequentially output. Memory cells generally have an increased threshold voltage as electrons are electrically trapped in the floating gate of the memory cell transistor, and are a "programmed cell" or "off cell". It is called (OFF cell). At this time, the off cell is defined to store data '0'. In contrast, a memory cell that is an electrically depletion type transistor and has a negative threshold voltage is called an "erased cell" or an "on cell". At this time, the on-cell is defined to store the data '1'.

By default, sense current is applied to the selected string in a read operation. At this time, the programmed cell, that is, the off cell transistor, is turned off because it has a high threshold voltage even if a ground voltage of 0V is applied to the corresponding word line. As a result, the bit line corresponding to the selected string is in a floating state, with the result that the voltage of the bit line is gradually increased. In contrast, an erased cell, that is, an on cell transistor, is turned on because it has a negative threshold voltage when a ground voltage of 0V is applied to the corresponding word line. That is, the drain-source channel of the on cell transistor is formed so that the current supplied to the corresponding bit line is discharged through the common source line. Therefore, the voltage of the bit line corresponding to the on cell transistor is gradually lowered.

The operation description and problems of the prior art for reading data in page units according to the above-described reading method are as follows. The decrease in cell size with increasing memory density results in a decrease in cell current. Such a decrease in cell current causes the amount of current supplied to the cell string bit line to determine cell data in the NAND flash memory device to be reduced, resulting in the voltage on the bit line being turned off and on when the off cell is selected. The time to raise to the voltage which can distinguish a cell becomes long. In addition, as the current difference for discriminating between the off cell and the on cell is small, the data sensing operation is also difficult.

As a technique to improve this, a large amount of current is supplied to the bit line in advance so that the bit line is charged to a required voltage level, and then a predetermined amount of current is supplied to the bit line. According to this scheme, when the voltage level on the bit line is slightly changed in the data stored in the selected memory cell, the node serving as the input of the sense amplifier through means for controlling the data line precharge level connected to the bit line and the sense amplifier. The parasitic capacitance component of and the parasitic capacitance component of the bit line are electrically separated. As a result, the node that becomes the input of the sense amplifier is changed greatly according to the change of the small bit line, so that not only can improve the speed loss caused when reading data, but also a small amount of current Since supplied, noise immunity can be improved.

Since the data stored in the memory units of the page unit are read at one time in the NAND flash memory device, the above-described read scheme (hereinafter, referred to as a bit line pre-charged read method) is used. When the bit line is selected, a coupling phenomenon between the adjacent bit lines of the off cell and the bit line of the selected on cell is experienced when the precharged bit line voltage is lowered. To prevent such coupling, the bit lines adjacent to the selected bit line must be shielded with ground voltage.

In the case of a flash memory device, a verify read operation is performed to determine whether a program is properly performed after programming. In general, a flash memory device supports a 1K program for programming two pages, that is, 1K memory cells at a time, to increase program ease. In this case, in the memory cell structure of the flash memory device of the prior art having 16K-byte as one block, there is a problem that 1K verify read operation cannot be performed after 1K program. In order to solve such a problem using the read method according to the prior art, the number of strings in the block must be doubled. This not only violates design specifications, but also has the adverse effect of increasing chip area. Therefore, according to the conventional technique of adopting a precharge method to ground shield neighboring bit lines, the 1K verify read operation is not possible because the number of bit lines to be selected must be reduced by half to prevent the selected bit lines from being coupled. Do.

Accordingly, an object of the present invention is to provide a read verification method of a NAND flash memory device supporting 1K read verification operation without increasing the memory area.

1 is a block diagram showing a NAND flash memory device according to the present invention;

2 is a circuit diagram showing a page buffer according to a preferred embodiment of the present invention;

3 is a timing diagram for explaining a verify read operation according to the present invention; And

4 is a diagram illustrating a change in voltage of a sensing node according to data stored in a memory cell.

* Explanation of symbols on the main parts of the drawings

100: memory cell array 120: row decoder circuit

140: first page buffer circuit 160: second page buffer circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a NAND type flash memory device includes an array of memory cells arranged in cross regions of word lines arranged along rows and bit lines arranged along columns. A row decode circuit connected to the word lines, a first page buffer circuit connected to odd bit lines of the bit lines, and a second page buffer circuit connected to even bit lines of the bit lines; The data stored in the memory cell array of the NAND flash memory device may include data from the memory cell array through the even-numbered bit lines after shielding the odd-numbered bit lines with a ground voltage during a 1K verify read operation. Reading; After shielding the even-numbered bit lines with a ground voltage, the data is read by reading data from the memory cell array through the odd-numbered bit lines.

(Action)

In this manner, in the case of using the bit line precharge read method, the 1K byte verify read operation may be performed by shielding odd and even bit lines with ground voltage and performing two read operations. have.

(Example)

Embodiments according to the present invention are described in detail below on the basis of reference drawings. According to the verify read operation according to the present invention, two read operations are performed through odd (or even) bit lines and even (or odd) bit lines in a 16K-byte block structure. That is, during the first read operation, the read operation is performed through the odd bit lines while the even bit lines are shielded by the ground voltage. Then, during the second read operation, the odd bit lines are shielded with the ground voltage while the read operation is performed over the even bit lines. According to this method, the 1K verify read operation may be performed after the 1K program is performed.

1 is a block diagram schematically illustrating a NAND flash memory device according to a preferred embodiment of the present invention. The flash memory device includes a memory cell array 100, a row decoder circuit 120, a first page buffer circuit 140, and a second page buffer circuit 160. The memory cell array 100 includes a plurality of bit lines, for example, 1K bit lines and redundant bit lines. Even-numbered bit lines BLm (m = 0, 2, 4, ..., 1023) of the bit lines are electrically connected to the first page buffer circuit 140 arranged above the memory cell array 100. The remaining bit lines BLn (n = 1, 3, 5,..., 1022) are electrically connected to the second page buffer circuit 160 arranged under the memory cell array 100.

The string corresponding to each bit line includes a string select transistor SST, a plurality of floating gate memory cell transistors M0-M15, and a ground select transistor GST. The drain of the string select transistor SST is connected to the corresponding bit line and the gate is connected to the string select line SSL. The ground select transistor GST has a source connected to a common source line and a gate connected to the ground select line GSL. Drain-source channels of the memory cell transistors M0-M15 are connected in series between a source of the string select transistor SST and a drain of the ground select transistor GST, and gates corresponding to the word lines ( WL0-WL15) respectively. The string select line SSL, the word lines WL0-WL15 and the ground select line GSL are electrically connected to the row decoder circuit 120. The first and second page buffer circuits 140, 160 include page buffers corresponding to each bit line, and a preferred embodiment of the page buffer is shown in FIG.

Referring to FIG. 2, the depletion transistor DM has one current electrode connected to a corresponding bit line BLi and a gate connected to a power supply voltage. The NMOS transistor NM1 is a source-drain channel connected between another current electrode of the depletion transistor DM and a node labeled S0 and a signal or bit line shut off signal provided from a reference voltage generator circuit (not shown). Has a gate connected to accept BLSHF). The PMOS transistor PM has a source-drain channel connected between the power supply voltage and the node SO and a gate connected to receive a signal or precharge control signal PRE provided from a precharge control circuit (not shown). NMOS transistor NM2 having a gate to which a signal or discharge control signal DCB is applied has a source-drain channel connected between node SO and ground voltage. NMOS transistor NM3 having a source-drain channel connected between node S0 and a latch node labeled N1 has a gate connected to receive signal SBL. The source-drain channels of the NMOS transistors NM4 and NM5 are connected in series between the latch node labeled N2 and the ground voltage, and the gates are connected to the node SO and the signal or latch control signal LATCH, respectively.

3 is a timing diagram illustrating a verify read operation according to the present invention, and FIG. 4 is a diagram illustrating a voltage level of the sensing node S0 according to data stored in a memory cell. Hereinafter, the verify read operation according to the present invention will be described in detail based on the reference drawings.

According to the verify read operation according to the present invention, first, even-numbered bit lines are shielded with a ground voltage through the first page buffer circuit 140, and data stored in memory cells corresponding to odd-numbered bit lines is stored in a second page. It is sensed through the buffer circuit 160. That is, 512 bytes (528 bytes, if including redundant cells) are read without coupling. The odd-numbered bit lines are then shielded with ground voltage through the second page buffer circuit 160 and data stored in memory cells corresponding to the even-numbered bit lines is sensed through the first page buffer circuit 140. do. That is, 512 bytes (528 bytes, if including redundant cells) are read without coupling. Therefore, in the case of using the bit line precharge read method, the 1K byte verify read operation may be performed by shielding odd and even bit lines with ground voltage and performing a read operation twice.

More specifically, first, during the time t1, each bit line is grounded according to the low-high transition of the signals DCB and SBL before the read operation related to the odd bit lines is performed. At the same time, each latch (in Fig. 2, consisting of inverters L1 and L2-) is reset. Then, according to the high-low transition of the signal PRE, during the time t2, the bit line is charged by the current from the PMOS transistor PM. After the bit line is charged to the required level, for a time t3, the signal PRE rises to an arbitrary level between the ground voltage and the supply voltage, so that less current is supplied than the current supplied during precharging the PMOS transistor. Is supplied to node S0. After the predetermined time has elapsed, during the time t4, when the signal LATCH transitions from the low level to the high level, the state of the latch will change according to the level of the node SO. That is, data stored in the selected memory cell is latched. At this time, the even-numbered bit lines are shielded with the ground voltage by the corresponding page buffer circuit. Similarly, the read operation related to the even bit lines is also the same as the read operation related to the odd bit lines, and the description thereof is omitted to avoid duplication of description. At this time, the odd-numbered bit lines are shielded by the ground voltage by the corresponding page buffer circuit.

As described above, in the case of using the bit line precharge read method, a 1K byte verify read operation may be performed by shielding odd-numbered and even-numbered bit lines with ground voltage and performing a read operation twice. .

Claims (2)

An array of memory cells arranged in intersection regions of word lines arranged along rows and bit lines arranged along columns, a row decode circuit connected to the word lines, and an odd bit line of the bit lines 1. A method of verify reading of a NAND type flash memory device comprising: a first page buffer circuit coupled to a second page buffer circuit; and a second page buffer circuit coupled to even bit lines of the bit lines. After shielding the odd bit lines with a ground voltage, reading data from the memory cell array through the even bit lines; Reading the data from the memory cell array through the odd bit lines after shielding the even bit lines with a ground voltage. The method of claim 1, And the bit lines are 1K.