KR960042762A - Semiconductor storage device - Google Patents

Semiconductor storage device Download PDF

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Publication number
KR960042762A
KR960042762A KR1019960014305A KR19960014305A KR960042762A KR 960042762 A KR960042762 A KR 960042762A KR 1019960014305 A KR1019960014305 A KR 1019960014305A KR 19960014305 A KR19960014305 A KR 19960014305A KR 960042762 A KR960042762 A KR 960042762A
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KR
South Korea
Prior art keywords
memory
bit line
local bit
lines
word lines
Prior art date
Application number
KR1019960014305A
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Korean (ko)
Other versions
KR100200012B1 (en
Inventor
요시토모 나나미야
Original Assignee
우에시마 세이스케
야마하 가부시키가이샤
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Publication of KR960042762A publication Critical patent/KR960042762A/en
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Publication of KR100200012B1 publication Critical patent/KR100200012B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 내노이즈성과 고속성능을 향상시킨 반도체 기억장치에 관한 것으로, 본 발명은 제1, 제2메모리블록(1a)(1b)을구비하고, 그 각각 다수개씩의 로컬비트선과 워드선의 각 교차부에 메모리셀이 배치되어 있다. 2개의 메모리블록(1a)(1b)의 대응하는 메모리셀에 서로 반전패턴의 데이터가 기입되며, 제1메모리블록(1a)측의 기준단자는 접지(VSS)에 접속되고,제2메모리블록(1b)측의 기준단자는 전원(VDD)에 접속된다. 로우디코더(3)와 컬럼디코더(4) 및 컬럼셀렉터(5a)(5b)에 의해 제1, 제2메모리블록(1a)(1b)내의 서로 대응하는 메모리셀이 동시에 선택되어 출력비트선에 전송되고, 이들의 상보동작에 의한 출력비트선의 전위변화를 차동형세스앰프(6)에서 판도한다.The present invention relates to a semiconductor memory device having improved noise resistance and high-speed performance. The present invention relates to a semiconductor memory device having first and second memory blocks (1a, 1b), each of which has a plurality of local bit lines And a memory cell is disposed in a portion. The data of the inverted patterns are written into the corresponding memory cells of the two memory blocks 1a and 1b, the reference terminal on the first memory block 1a side is connected to the ground VSS, 1b are connected to the power supply VDD. The corresponding memory cells in the first and second memory blocks 1a and 1b are simultaneously selected by the row decoder 3, the column decoder 4 and the column selectors 5a and 5b, And the potential change of the output bit line due to the complementary operation of these is represented in the differential type sense amplifier 6.

Description

반도체 기억장치Semiconductor storage device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명의 일실시예에 의한 마스크 ROM의 블록구성을 나타낸 도면, 제2도는 본 발명에 의한 실시예의 메모리블록의 구체구성을 나타낸 도면, 제3도는 제1도의 메모리블록 일부의 상세한 구성을 나타낸 도면, 제4도는 제3도의 회로 일부의 보다 상세한 구성을 나타낸 도면.FIG. 1 is a diagram showing a block configuration of a mask ROM according to an embodiment of the present invention; FIG. 2 is a diagram showing a specific configuration of a memory block in an embodiment of the present invention; Fig. 4 shows a more detailed configuration of a part of the circuit of Fig. 3; Fig.

Claims (2)

다수개의 로컬비트선과, 이 로컬비트선과 교차해서 배설된 다수개의 워드선과, 이들 워드선과 상기 로컬비트선의 각 교차부에 배치되어 각각 소정의 데이터가 기입되고, 상기 워드선에 의해 선택적으로 구동되는 다수의 메모리셀을 구비하고, 상기 각 메모리셀의 기준단자가 제1기준전위에 접속된 제1메모리블록과, 다수개씩의 로컬비트선과 워드선및 다수의 메모리셀이 레이아웃되고, 각 메모리셀에는 상기 제1메모리블록내의 대응하는 번지의 메모리셀 데이터와는 반대의 데이터가 기입되며, 또 기준단자가 상기 제1기준전위와 다른 제2기준전위에 접속된 제2메모리블록과, 상기 제1, 제2메모리블록내의 서로 대응하는 번지의 메모리셀을 동시에 선택하고, 이 선택된 2개의 메모리셀 출력단자를 각각 선택된로컬비트선을 통해 하나의 출력비트선에 접속하는 선택수단과, 이 선택수단에 의해 선택된 2개의 메모리셀이 상기 제1, 제2기준전위 사이에 직렬접속되어 한쪽은 온, 다른쪽은 오프가 되는 상보동작을 하는데 따른 상기 출력비트선의 전위변화를 검출하는 차동형 센스수단을 구비한 것을 특징으로 하는 반도체 기억장치.A plurality of local bit lines, a plurality of word lines arranged to intersect with the local bit lines, and a plurality of word lines, each of which is arranged at each of the intersections of the word lines and the local bit lines and in which predetermined data is written, A first memory block having a plurality of memory cells, each memory cell having a reference terminal connected to a first reference potential, a plurality of local bit lines, a plurality of word lines, and a plurality of memory cells, A second memory block in which data opposite to the memory cell data of the corresponding address in the first memory block is written and the reference terminal is connected to a second reference potential different from the first reference potential; Two memory cells corresponding to each other in the two memory blocks are simultaneously selected and the selected two memory cell output terminals are connected to one output bit line through the selected local bit line And the second memory cell selected by the selecting means is connected in series between the first and second reference potentials, and the potential change of the output bit line in accordance with the complementary operation in which one is turned on and the other is turned off And a differential sense unit for detecting the differential signal. 제1항에 있어서, 상기 제1, 제2메모리블록의 각 메모리셀은 각각 다른 워드선에 의해 구동되는 다수의 MOS트랜지스터가 직렬접속되어서 구성되며, 이들 MOS트랜지스터가 상기 워드선이 비선택상태에 있을 때 온되는 NAND형 셀군이고, 상기 선택수단은 상기 제1, 제2메모리블록내의 대응하는 NAND형 셀군을 선택하고, 이 선택된 NAND형 셀군의 출력단자를 각각 선택된 상기 로컬비트선을 통해 동시에 상기 출력비트선에 접속하는 메모리셀 선택수단과, 상기 제1, 제2메모리블록의 대응하는 워드선을 동시에 선택하는 워드선 선택수단을 가지며, 상기 출력비트선은 상기 워드선 선택수단에 의한 워드선 선택의 확정전에 상기 제1, 제2메모리를블내의 선택된 NAND형 셀군을 통해 상기 제1, 제2기준전위의 중간전위에 프리챠지되는 것을 특징으로 하는 반도체 기억장치.The memory device according to claim 1, wherein each of the memory cells of the first and second memory blocks has a plurality of MOS transistors connected in series connected to each other, the word lines being driven by different word lines, And the selection means selects the corresponding NAND cell group in the first and second memory blocks and simultaneously outputs the output terminals of the selected NAND cell group through the respective selected local bit lines to the NAND cell group, And an output bit line connected to an output bit line by said word line selecting means, wherein said output bit line is connected to said word line selecting means by said word line selecting means, Is precharged to the intermediate potential of the first and second reference potentials through the selected NAND cell group in the first and second memories before the selection is determined. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960014305A 1995-05-02 1996-05-02 Semiconductor memory device KR100200012B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP13266695 1995-05-02
JP95-132666 1995-05-02
JP7420496A JP3726337B2 (en) 1995-05-02 1996-03-28 Semiconductor memory device
JP96-74204 1996-03-28

Publications (2)

Publication Number Publication Date
KR960042762A true KR960042762A (en) 1996-12-21
KR100200012B1 KR100200012B1 (en) 1999-06-15

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KR (1) KR100200012B1 (en)
TW (1) TW302483B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002001574A1 (en) * 2000-06-29 2002-01-03 Fujitsu Limited Semiconductor memory device
JP4684719B2 (en) * 2005-04-07 2011-05-18 パナソニック株式会社 Semiconductor memory device
JP5585491B2 (en) * 2011-02-23 2014-09-10 富士通セミコンダクター株式会社 Semiconductor memory and system
JP5665789B2 (en) * 2012-03-28 2015-02-04 株式会社東芝 Configuration memory
DE202014106307U1 (en) 2014-12-30 2015-02-25 E-Lead Electronic Co., Ltd. Reinforced valve

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JPH0922600A (en) 1997-01-21
TW302483B (en) 1997-04-11
KR100200012B1 (en) 1999-06-15
JP3726337B2 (en) 2005-12-14

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