TW301792B - Tape automated bonding method and structure thereof - Google Patents

Tape automated bonding method and structure thereof Download PDF

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Publication number
TW301792B
TW301792B TW085101718A TW85101718A TW301792B TW 301792 B TW301792 B TW 301792B TW 085101718 A TW085101718 A TW 085101718A TW 85101718 A TW85101718 A TW 85101718A TW 301792 B TW301792 B TW 301792B
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Taiwan
Prior art keywords
conductive
bonding
patent application
aforementioned
item
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TW085101718A
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Chinese (zh)
Inventor
bao-yun Tang
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Ind Tech Res Inst
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Priority to US08/579,511 priority Critical patent/US6008072A/en
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW085101718A priority patent/TW301792B/en
Priority to JP8261714A priority patent/JPH09223714A/en
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Publication of TW301792B publication Critical patent/TW301792B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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  • Wire Bonding (AREA)

Abstract

A method of forming bonding structure comprises of: (1) preparing one integrated circuit component with conductive bonding bump;(2) preparing one anisotropic conductive film composed by insulating adhesive coated on protection layer and conductive particle distributed in insulating adhesive; (3) preparing one first dielectric made of first dielectric material; (4) preparing one lead array made of many conductive lead adhered to first dielectric, in which conductive lead of the lead array has inner lead terminal and outer lead terminal, and the inside perimeter of first dielectric has one void without first dielectric material, and inner lead across inside perimeter extends to void without first dielectric; (5) preparing one isolating film by adhering one supporting metal to second dielectric; (6) preparing one thermode to supply thermal energy via selected time, temperature and pressure; (7) placing one anisotropic conductive film on the above integrated circuit component, making many conductive particles within contact with conductive bonding bump; (8) with first step time transferring thermol energy of first step temperature and first step pressure to anisotropic conductive film via protection layer; (9) tearing the above protection film; (10) forming many bonding pairs, which are combined by one of the above inner lead and one of the above conductive bonding bump, and the above conductive particle places the above lead array on conductive particle distributed inside insulating adhesive, making conductive particle be positioned between one of the above inner leads and one the above conductive bonding bumps; (11) overlaying the above void with insulating film, and the above second dielectric material is between the above lead array and the above supporting metal layer; and (12) with second step time transferring thermol energy of second step temperature and second step pressure to the above isolating film, insulating dielectric and bonding pair, making the above each bonding pair form conductive bonding between the above conductive particle, the above inner lead terminal and the above conductive bump.

Description

經濟部中央橾準局員工消費合作社印震 A7 B7 五、發明説明(I ) 發明背景 本發明係有關於一種由導電粒子(Conductive Particle)與絕緣性黏著劑(Insulation Adhesive)所構成 之異方性導電膜(Anisotropic Conductive Film, ACF) ’ 經由捲帶式晶粒接合(Tape Automated Bonding, TAB)方 法,使積體電路元件之輸入/輸出端與金屬引腳陣列(Lead Array)形成導電性接合。由於異方性導電膜的使用,使得接合 製程能提供較低之接合溫度、壓力及可信賴的封膠 (Encapsulation)結構。 習知技術 傳統的捲帶式晶粒接合方法必需以高溫讓金屬引腳陣列之內 端引腳與積體電路元件之輸入/輸出端形成導電性接合。由於組 裝元件彼此間之熱膨脹係數(Coefficient of Thermal Expansion, CTE)差異,使得後續外部引腳與基板之對位接合 製程變得更困難,本發明是藉由異方性導電膜與捲帶式晶粒接合 製程的使用,提供了避免此問題發生的方法。異方性導電膜是由 導電粒子與絕緣性黏著劑所構成的。The Ministry of Economic Affairs, Central Bureau of Accreditation and Employee Consumer Cooperative Yinzhen A7 B7 V. Description of the Invention (I) Background of the Invention The present invention relates to an anisotropy composed of conductive particles and insulating adhesives Conductive film (Anisotropic Conductive Film, ACF) 'Tape Automated Bonding (TAB) method is used to make the input / output end of the integrated circuit element and the metal pin array (Lead Array) form a conductive bond. Due to the use of anisotropic conductive films, the bonding process can provide a lower bonding temperature, pressure and reliable encapsulation (Encapsulation) structure. Conventional technology The traditional tape-and-reel die bonding method requires high temperature to form conductive bonding between the inner end pin of the metal pin array and the input / output end of the integrated circuit device. Due to the difference in the coefficient of thermal expansion (CTE) of the assembled components, the subsequent alignment bonding process of the external pins and the substrate becomes more difficult. The present invention uses an anisotropic conductive film and a tape-type crystal The use of particle bonding process provides a way to avoid this problem. The anisotropic conductive film is composed of conductive particles and insulating adhesive.

Tagosa等人在其所申請之專利(1].5.?3〖.如· 4,9 63,002 )描述有關使用導電粒子與絕緣性黏著劑之接合結 構,Fujimoto在其所申請之專利(3-639 7,Japan)中則描述 了有關複合導電粒子、黏著劑層及翻轉式晶粒接合(Flip Chip Bonding)的方法。Tsukagoshi等人在其所申請之專利(U.S. Pat. No. 5,00 1,542 )描述了由玻璃、合成樹脂 '金屬 '陶 瓷或這些材料所混合組成之基板;基板中心部份爲一空孔,用於 薄層載具或TAB的結構。Tsukagoshi等人用可變形的導電粒子' 硬的導電粒子及黏著劑所組成之材料形成導電接合。本案發明所 木紙張尺度適用中國國家標準(CNS ) A4規格(210X2W公嫠) I n^i 1--- I - I'-» —ϋ n^i - I -士-- —^ϋ— —II ml ^ J. - 0¾. i (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 301792 A7 ___B7_五、發明説明(> ) 使用之捲帶式晶粒接合之結構及製程爲一種不同、且更具彈性的 金屬引腳陣列架構。本案發明所使用之異方性導電膜是由黏著劑 與各種不同形式之導電粒子所組成 > 這與Tsukagoshi等人在其 所申請之專利描述不同。至於形成導電接合之製程與 Tsukagoshi等人在其所申請專利所提出之方法也不同。 Tsukagoshi等人在其所申請之專利(U. S. Pat. No 4,470, 657 )中敘述以多種尺寸的導電粒子與黏著劑所構成的異 方性導電膜的用途,捲帶式晶粒接合方法在此發明專利中並未提 及。 Tsukagoshi等人在其所申請專利(U. S· Pat_ No 4,731,282 )是有關於絕緣性黏著劑之敘述。 發明的簡要說明 傳統捲帶式晶粒接合(TAB)的結構如圖1所示,引腳陣列由金屬 引腳22 ;此金屬引腳可以是銅,金屬引腳是附著於第一種介電層 23 ;此介電層可以是聚乙醢氨(Polyimide),金屬引腳之內端 與導電性凸塊2 1 ;此導電性凸塊可以是金(Au )凸塊 (Bump)。金凸塊是利用電鍍的方法鍍在積體電路元件20之氧化 鋁輸入/輸出端。熱能經由加熱頭(Thermode) 10以所設定之溫 度、壓力及時間參數,傳遞至金屬引腳陣列中之金屬引腳,使金 靥引腳之內端與金凸塊形成導電性接合。 在傳統的捲帶式晶粒接合製程中高溫是必要的;通常是介於 450至550°C之間,如此才能使金屬引腳陣列中之金屬引腳與積 體電路元件上之金凸塊形成導電性接合。銅引腳22與介電層23之 熱膨脹係數差異,使得後續外部引腳與基板之對位接合製程變得 更困難。金屬凸塊本身之硬度會將加熱頭所施加之作用力傳至積 體電路元件,使氧化鋁墊發生破裂現象,爲避免此現象’控制加 « I- - I S I - I- I - — -I-士又- I - I - I - !· ------- TW • 、va (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X2$公釐) 一1 - 經濟部中央標準局具工消費合作杜印製 A7 B7五、發明説明(3 ) 熱頭端面之平面度(Planarity)及端面與金屬凸塊之平行度 (Parallelism)變得非常重要,這將使設備的製造成本更加昂 貴。傳統的捲帶式晶粒接合製程必需在製程之後進行封膠 (Ecapsulation)以避免濕氣造成腐蝕(Corrosion)而傷及 接點。 本案發明之主要目的在於提供低成本的捲帶式晶粒接合製 程,新製程使用較低之溫度及壓力,且在接點形成之同時完成封 膠保護作用。 本案發明之更進一步的目的在於提供低成本的捲帶式晶粒接 合結構,此結構是利用較低成本之捲帶式晶粒接合製程;以較低 之溫度及壓力,且在接點形成之同時完成封膠保護作用。 這些目的是藉由異方性導電膜的使用而達成,異方性導電膜是由 導電粒子與絕緣性黏著劑所構成的。捲帶式晶粒接合製程完成 後,異方性導電膜膜內的導電粒子31便介於引腳陣列由金屬引腳 22與積體電路元件2G上之金屬凸塊;如圖2A及2B所示,導電粒 子具有補償金凸塊與加熱頭之平行度變異,因此可以減低接合製 程所使用之壓力,大約是介於20至40kg/cm2。當導電性接合形成 時,絕緣性黏著劑32包覆在接點之四週形成封膠作用,保護接點 不因大量濕氣造成腐蝕及不受機械性之傷害。接合製程所需之溫 度介於15G至18G°C之間,黏著劑在硬化(Curing)之後能使接 點維持接處狀態。 金屬引腳陣列可以是有空孔設計如圖2C所示,金屬引腳陣列 由金屬引腳22 ;此金屬引腳可以是銅,金屬引腳附著於介電層 23 ;此介電層可以是聚乙醯氨,介電層內緣四週73之接合區域 75,此接合區域沒有介電層,內部引腳之尾端74向沒有介電層區 域延伸。此種形式之引腳陣列需使用一種由金屬箔片27與聚乙醯 氨25所構成之隔絕層,使加熱頭不會和黏著劑作用,完成接合後 —^1 - - - - I I I - - HH m ^^1 ml 1 V V _ 、T (請先閱讀背面之注意事項真填寫本頁) 本紙張尺度適用中國國家標芈(CNS〉A4規格(210X297公釐) -5- 經濟部中央標準局員工消費合作社印袈 A7 B7 五、發明説明(¥ ) 之結構如圖2A所示。 金屬引腳陣列也可以是圖2D所表示的形式,此形式的金屬引 腳陣列無空孔設計,金屬引腳22附著於整片的介電層23之上,此 種形式的金屬引腳陣列不需使用隔絕層於接合製程中,完成接合 後之結構如圖2B所示。 異方性導電膜所使用的絕緣性黏著劑可以是熱塑型 (Thermoplastic)、熱固型(Thermosetting)或是上述兩 種材料所混合構成的。導電粒子可以是金屬顆粒、石墨纖維或是 高分子球體表面鍍上一層金屬所成的複合導電粒子。 圖式的簡要說明 圖1表示捲帶式晶粒接合結構的習知技術。 圖2A表示異方性導電膜和有空孔設計之金屬引腳陣列以捲帶式晶 粒接合方法形成的結構剖面圖。 圖2B表示異方性導電膜和沒有空孔設計之金屬引腳陣列以捲帶式 晶粒接合方法形成的結構剖面圖。 圖2C表示有空孔設計的金屬引腳陣列之上視圖。 圖2D表示沒有空孔設計金屬引腳陣列之上視圖。 圖3A表示異方性導電膜貼在一顆有金屬凸塊的積體電路元件的剖 面圖。 圖3B表示加熱頭與貼有異方性導電膜的積體電路元件接觸的剖面 圖。 圖3C表示表面貼附有異方性導電膜的積體電路元件經加熱頭預壓 合(Pre-bonding)後之剖面圖。 圖3D表示有空孔設計的金屬引腳陣列置於有異方性導電膜之積體 電路元件表面上並對完成對位,此異方性導電膜已完成預壓 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210 X 297公釐) 1^1 —-—I- - - - « - -I . - —^n I 二 - * 士交 -='I . I In - 0¾ 、v5 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A7 B7五、發明説明(3r ) 合。 圖3E表示以圖3D之結構再放置一片隔絕層於金屬引腳陣列之上, 加熱頭透過隔絕層加熱加壓。 圖4A表示有保護層的異方性導電膜貼附於無空孔設計金屬引腳陣 列的剖面圖。 圖4B表示加熱頭與無空孔設計金屬引腳陣列接觸的情形,此金屬 引腳陣列表面貼附一層有保護層的異方性導電膜。 圖4C表示貼附於金屬引腳陣列之異方性導電膜經預壓合並撕去表 面保護層之剖面圖。 圖4D表示在無空孔設計金屬引腳陣列之金屬引腳上加熱之捲帶式 晶粒接合結構剖面圖。 圖4E表示在積體電路元件表面加熱之捲帶式晶粒接合結構剖面 圖,此積體電路元件置於無空孔設計金屬引腳陣列之上。 圖5A表示異方性導電膜之結構剖面圖。 圖5B表示用於異方性導電膜內之石墨導電纖維形狀。 圖5C表示用於異方性導電膜內之金屬顆粒形狀。 圖5D表示用於異方性導電膜內之複合導電粒子形狀,此複合導電 粒子內部爲一高分子球體表面鍍上一層導電金屬。 圖5 E表示用於異方性導電膜內之多層複合導電粒子形狀,此多 層複合導電粒子爲複合導電粒子的表面再塗布另一種高分子 之結構。 圖6A表示有上下保護層的異方性導電膜之結構剖面圖。 圖6B表示只有單一保護層的異方性導電膜之結構剖面圖。 圖7表示無空孔設計金屬引腳陣列之上視圖。 11_'n^i I - I i - - I I 1-·- -I —I -- 8 士 -1 - 1- 1. - - - V V 、v* (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -Ί 一 301792 A7 經濟部中央標準局員工消费合作社印製 B7 五、發明説明(G) 最佳窗施例的說明 請參閱圖2A,2C,3A至3E ’ 5A至5E,6A及6B ’說明利用異方 性導電膜、有空孔設計金屬引腳陣列及捲帶式晶粒接合方法所形 成的接合結構之實施例。圖3纟表不—顆有金屬凸塊21的積體電路 元件20的剖面圖;在此實施例此金屬凸塊爲金凸塊。取適當長度 之異方性導電膜3G並置於積體電路元件20之表面,異方性導電膜 與所有金凸塊21接觸。異方性導電膜3G是由塗布在保護層51之上 的絕緣性黏著劑32及分布於絕緣性黏著劑之內的導電粒子31所構 成。 圖5 A表示由導電粒子31及絕緣性黏著劑3 2但無介電層所組成 異方性導電膜30之結構剖面圖。圇5B至5E舉例說明一些導電粒子 之種類。導電粒子可以是圖5B所表示之石墨導電纖維44、圖5C之 金屬顆粒41、圖5D之複合導電粒子,此複合導電粒子內部爲一高 分子球體41表面鍍上一層導電金屬42、或圖5 E之多層複合導電 粒子形狀,此多層複合導電粒子爲高分子球體41表面鍍上一層導 電金屬表面再塗布另一種高分子43之結構。圖6A及6B則舉例說明 —些異方性導電膜的形式。如圖6A所示,由分布於絕緣性黏著劑 32之內的導電粒子31所構成的異方性導電膜3〇可有保護層51、 52覆蓋於異方性導電膜之兩側。如圖6β所示,由分布於絕緣性黏 著劑32之內的導電粒子3丨所構成的異方性導電膜3〇可有保護層 51覆蓋於異方性導電膜之單側。由圖5Α可看出當依箭頭乃的方相 施加壓力’只有順著箭頭的方向可導電,但垂直於箭頭的方向仍 然是絕緣。 參閱圖3Β ’加熱頭與只有單邊保護層51之異方性導電膜30接 觸时口晒®。加顯丨〇㈣喊粒髓顏力,麵熱能至與 加熱頭接觸之物體。加熟頭以溫度⑹至⑽。C、壓力^至⑼Tagosa et al.'S patent application (1) .5.? 3 〖.ru · 4,9 63,002) describes the joint structure using conductive particles and insulating adhesive, Fujimoto's patent application (3- 639 7, Japan) describes the method of composite conductive particles, adhesive layer and flip chip bonding (Flip Chip Bonding). The patent applied for by Tsukagoshi et al. (US Pat. No. 5,00 1,542) describes a substrate composed of glass, synthetic resin 'metal' ceramics or a mixture of these materials; the central part of the substrate is a hollow hole for The structure of the thin-layer carrier or TAB. Tsukagoshi et al. Used deformable conductive particles' hard conductive particles and adhesives to form a conductive bond. The scale of the paper used in the case of the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210X2W public daughter) I n ^ i 1 --- I-I'- »—ϋ n ^ i-I-士-— ^ ϋ— — II ml ^ J.-0¾. I (Please read the precautions on the back before filling in this page) Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 301792 A7 ___B7_ V. Description of the invention (>) The structure and process of die bonding is a different and more flexible metal pin array architecture. The anisotropic conductive film used in the present invention is composed of an adhesive and various types of conductive particles > This is different from the description of the patent applied by Tsukagoshi et al. The process of forming conductive joints is also different from the method proposed by Tsukagoshi et al. In his patent application. Tsukagoshi et al. Describe in their patent application (US Pat. No 4,470, 657) the use of anisotropic conductive films composed of conductive particles and adhesives of various sizes. The tape-bonded die bonding method is invented here It is not mentioned in the patent. Tsukagoshi et al.'S patent application (U.S. Pat_No 4,731,282) is a description of insulating adhesives. Brief description of the invention The structure of a traditional tape-and-reel die bond (TAB) is shown in FIG. 1, the pin array is composed of metal pins 22; this metal pin may be copper, and the metal pin is attached to the first dielectric Layer 23; This dielectric layer may be Polyimide, the inner end of the metal pin and the conductive bump 21; this conductive bump may be a gold (Au) bump. The gold bumps are plated on the aluminum oxide input / output terminals of the integrated circuit element 20 by electroplating. The thermal energy is transferred to the metal pins in the metal pin array with the set temperature, pressure and time parameters through the heating head (Thermode) 10, so that the inner end of the gold pin leads and the gold bumps form a conductive bond. High temperature is necessary in the traditional tape-and-reel die bonding process; usually between 450 and 550 ° C, so that the metal pins in the metal pin array and the gold bumps on the integrated circuit device Form a conductive bond. The difference in the coefficient of thermal expansion of the copper pin 22 and the dielectric layer 23 makes the subsequent external bonding process of the external pin and the substrate more difficult. The hardness of the metal bumps itself will transfer the force applied by the heating head to the integrated circuit components, causing the alumina pad to crack, to avoid this phenomenon 'control plus «I--ISI-I- I-— -I -士 又-I-I-I-! · ------- TW •, va (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X2 $ Mm) 1 1-A7 B7 du printed by the Ministry of Economy, Central Standards Bureau, Tooling and Consumers Co., Ltd. 5. Description of invention (3) The flatness of the thermal head end face (Planarity) and the parallelism between the end face and the metal bump (Parallelism) change It is very important, which will make the manufacturing cost of the equipment more expensive. The traditional tape-and-reel die bonding process must be encapsulated (Ecapsulation) after the process to prevent moisture from corroding and damaging the contacts. The main purpose of the present invention is to provide a low-cost tape-and-die bonding process. The new process uses lower temperatures and pressures, and completes the protection of the sealant while the contacts are formed. A further object of the invention of the present invention is to provide a low-cost tape-and-reel die-bonding structure that utilizes a lower-cost tape-reel-to-die bonding process; it is formed at the junction with lower temperature and pressure At the same time complete the protection of sealant. These objectives are achieved through the use of an anisotropic conductive film, which is composed of conductive particles and an insulating adhesive. After the tape-die bonding process is completed, the conductive particles 31 in the anisotropic conductive film are interposed between the pin array by the metal pins 22 and the metal bumps on the integrated circuit element 2G; as shown in FIGS. 2A and 2B It is shown that the conductive particles have compensation for the parallelism variation of the gold bumps and the heating head, so the pressure used in the bonding process can be reduced, which is about 20 to 40 kg / cm2. When the conductive joint is formed, the insulating adhesive 32 wraps around the contact to form a sealant, which protects the contact from corrosion and mechanical damage caused by a large amount of moisture. The temperature required for the bonding process is between 15G and 18G ° C. After the adhesive is cured, the joint can maintain the joint state. The metal pin array may have a hole design as shown in FIG. 2C. The metal pin array is composed of metal pins 22; the metal pin may be copper, and the metal pin is attached to the dielectric layer 23; the dielectric layer may be Polyethyleneamide, a junction area 75 around the inner edge of the dielectric layer 73, this junction area has no dielectric layer, and the tail end 74 of the inner pin extends toward the area without the dielectric layer. This type of pin array needs to use an insulating layer composed of metal foil 27 and polyethylene 25, so that the heating head will not interact with the adhesive, and after completion of bonding — ^ 1----III-- HH m ^^ 1 ml 1 VV _, T (Please read the precautions on the back and fill in this page first) This paper size is applicable to the Chinese National Standard (CNS> A4 specification (210X297 mm) -5- Central Bureau of Standards, Ministry of Economic Affairs Employee Consumer Cooperative Seal A7 B7 Fifth, the structure of the invention (¥) is shown in Figure 2A. The metal pin array can also be in the form shown in Figure 2D, this form of metal pin array has no hole design, metal lead The pin 22 is attached to the entire dielectric layer 23. This type of metal pin array does not require an isolation layer in the bonding process, and the structure after bonding is shown in FIG. 2B. The anisotropic conductive film is used The insulating adhesive can be Thermoplastic, Thermosetting, or a mixture of the above two materials. The conductive particles can be metal particles, graphite fibers, or polymer spheres coated with a layer of metal Composite conductive particles Brief Description of the Drawings Figure 1 shows the conventional technology of the tape-and-reel die bonding structure. FIG. 2A shows the structure of the anisotropic conductive film and the metal pin array with hollow holes designed by the tape-reel and die bonding method. Cross-sectional view. FIG. 2B shows the cross-sectional view of the structure of the anisotropic conductive film and the metal pin array without void design formed by the tape-and-reel die bonding method. FIG. 2C shows the top view of the metal pin array with void design Figure 2D shows a top view of a metal pin array without holes. Figure 3A shows a cross-sectional view of an integrated circuit element with an anisotropic conductive film attached to a metal bump. Figure 3B shows a difference between the heating head and the paste Cross-sectional view of the contact of the integrated circuit element of the square conductive film. FIG. 3C shows a cross-sectional view of the integrated circuit element with the anisotropic conductive film attached to the surface after pre-bonding by the heating head. FIG. 3D shows The metal pin array with holes is placed on the surface of the integrated circuit element with an anisotropic conductive film and the alignment is completed. The anisotropic conductive film has been pre-pressed. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specifications (210 X 297 mm) 1 ^ 1 —-— I----«--I.-— ^ N I 2-* Shijiao-= 'I. I In-0¾, v5 (please read the notes on the back first (Fill in this page) A7 B7 Printed by the National Bureau of Standards, Ministry of Economic Affairs Consumer Cooperative V. Description of invention (3r). Figure 3E shows the structure shown in Figure 3D, and then an insulation layer is placed on the metal pin array. Heating head Heating and pressing through the insulating layer. FIG. 4A shows a cross-sectional view of the anisotropic conductive film with a protective layer attached to a metal pin array with no holes. Fig. 4B shows a situation where the heating head is in contact with a metal pin array with no void design, and an anisotropic conductive film with a protective layer is attached to the surface of the metal pin array. Fig. 4C shows a cross-sectional view of the anisotropic conductive film attached to the metal pin array after pre-pressing and tearing off the surface protective layer. Fig. 4D shows a cross-sectional view of a tape-bonded die bonding structure heated on metal pins of a metal pin array with no holes. Fig. 4E shows a cross-sectional view of a tape-bonded die bonding structure heated on the surface of an integrated circuit element. The integrated circuit element is placed on a metal pin array with no void design. 5A shows a cross-sectional view of the structure of an anisotropic conductive film. Fig. 5B shows the shape of the graphite conductive fiber used in the anisotropic conductive film. FIG. 5C shows the shape of metal particles used in the anisotropic conductive film. Fig. 5D shows the shape of the composite conductive particles used in the anisotropic conductive film. The composite conductive particles are coated with a layer of conductive metal on the surface of a polymer sphere. Fig. 5E shows the shape of the multi-layer composite conductive particles used in the anisotropic conductive film. The multi-layer composite conductive particles have a structure in which another polymer is coated on the surface of the composite conductive particles. 6A shows a cross-sectional view of the structure of an anisotropic conductive film with upper and lower protective layers. 6B shows a cross-sectional view of the structure of an anisotropic conductive film with only a single protective layer. Fig. 7 shows an upper view of a metal pin array with no holes. 11_'n ^ i I-I i--II 1- ·--I —I-8 ± -1-1- 1.---VV, v * (Please read the precautions on the back before filling this page ) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm)-Ί 一 301792 A7 Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative B7 V. Invention description (G) Please refer to the description of the best window example 2A, 2C, 3A to 3E '5A to 5E, 6A and 6B' illustrate an embodiment of a bonding structure formed by using an anisotropic conductive film, a hole design metal pin array, and a tape and die bonding method. Fig. 3 shows a cross-sectional view of an integrated circuit element 20 having metal bumps 21; in this embodiment, the metal bumps are gold bumps. The anisotropic conductive film 3G of an appropriate length is taken and placed on the surface of the integrated circuit element 20, and the anisotropic conductive film is in contact with all the gold bumps 21. The anisotropic conductive film 3G is composed of an insulating adhesive 32 coated on the protective layer 51 and conductive particles 31 distributed in the insulating adhesive. Fig. 5A shows a cross-sectional view of the structure of an anisotropic conductive film 30 composed of conductive particles 31 and insulating adhesive 32 but no dielectric layer. Examples 5B to 5E illustrate some types of conductive particles. The conductive particles may be graphite conductive fibers 44 shown in FIG. 5B, metal particles 41 in FIG. 5C, and composite conductive particles in FIG. 5D. The composite conductive particles are coated with a layer of conductive metal 42 on the surface of a polymer sphere 41, or FIG. 5 The shape of the multi-layer composite conductive particles of E. The multi-layer composite conductive particles have a structure in which a layer of conductive metal is coated on the surface of the polymer sphere 41 and then another polymer 43 is coated. 6A and 6B illustrate some forms of anisotropic conductive films. As shown in FIG. 6A, the anisotropic conductive film 30 composed of the conductive particles 31 distributed within the insulating adhesive 32 may have protective layers 51, 52 covering both sides of the anisotropic conductive film. As shown in FIG. 6β, the anisotropic conductive film 30 composed of the conductive particles 3 distributed in the insulating adhesive 32 may have a protective layer 51 covering one side of the anisotropic conductive film. It can be seen from FIG. 5A that when pressure is applied in accordance with the direction of the arrow, only the direction of the arrow can conduct electricity, but the direction perpendicular to the arrow is still insulated. Refer to Fig. 3B 'Mouth Exposure® when the heating head is in contact with the anisotropic conductive film 30 having only one-sided protective layer 51. Add 丨 〇 ㈣ call for the strength of the medulla, the surface heat energy to the object contacting the heating head. Add cooked head to temperature ⑹ to ⑽. C, pressure ^ to ⑼

度ϋ 中國 ® 家eNS :297公蝥) 一(? 一 :--I I - - I. _ I -1- - •士又' I HI ill 1 ...... n^i ^ϋ» • US. 、τ (請先閱讀背面之注意事項再填寫本頁) __B7_ 五、發明説明(7) kg/cm2及3至5秒的時間將異方性導電膜預熱。此預熱步驟使絕 緣性黏著劑輕微地流動並將金凸塊21完全覆蓋,然後將異方性導 電膜之保護層51撕去,如圖3C所示。 接下來的步驟如圖3D所示,圖3D表示具有金屬導電引腳22之 引腳陣列貼附在第一種介電層23,置於有異方性導電膜3G之上, 並使金屬導電引腳22之內端在積體電路元件20之金凸塊21上。在 此實施例中之金靥導電引腳22是銅而的一種介電層23是聚乙醯 氨。引腳陣列之上視圖如圖2C所示,圖2C。介電層內緣四週73之 接合區域75,此接合區域沒有介電層,內部引腳22之尾端向沒有 介電層區域延伸》內部引腳之尾端向沒有介電層區域延伸之現象 仍可在圖3D中發現。 下一步驟如圖3E所示,一種有金屬箔片27之隔絕層貼附於第 二種介電層’在此實施例中,第二種介電層25是聚乙醯氨而金屬 箔片27是鋁。此隔絕層放置於空孔或沒有第—種介電層之引腳陣 列區域’在整個引腳陣列內部區域四周,靠近空孔邊界,隔絕層 之第二種介電層25與第一種介電層23接觸,隔絕層之第二種介電 層25將金屬箔片27與引腳陣列分開。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 下一步驟如圖3E所示,加熱頭1〇與隔絕層之金屬箔片27接 觸,加熱頭以溫度150至i70°C、壓力20至40kg/Cm2及時間5至 20秒傳遞熱能至隔絕層、引腳陣列、金凸塊及積體電路元件組装 如圖3E ,至此整個圖2A之接合結構完成。在整個接合製程中加熱 頭溫度將上升至28Q至3QG°C之間。 在前述實施例中所形成之完整接合結構如圖2A所示,金凸塊 21是以電鍍的方法長於積體電路元件2〇之氧化鋁輸入/輸出端。 引腳陣列之銅引腳22內端被定位以至於每根引腳內端與每個金凸 塊开^成接合對。當此種組裝受壓力作用後,在引腳內端與金凸塊 之每一接合對間便有許多異方性導電膜內之導電粒子31。導電粒 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 經濟部中央標準局員工消費合作社印袈 A7 ___B7_ 五、發明説明(β ) 子31使引腳內端與金凸塊之每一接合對能導電。隔絕層之第二種 介電層2 5與異方性導電膜內之絕緣性黏著劑及在空孔四週之第一 種介電層23接觸。絕緣性黏著劑因組裝過程中,加熱頭傳遞熱及 壓力而流動,使接合結構封膠並因黏著劑硬化使整個接合點得以 保持導電接觸狀態》絕緣性黏著劑是環氧樹脂(Epoxy),也可 以是熱塑型、熱固型或是上述兩種材料所混合構成的。在此實施 例中所使用之隔絕層是鋁箔27貼附於高分子層25之上,也可以是 Si icone Rubber貼附於高分子層或其它類似材料之上。 接下來請參閱圖2B,2D,4A至4E,5A至5E,6A及6B,說明 利用異方性導電膜、無空孔設計金屬引腳陣列及捲帶式晶粒接合 方法所形成的接合結構之實施例。圖4A表示有單邊保護層51的 異方性導電膜3 0貼附於由第一種介電層2 3及金屬引腳2 2之無空孔 設計引腳陣列之上的剖面圖β圖20表示此實施例中之金屬引腳陣 列上視圖。金屬引腳22貼附於第一種介電層23之上,此介電層無 空孔設計。金屬引腳之內端貼附於第一種介電層23之上。 圖5 Α表示由導電粒子31及絕緣性黏著劑32但無介電層所組成 異方性導電膜30之結構剖面圖。圖58董5E舉例說明一些導電粒子 之種類。導電粒子可以是圖5B所表示之石墨導電纖維44、圖5C之 金屬顆粒41 '圖5D之複合導電粒子,此複合導電粒子內部爲一高 分子球體41表面鍍上一層導電金屬42、或圖5 E之多層複合導電、 粒子形狀,此多層複合導電粒子爲高分子球體41表面鍍上一層導 電金屬表面再塗布另一種高分子43之結構。圖6A及6B則舉例說明 一些異方性導電膜的形式。如圖6A所示,由分布於絕緣性黏著劑 3 2之內的導電粒子3 1所構成的異方性導電膜3 0可有保護層5 1、 52覆蓋於異方性導電膜之兩側。如圖6B所示’由分布於絕緣性黏 著劑32之內的導電粒子31所構成的異方性導電膜30可有保護層 512覆蓋於異方性導電膜之單側。由圖5A可看出當依箭頭75的方 本紙張尺度適用中國囡&準(CNS ) A4規格(210X 297公釐)~ ~~" · " I I I - - I- -I I I- < -- - - I - - II -. 丁 • 0¾ 、τ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ___B7五、發明説明(7) 子31使引腳內端與金凸塊之每一接合對能導電。隔絕層之第二種 介電層25與異方性導電膜內之絕緣性黏著劑及在空孔四週之第一 種介電層23接觸。絕緣性黏著劑因組裝過程中,加熱頭傳遞熱及 壓力而流動,使接合結構封膠並因黏著劑硬化使整個接合點得以 保持導電接觸狀態。絕緣性黏著劑是環氧樹脂(Epoxy),也可 以是熱塑型、熱固型或是上述兩種材料所混合構成的》在此實施 例中所使用之隔絕層是鋁箔27貼附於高分子層25之上,也可以是 Slicone Rubber貼附於高分子層或其它類似材料之上。 接下來請參閱圇2B,2D,4A至4E,5A至5E,6A及6B,說明 利用異方性導電膜、無空孔設計金靥引腳陣列及捲帶式晶粒接合 方法所形成的接合結構之實施例。圖4A表示有單邊保護層51的 異方性導電膜30貼附於由第一種介電層23及金屬引腳22之無空孔 設計引腳陣列之上的剖面圖。圖2D表示此實施例中之金屬引腳陣 列上視圖》金屬引腳22貼附於第一種介電層23之上,此介電層無 空孔設計。金屬引腳之內端貼附於第一種介電層23之上。 圖5A表示由導電粒子31及絕緣性黏著劑32但無介電層所組成 異方性導電膜30之結構剖面圖。圖5B星5E舉例說明一些導電粒子 之種類。導電粒子可以是圖5Β所表示之石墨導電纖維44、圖5C之 金屬顆粒41、圖5D之複合導電粒子,此複合導電粒子內部爲一高 分子球體41表面鍍上一層導電金屬42、或圖5 Ε之多層複合導電 粒子形狀,此多層複合導電粒子爲高分子球體41表面鏟上一層導 電金屬表面再塗布另一種高分子43之結構。圖6Α及6Β則舉例說明 一些異方性導電膜的形式。如圖6Α所示,由分布於絕緣性黏著劑 32之內的導電粒子31所構成的異方性導電膜30可有保護層51、 52覆蓋於異方性導電膜之兩側。如圖6Β所示,由分布於絕緣性黏 著劑32之內的導電粒子31所構成的異方性導電膜30可有保護層 512覆蓋於異方性導電膜之單側。由圖5Α可看出當依箭頭75的方 I--------- ά------、玎------^ (請先閱讀背面之注意事項再填寫本頁) (CNS ) Α4规格(210X297公釐) 一//一 A7 _____B7 五、發明説明(P) 電路元件2G之另一面,金凸塊21是以電鍍的方法長於積體電路元 件20之氧化鋁輸入/輸出端,加熱頭以溫度15〇至i7〇°c、壓力2〇 至40kg/cm2及時間5至20秒對此種組裝加熱,完成後之接合結構 如圖2B所示。 在前述實施例中所形成之完整接合結構如圖2B所示,金凸塊 21是以電鍍的方法長於積體電路元件20之氧化鋁輸入/輸出端。 引腳陣列之銅引腳22內端被定位以至於每根引腳內端與每個金凸 塊形成接合對。當此種組裝受壓力作用後,在引腳內端與金凸塊 之每一接合對間便有許多異方性導電膜內之導電粒子31。導電粒 子31使引腳內端與金凸塊之每一接合對能導電。絕緣性黏著劑因 組裝過程中,加熱頭傳遞熱及壓力而流動,使接合結構封膠並因 黏著劑硬化使整個接合點得以保持導電接觸狀態。絕緣性黏著劑 是環氧樹脂(Epoxy),也可以是熱塑型、熱固型或是上述兩種 材料所混合構成的。 在此實施例之種方法及結構中,引腳陣列之引腳內端可以是 面矩陣方式如圖7所示。在引腳陣列中引腳22之引腳內端74貼附 於沒有空孔設計之第一種介電層23之上。在此例中,引腳22及引 腳內端74是銅。 雖然以±_係以_實_絲述本的特徵,然而凡 熟知此技_人士均可以了解,尙雛多_或形式的修改,仍 可能落於本卿___之內,_本之麵自不當限 於以上的實肺II ,獅以麵爲限 - 一_.. 1 _?〇7/八格) 本紙張尺度適用中國國家榡準(CNS ) A4规格(2丨(>〆- (請先閲讀背面之注意事項再填寫本頁) -裝· -a 經濟部中央標隼局員工消費合作社印製Degree ϋ China® home eNS: 297 male cane) One (? One: --II--I. _ I -1--• Shi You 'I HI ill 1 ...... n ^ i ^ ϋ »• US. Τ (please read the precautions on the back before filling in this page) __B7_ V. Description of the invention (7) kg / cm2 and 3 to 5 seconds to preheat the anisotropic conductive film. This preheating step insulates The adhesive flows slightly and completely covers the gold bumps 21, and then the protective layer 51 of the anisotropic conductive film is torn off, as shown in FIG. 3C. The next steps are shown in FIG. 3D, which shows that the metal The pin array of the conductive pins 22 is attached to the first dielectric layer 23 and is placed on the anisotropic conductive film 3G, and the inner ends of the metal conductive pins 22 are in the gold bump of the integrated circuit element 20 On block 21. In this embodiment, the gold-lead conductive pins 22 are copper and a dielectric layer 23 is polyethylene. The top view of the pin array is shown in Figure 2C and Figure 2C. Inside the dielectric layer The bonding area 75 around the edge 73, this bonding area has no dielectric layer, and the end of the inner pin 22 extends toward the area without the dielectric layer. The phenomenon that the tail end of the inner pin extends toward the area without the dielectric layer Found in 3D. The next step is shown in FIG. 3E. An insulating layer with a metal foil 27 is attached to the second dielectric layer. In this embodiment, the second dielectric layer 25 is polyvinyl amide The metal foil 27 is aluminum. This isolation layer is placed in the hole or the pin array area without the first type dielectric layer around the entire area of the pin array, close to the boundary of the hole, the second type of insulation layer The electrical layer 25 is in contact with the first dielectric layer 23, and the second dielectric layer 25 of the insulating layer separates the metal foil 27 from the pin array. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the back side first (Notes are required to fill out this page) The next step is shown in Figure 3E. The heating head 10 is in contact with the metal foil 27 of the insulating layer. The heat energy is transferred to the insulation layer, pin array, gold bumps and integrated circuit components in 20 seconds as shown in Figure 3E, and the entire bonding structure of Figure 2A is completed. The temperature of the heating head will rise to 28Q to 3QG ° throughout the bonding process Between C. The complete joint structure formed in the foregoing embodiment is shown in FIG. 2A The gold bump 21 is longer than the aluminum oxide input / output end of the integrated circuit element 20 by electroplating. The inner ends of the copper pins 22 of the pin array are positioned so that the inner end of each pin and each gold bump When the assembly is subjected to pressure, there are many conductive particles 31 in the anisotropic conductive film between each joint pair of the inner end of the pin and the gold bump. The conductive particles are of paper size Applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 A_ ___B7_ Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A5 ___B7_ Fifth, the invention description (β) sub 31 enables each joint of the inner end of the pin to the gold bump Conductive. The second dielectric layer 25 of the insulating layer is in contact with the insulating adhesive in the anisotropic conductive film and the first dielectric layer 23 around the hole. The insulating adhesive flows due to the heat and pressure transmitted by the heating head during the assembly process, so that the joint structure is sealed and the entire joint is kept in conductive contact due to the hardening of the adhesive. The insulating adhesive is epoxy (Epoxy), It can also be a thermoplastic type, a thermosetting type or a mixture of the above two materials. The insulating layer used in this embodiment is an aluminum foil 27 attached to the polymer layer 25, or Si icone Rubber may be attached to the polymer layer or other similar materials. Next, please refer to FIGS. 2B, 2D, 4A to 4E, 5A to 5E, 6A and 6B, to illustrate the bonding structure formed by using anisotropic conductive film, non-void design metal pin array and tape-and-reel die bonding method的 实施 例。 Examples. FIG. 4A shows a cross-sectional view β of an anisotropic conductive film 30 with a single-sided protective layer 51 attached to a pin array composed of the first dielectric layer 23 and the metal pin 22 without holes. 20 represents the top view of the metal pin array in this embodiment. The metal pin 22 is attached to the first type dielectric layer 23, and this dielectric layer has no void design. The inner end of the metal pin is attached to the first type dielectric layer 23. Fig. 5A shows a cross-sectional view of the structure of an anisotropic conductive film 30 composed of conductive particles 31 and an insulating adhesive 32 without a dielectric layer. Figure 58 Dong 5E illustrates some types of conductive particles. The conductive particles may be graphite conductive fibers 44 shown in FIG. 5B, metal particles 41 in FIG. 5C, and composite conductive particles in FIG. 5D. The composite conductive particles are coated with a layer of conductive metal 42 on the surface of a polymer sphere 41, or FIG. 5 The multi-layer composite conductive and particle shape of E. This multi-layer composite conductive particle is a structure in which the surface of the polymer sphere 41 is coated with a layer of conductive metal and then another polymer 43 is coated. 6A and 6B illustrate some forms of anisotropic conductive films. As shown in FIG. 6A, the anisotropic conductive film 30 composed of the conductive particles 3 1 distributed in the insulating adhesive 3 2 may have protective layers 5 1, 52 covering both sides of the anisotropic conductive film . As shown in FIG. 6B, the anisotropic conductive film 30 composed of the conductive particles 31 distributed in the insulating adhesive 32 may have a protective layer 512 covering one side of the anisotropic conductive film. It can be seen from FIG. 5A that when the square paper size according to arrow 75 is applicable to the Chinese standard (CNS) A4 specification (210X 297 mm) ~ ~~ " · " III--I- -II I- <---I--II-. Ding 0¾, τ (please read the precautions on the back before filling out this page) A7 ___B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (7) Child 31 Each conductive pair of the inner end of the pin and the gold bump can be conductive. The second type dielectric layer 25 of the insulating layer is in contact with the insulating adhesive in the anisotropic conductive film and the first type dielectric layer 23 around the hole. The insulating adhesive flows due to the heat and pressure transmitted by the heating head during the assembly process, so that the joint structure is sealed and the entire joint is maintained in conductive contact due to the hardening of the adhesive. The insulating adhesive is epoxy (Epoxy), it can also be thermoplastic, thermosetting or a mixture of the above two materials. The insulating layer used in this embodiment is the aluminum foil 27 attached to the high On the molecular layer 25, it is also possible to apply Silicone Rubber to the polymer layer or other similar materials. Next, please refer to 2B, 2D, 4A to 4E, 5A to 5E, 6A and 6B, to illustrate the use of anisotropic conductive film, void-free design of gold tantalum pin array and taped die bonding method Example of structure. FIG. 4A shows a cross-sectional view of an anisotropic conductive film 30 with a single-sided protective layer 51 attached to a pin array designed by the first dielectric layer 23 and the metal pin 22 without holes. FIG. 2D shows the top view of the metal pin array in this embodiment. The metal pins 22 are attached to the first type dielectric layer 23, and the dielectric layer has no void design. The inner end of the metal pin is attached to the first type dielectric layer 23. Fig. 5A shows a cross-sectional view of the structure of an anisotropic conductive film 30 composed of conductive particles 31 and an insulating adhesive 32 without a dielectric layer. Figures 5B and 5E illustrate some types of conductive particles. The conductive particles may be graphite conductive fibers 44 shown in FIG. 5B, metal particles 41 in FIG. 5C, and composite conductive particles in FIG. 5D. The composite conductive particles are coated with a layer of conductive metal 42 on the surface of a polymer sphere 41, or FIG. 5 The shape of the multi-layer composite conductive particles of Ε is a structure in which a layer of conductive metal is shoveled on the surface of the polymer sphere 41 and then another polymer 43 is coated. 6A and 6B illustrate some forms of anisotropic conductive films. As shown in FIG. 6A, the anisotropic conductive film 30 composed of the conductive particles 31 distributed in the insulating adhesive 32 may have protective layers 51, 52 covering both sides of the anisotropic conductive film. As shown in FIG. 6B, the anisotropic conductive film 30 composed of the conductive particles 31 distributed within the insulating adhesive 32 may have a protective layer 512 covering one side of the anisotropic conductive film. It can be seen from Fig. 5Α that when I follow the arrow 75, I --------- ά ------, 玎 ------ ^ (Please read the precautions on the back before filling this page ) (CNS) Α4 specification (210X297mm) 1 // 1A7 _____B7 5. Description of invention (P) On the other side of the circuit element 2G, the gold bump 21 is longer than the aluminum oxide input of the integrated circuit element 20 by electroplating At the output end, the heating head heats this assembly at a temperature of 15 ° to i70 ° C, a pressure of 20 to 40 kg / cm 2 and a time of 5 to 20 seconds. The completed joint structure is shown in FIG. 2B. The complete bonding structure formed in the foregoing embodiment is shown in FIG. 2B. The gold bumps 21 are longer than the aluminum oxide input / output terminals of the integrated circuit element 20 by electroplating. The inner ends of the copper pins 22 of the pin array are positioned so that the inner ends of each pin form a bonding pair with each gold bump. When this type of assembly is subjected to pressure, there are many conductive particles 31 in the anisotropic conductive film between each joint pair of the inner end of the pin and the gold bump. The conductive particles 31 make each bonding pair of the inner end of the pin and the gold bump conductive. The insulating adhesive flows during the assembly process when the heating head transmits heat and pressure, so that the joint structure is sealed and the entire joint is maintained in conductive contact due to the hardening of the adhesive. The insulating adhesive is epoxy resin, which can also be thermoplastic, thermosetting or a mixture of the above two materials. In the method and structure of this embodiment, the inner ends of the pins of the pin array may be in a surface matrix manner as shown in FIG. 7. In the pin array, the inner end 74 of the pin 22 is attached to the first dielectric layer 23 without a hole design. In this example, the pin 22 and the inner end 74 of the pin are copper. Although the characteristics of the text are described in terms of ± _ 实 _ 丝 _, anyone familiar with this technique_ can understand that the modification of the form or the form may still fall within Ben Qing___, _ 本 之The face is improperly limited to the above real lung II, the lion is limited to the face-one _ .. 1 _? 〇7 / eight grids) This paper scale is applicable to China National Standard (CNS) A4 specifications (2 丨 (> 〆- (Please read the precautions on the back before filling out this page)-installed · -a Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs

Claims (1)

301792 A8 B8 C8 D8 i修正士 I女本年月g補充防.8. tr) 、申請專利範圍 經濟部中央揉孳扃員工消費合作社印裝 申請專利笳囿 1種形成接合結構的方法,係包含: 準備一具有導電性接合凸塊之積體電路元件; 準備一異方性導電膜是由塗布在保護層之上的絕緣性黏著劑及 分布於絕緣性黏著劑之內的導電粒子所組成; 準備一由第一種介電材料所作成之第一種介電層; 準備一由許多導電引腳貼附在第一種介電層所組成之引腳陣 列’此引腳陣列之導電引腳具有內引腳端及外引腳端,且第一 種介電層之內部四週具有一沒有第一種介電層材料之空孔,而 內引腳端越過內部四週向沒有第一種介電層材料之空孔延伸; 準備一由一層支持金屬貼附在第二種介電層之隔絕膜; 準備一加熱頭’能經由所選擇之時間、溫度及壓力而提供熱 倉b ; 放置一片異方性導電膜於前述之積體電路元件之上,使其中許 多導電粒子與導電性接合凸塊接觸; 將前述之加熱頭以第一階段之時間將第一階段之溫度及第一階 段之壓力經由保護層傳遞熱能至異方性導電膜; 撕去前述之保護膜層; 形成許多接合對,這些接合對係由前述內引腳之一與前述導電 性接合凸塊之一所組成,而前述之導電粒子以放置前述之引腳 陣列於前述之分布於絕緣性黏著劑之內的導電粒子之上,以致 於內引腳端處與導電性接合凸塊之上的方法,使導電粒子處於 前述內引腳之一與前述導電性接合凸塊之一之間: 放置一片已做好的隔絕膜於前述之引腳陣列之上,使做好的隔 絕膜覆蓋前述之空孔,而前述之第二種介電材料層是介於前述 引腳陣列及前述支持金屬層之間;以及 本紙張尺度適用中國國家標準(CNS ) Λ4現格(210X297公釐) --------藥------V—-----^ (請先閱讀背面之注意事項JS-¾本頁) 經濟部中央標準局貞工消费合作社印製 A8 B8 C8 D8六、申請專利範圍 將前述之加熱頭以第二階段之時間將第二階段之溫度及第二階 段之壓力傳遞熱能至前述之隔絕膜、絕緣介電層及接合對,使 前述之每一接合對在之前述之導電粒子、前述之內引腳端及前 述導電性凸塊間形成導電接合》 2. 如申請專利範圍第1項所述之方法,其中之第一階段溫度爲60 至lGlTC、第一階段壓力爲5至1G kg/cm2及第一階段時間爲3 至5秒。 3. 如申請專利範圍第1項所述之方法,其中之第二階段溫度爲 150至180°C、第二階段壓力爲20至40 kg/cm2及第二階段時 間爲5至20秒。 4. 如申請專利範圍第1項所述之方法,其中之導電接合凸塊爲 金。 5. 如申請專利範圍第1項所述之方法,其中之導電引腳爲銅。 6. 如申請專利範圍第1項所述之方法,其中之導電粒子爲金屬。 7. 如申請專利範圍第1項所述之方法,其中之導電粒子爲一高分 子球體表面鍍上一層導電金屬。 8. 如申請專利範圍第1項所述之方法,其中之導電粒子爲第一種 高分子球體表面鍍上一層導電金屬再於導電金屬表面塗布第二 種高分子。| 9. 如申請專利範圍第1項所述之方法,其中之導電粒子爲石墨。 10. 如申請專利範圍第1項所述之方法,其中之支持金屬爲鋁而 第二種介電層爲聚乙醯氨。 U.如申請專利範圍第1項所述之方法,其中之第一種介電層由 聚乙醯氨所構成》 (請也閱讀背面之注意事項i ,馬本頁) 、17 線 (CNS ) A4規格(210X297公釐) 一 1砵一 Α8 Β8 C8 D8 301792 π、申請專利範圍 12·—種形成接合結構的方法,係包含: 準備一具有導電性接合凸塊之積體電路元件; 準備一異方性導電膜是由塗布在保護層之上的絕緣性黏著劑及 分布於絕緣性黏著劑之內的導電粒子所組成; 準備一介電層; 準備一由許多導電引腳貼附在第一種介電層所組成之引腳陣 列,此引腳陣列之導電引腳具有內引腳端及外引腳端; 準備一加熱頭,能經由所選擇之時間、溫度及壓力而提供熱 能; 放置一片異方性導電膜於前述之引腳陣列之上,使其中許多分 布於絕緣性黏著劑導電粒子與內引腳端接觸: 將前述之加熱頭以第一階段之時間將第一階段之溫度及第一階 段之壓力經由保護層傳遞熱能至異方性導電膜; 撕去前述之保護膜層; 形成許多接合對,這些接合對係由前述內引腳之一與前述導電 性接合凸塊之一所組成,而前述之導電粒子以放置前述之引腳 陣列於前述之分布於絕緣性黏著劑之內的導電粒子之上,以致 於內引腳端處與導電性接合凸塊之上的方法,使導電粒子處於 .前述內引腳之一與導電性接合凸塊之一之間;以及 將前述之加熱頭以第二階段之時間將第二階段之溫度及第二階 段之壓力傳遞熱能至前述之隔絕膜、絕緣介電層及接合對,使 前述之每一接合對在之前述之導電粒子、前述之內引腳端及前 述導電性凸塊間形成導電接合》 13. 如申請專利範圍第12項所述之方法,其中之第一階段溫度爲 60至100°C、第一階段壓力爲5至10 kg/cm2及第一階段時間 爲3至5秒。 14. 如申請專利範圍第12項所述之方法,其中之第二階段溫度爲 本紙液尺度適用t國國家樣準(cns ) a4规格(mox 297公釐) -!ζ- 裝 、1Ti I 線 (請先閲讀背面之注意事項再:,舄本頁) 經濟部中央梂隼局員工消費合作社印裝 ABCD 經濟部中夬標準局男工消费合作社印製 々、申請專利範圍 150至18(3°C、第二階段壓力爲20至40 kg/cm2及第二階段時 間爲5至20秒。 15. 如申請專利範圍第12項所述之方法,其中之導電接合凸塊爲 金。 16. 如申請專利範圍第12項所述之方法,其中之導電引腳爲銅。 17. 如申請專利範圍第12項所述之方法,其中之導電粒子爲金 屬。 18. 如申請專利範圍第12項所述之方法,其中之導電粒子爲一高 分子球體表面鍍上一層導電金屬》 19. 如申請專利範圍第12項所述之方法,其中之導電粒子爲第一 種高分子球體表面鍍上一層導電金靥再於導電金靥表面塗布第 二種高分子。 . 20. 如申請專利範圍第12項所述之方法,其中之導電粒子爲石 细 « 墨。 21. 如申請專利範圍第12項所述之方法,其中之介電層由聚乙醯 氣所構成。 22. —種接合結構,係包含; 一種有許多導電性接合凸塊之積體電路元件; 一種由第一種介電材料所作成之第一種介電層; 一種由許多導電引腳貼附在第一種介電層所組成之引腳陣 列,此引腳陣列之導電引腳具有內引腳端及外引腳端; 許多接合對,這些接合對係由前述內引腳之一與前述導電性 接合凸塊之一所組成; 一種由導電粒子分布於絕緣性黏著劑所構成之異方性導電 膜,這些導電粒子被配置於每一接合對之內引腳端與導電性 接合凸塊之間;以及 許多接合對,其中每一接合對之內引腳端、每一接合對之導 (CNS ) A4*見格(210 X 297公釐) —丨t 一 ----------¾------,玎------^ (請先閱讀背面之注意事項再>/.烏本頁) 301792 A8 B8 C8 D8 申請專利托圍 電性接合凸塊及在前述每一接合對之內引腳端、每一接合對 之導電性接合凸塊之間之導電粒子形成導電性接合。 23. 如申請專利範圍第22項所述之接合結構,其中每一內引腳端 貼附在第一種介電層。 24. 如申請專利範圍第22項所述之接合結構,其中第一種介電層 具有內部四週沒有第一種介電層材料之空孔,且每一內引腳端 越過內部四週向此空孔延伸〇 25. 如申請專利範圍第24項所述之接合結構,更進一步之描述爲 由貼附在第二種介電材料層之支持金屬所形成之隔絕膜覆蓋前 述之空孔,前述第二種介電材料層與前述內引腳端接觸,前述 第二種介電材料層與前述第一種介電層接觸,前述第二種介電 材料層使前述支持金屬層與導電引腳絕緣。 26. 如申請專利範圍第22項所述之接合結構,其中之導電引腳爲 銅。 27. 如申請專利範圍第22項所述之接合結構,其中之導電接合凸 塊爲金。 . 校及術 封著5 幸作院 經濟部中央橾準局員工消費合作社印製 28. 如申請專利範圍第22項所述之接合結構,其中之導電粒子爲 金屬》 29. 如申請專利範圍第22項所述之接合結構,其中之導電粒子爲 一高分子球體表面鍍上一層導電金屬。 30. 如申請專利範圍第22項所述之接合結構,其中之導電粒子爲 第一種高分子球體表面鏟上一層導電金屬再於導電金屬表面塗 布第二種高分子。 31. 如申請專利範圍第22項所述之接合結構,其中之導電粒子爲 石墨。 32. 如申請專利範圍第22項所述之接合結構,其中之支持金屬爲 裝 訂 , 線 (請先閱讀背面之注意事項再丨"本頁) 本紙張尺度適用中國國家榡準(CNS ) Λ4規格(210X 297公釐) ABCD 六、申請專利範圍鋁而第二種介電層爲聚乙醯氨》33.如申請專利範圍第22項所述之接合結構,其中之第一種介電 層由聚乙醯氨所構成。 --^--------^------ir----- (請先閱讀背面之注意事項再4寫本頁) 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用t國國家標準(CNS ) A4規格(210X 297公釐) 一I ί301792 A8 B8 C8 D8 i Amendment I female this year g supplementary prevention. 8. tr), the scope of patent application The Central Ministry of Economic Affairs, the Ministry of Economic Affairs, the Employee Consumer Cooperative printed and applied for a patent to apply a method of forming a joint structure, which includes : Prepare an integrated circuit element with conductive bonding bumps; prepare an anisotropic conductive film composed of an insulating adhesive coated on the protective layer and conductive particles distributed in the insulating adhesive; Prepare a first dielectric layer made of the first dielectric material; prepare a pin array composed of many conductive pins attached to the first dielectric layer 'conductive pins of this pin array It has an inner pin end and an outer pin end, and there is a hole without the first dielectric layer material on the inner periphery of the first dielectric layer, while the inner pin end has no first dielectric layer across the inner periphery The hole of the layer material is extended; prepare an insulating film with a layer of supporting metal attached to the second dielectric layer; prepare a heating head that can provide a thermal chamber b through the selected time, temperature and pressure; place a piece of different Square conductive film On the aforementioned integrated circuit element, many of the conductive particles are brought into contact with the conductive bonding bumps; the aforementioned heating head transfers the heat energy of the first stage temperature and the first stage pressure through the protective layer at the time of the first stage To the anisotropic conductive film; tear off the aforementioned protective film layer; form many bonding pairs, which are composed of one of the inner leads and one of the conductive bonding bumps, and the aforementioned conductive particles are placed The aforementioned pin array is on the aforementioned conductive particles distributed in the insulating adhesive so that the conductive pin is located on one of the aforementioned inner pins at the end of the inner pin and on the conductive bonding bump Between one of the aforementioned conductive bonding bumps: place a prepared insulating film on the aforementioned pin array, so that the completed insulating film covers the aforementioned hole, and the aforementioned second dielectric material The layer is between the aforementioned pin array and the aforementioned supporting metal layer; and this paper scale is applicable to the Chinese National Standard (CNS) Λ4 present grid (210X297mm) -------- Pharmaceutical -------- V —----- ^ ( First read the notes on the back JS-¾ page) A8 B8 C8 D8 printed by the Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Scope of patent application The aforementioned heating head will be used for the second stage of the temperature and temperature The second stage of pressure transfers heat energy to the aforementioned insulating film, insulating dielectric layer and bonding pair, so that each bonding pair forms electrical conduction between the aforementioned conductive particles, the aforementioned inner pin ends and the aforementioned conductive bumps Joining "2. The method as described in item 1 of the patent application, wherein the first stage temperature is 60 to 1 GlTC, the first stage pressure is 5 to 1 G kg / cm2 and the first stage time is 3 to 5 seconds. 3. The method as described in item 1 of the patent application, wherein the second stage temperature is 150 to 180 ° C, the second stage pressure is 20 to 40 kg / cm2 and the second stage time is 5 to 20 seconds. 4. The method as described in item 1 of the patent application, wherein the conductive bonding bumps are gold. 5. The method as described in item 1 of the patent application, wherein the conductive pins are copper. 6. The method as described in item 1 of the patent application, wherein the conductive particles are metal. 7. The method as described in item 1 of the patent application, wherein the conductive particles are coated with a layer of conductive metal on the surface of a high molecular sphere. 8. The method as described in item 1 of the patent application, wherein the conductive particles are the first polymer sphere coated with a layer of conductive metal and then coated with a second polymer on the surface of the conductive metal. | 9. The method as described in item 1 of the patent application, wherein the conductive particles are graphite. 10. The method as described in item 1 of the patent application, wherein the supporting metal is aluminum and the second dielectric layer is polyvinyl amide. U. The method as described in item 1 of the scope of patent application, in which the first dielectric layer is composed of polyacetamide "(please also read the precautions on the back i, Ma page), 17 lines (CNS) A4 specification (210X297mm)-1 砵 一 A8 Β8 C8 D8 301792 π, patent application range 12 · a method of forming a bonding structure, which includes: preparing an integrated circuit element with conductive bonding bumps; preparing one The anisotropic conductive film is composed of an insulating adhesive coated on the protective layer and conductive particles distributed in the insulating adhesive; preparing a dielectric layer; preparing a plurality of conductive pins attached to the first A pin array composed of a dielectric layer. The conductive pins of the pin array have inner pin ends and outer pin ends; prepare a heating head, which can provide heat energy through the selected time, temperature and pressure; Place a piece of anisotropic conductive film on the aforementioned pin array, so that many of the conductive particles distributed in the insulating adhesive are in contact with the inner pin end: Put the aforementioned heating head at the first stage for the first stage temperature And the first-stage pressure transfers heat energy to the anisotropic conductive film through the protective layer; tears away the aforementioned protective film layer; forms many bonding pairs, which are formed by one of the inner leads and the conductive bonding bumps A method in which the aforementioned conductive particles are placed on the aforementioned pin array on the aforementioned conductive particles distributed in the insulating adhesive so that the inner pin ends are on the conductive bonding bumps , So that the conductive particles are between one of the aforementioned inner pins and one of the conductive bonding bumps; and the aforementioned heating head transfers the thermal energy to the temperature of the second stage and the pressure of the second stage to the second stage at the time of the second stage The aforementioned insulating film, insulating dielectric layer and bonding pair, forming a conductive bond between the aforementioned conductive particles, the aforementioned inner pin ends and the aforementioned conductive bumps of each aforementioned bonding pair 13. The method according to item 12, wherein the first-stage temperature is 60 to 100 ° C, the first-stage pressure is 5 to 10 kg / cm2, and the first-stage time is 3 to 5 seconds. 14. The method as described in item 12 of the scope of patent application, in which the second-stage temperature is based on the paper liquid standard and is applicable to the national sample standard (cns) a4 specification (mox 297 mm)-! Ζ- installed, 1Ti I line (Please read the precautions on the back before :, 舄 this page) Printed and printed by the employee consumer cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs ABCD Printed by the Male Workers Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics, patent application range 150 to 18 (3 ° C. The second stage pressure is 20 to 40 kg / cm2 and the second stage time is 5 to 20 seconds. 15. The method as described in item 12 of the patent application scope, in which the conductive bonding bumps are gold. 16. The method described in item 12 of the patent application, wherein the conductive pins are copper. 17. The method described in item 12 of the patent application, wherein the conductive particles are metal. 18. As stated in the item 12 of the patent application The method described, wherein the conductive particles are coated with a layer of conductive metal on the surface of a polymer sphere 19. The method described in item 12 of the patent application, wherein the conductive particles are coated with a layer of conductive on the surface of the first polymer sphere Jinyu then conductive The second polymer is coated on the surface of T. 20. The method as described in item 12 of the patent application, wherein the conductive particles are Shi fine ink. 21. The method as described in item 12 of the patent application, of which The dielectric layer is made of polyethylene gas. 22. A bonding structure consisting of: an integrated circuit element with many conductive bonding bumps; a first dielectric made of the first dielectric material Electrical layer; a pin array composed of many conductive pins attached to the first dielectric layer, the conductive pins of this pin array have inner pin ends and outer pin ends; many bonding pairs, these bonding The pair is composed of one of the inner leads and one of the conductive bonding bumps; an anisotropic conductive film composed of conductive particles distributed on the insulating adhesive, the conductive particles being arranged in each bonding pair Between the inner pin end and the conductive bonding bump; and many bonding pairs, where the inner pin end of each bonding pair and the guide of each bonding pair (CNS) A4 * see grid (210 X 297 mm) — 丨 t one ---------- ¾ ------玎 ------ ^ (Please read the precautions on the back first> /. Woo page) 301792 A8 B8 C8 D8 Patent pending electrical bonding bumps and pins within each of the aforementioned bonding pairs The conductive particles between the end and the conductive bonding bumps of each bonding pair form a conductive bond. 23. The bonding structure as described in item 22 of the patent application scope, in which each inner pin end is attached to the first Dielectric layer 24. The bonding structure as described in item 22 of the patent application scope, in which the first dielectric layer has voids without the first dielectric layer material on the inner periphery, and each inner pin end passes over the inner The periphery extends to this hole. The joint structure as described in item 24 of the patent application scope is further described as the insulating film formed by the supporting metal attached to the second dielectric material layer covering the aforementioned space Hole, the second dielectric material layer is in contact with the inner pin end, the second dielectric material layer is in contact with the first dielectric layer, and the second dielectric material layer allows the support metal layer to Conductive pins are insulated. 26. The joint structure as described in item 22 of the patent application, wherein the conductive pins are copper. 27. The bonding structure as described in item 22 of the patent application, wherein the conductive bonding bumps are gold. . School and Shufeng Seal 5 Printed by the Employee Consumer Cooperative of the Central Central Bureau of Economics of the Ministry of Economics 28. The joint structure as described in item 22 of the patent application, where the conductive particles are metal. 29. If the patent application is the 22nd The joint structure described in item 1, wherein the conductive particles are coated with a layer of conductive metal on the surface of a polymer sphere. 30. The joint structure as described in item 22 of the patent application, wherein the conductive particles are a layer of conductive metal on the surface of the first polymer sphere, and the second polymer is coated on the surface of the conductive metal. 31. The joint structure as described in item 22 of the patent application, wherein the conductive particles are graphite. 32. The joint structure as described in item 22 of the patent application scope, in which the supporting metal is binding, thread (please read the precautions on the back side first and then this page) This paper size is applicable to China National Standard (CNS) Λ4 Specifications (210X 297mm) ABCD VI. Patent application range aluminum and the second dielectric layer is polyacetamide "33. The bonding structure as described in item 22 of the patent application range, of which the first dielectric layer It is composed of polyethylene amide. -^ -------- ^ ------ ir ----- (Please read the precautions on the back first and then write 4) This paper is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The scale is applicable to the national standard (CNS) A4 specifications (210X 297 mm)
TW085101718A 1995-12-27 1996-02-08 Tape automated bonding method and structure thereof TW301792B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US08/579,511 US6008072A (en) 1995-12-27 1995-12-27 Tape automated bonding method
TW085101718A TW301792B (en) 1996-02-08 1996-02-08 Tape automated bonding method and structure thereof
JP8261714A JPH09223714A (en) 1995-12-27 1996-10-02 Bonded structure forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW085101718A TW301792B (en) 1996-02-08 1996-02-08 Tape automated bonding method and structure thereof

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TW301792B true TW301792B (en) 1997-04-01

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