經濟部中央橾準局員工消费合作社印製 A7 B7 五、發明説明（/ ) 〔發明領域〕 本發明係關於積體電路的製造方法，更特定地，本發 明係關於積體電路的製程中之接觸窗（contact)的形成方法 〇 [發明背景〕 在積體電路的製程中，當各種元件，如MOS, BJT等元 件，被形成於半導體基片上之後接著即是在該等元件之上 沉積一層介電薄膜材料，如BPTE0S等，以作爲金屬連線間 的介電層（Interconnect Dielectric)及晶片的保護層之 用。通常，爲了使BPTE0S等介電層有較佳之步階覆蓋性 (step coverage)，在沉積介電層之前會先沉積一層具有較 佳的間隙塡充性（gap filling)之底層（under layer)，如 PETE0S。另，爲了使介電層具有較平坦的表面以利後續之 光罩作業，該介電層上通常被塗覆（coating)—層旋施玻璃 (S0G)層。 一般沉積BPTE0S介電層的方法有兩種，一爲在高濃度 的臭氧（Hi 03 )的環境下來實施，另-種爲在低濃度的臭 氧（Low 03 )的環境下實施，且各有其優點與缺點。在高濃 度的臭氧下所沉積之BPTE0S因其品質較穩定故其在形成接 觸窗開口時*可形成較佳之碗狀開口 •而其缺點則是沉積 的速度較慢。相反的，在低濃度的臭氧下所沉積之BPTE0S 因其品質較不穩定故其無法形成理想之碗狀的接觸窗開口 ，而其優點則是沉積的速度較快。 -3 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I I n 丨裝 訂 I 知 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（yl 在積體電路的製程中，BPTEOS介電層沉積速度的快慢 直接影響到生產的產出效率，而接觸窗開口形狀是否理想 則影響到金屬接線連接之可靠度，亦即影響到整個半導體 元件製造的良率（yield)»如何在介電層的沉積程序與在接 觸窗開口的蝕刻程序中同時兼顧製造的效率，即以較快的 速度沉積介電層，與產品的良率，即形成理想的碗狀接觸 窗開口，兩者一直是目前半導體元件製造領域中亟欲突破 與克服之處。 〔發明槪要〕 因而，本發明的一主要的目的爲提供一種半導體元件 的製程其可同時以高的速率沉積介電層來提高生產效率並 可形成理想的碗形接觸窗開口來提高半導體元件的良率。 本發明的另一目的爲提供一種可鈾刻一理想的碗狀開 口之接觸窗（contact)的蝕刻方法。 依照本發明的目的，一種可在高的介電層沉積速率下 形成碗形的接觸窗開口之積體電路製造方法被揭示。本發 明之方法包括的步驟有：提供一半導體基質並於該半導體 基質之中及其上形成半導體元件；於該半導體元件之表面 上沉積一第一厚度的電漿強化四乙基磷矽酸酯（PETE0S )層 ;在該PETE0S層上沉積一第二厚度的硼磷四乙基磷矽酸酯 .(BPTEOS)層；對該BPTEOS層施以熱流（flow)處理；在該 BPTEOS層上塗佈一第三厚度的旋施玻璃（S0G)層；對該旋 施玻璃層施以固化（curing)處理；對該旋施玻璃層與 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ297公嫠） --------—裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消费合作社印裝 A7 B7 〜-----------------------------------------------------------------丨丨 __ 五、發明说明（>) BPTE0S層進行回蝕刻（etching back )作業，以回蝕刻一第 四厚度*該第四厚度大於第三厚度而小於第二厚度；對回 蝕刻後之BPTE0S層進行濕式緩衝氧化物蝕刻（Buffer Oxide E t c h ) ·以鈾刻一第五；進行接觸孔光阻覆蓋作業；對 滅44: 光阻施以硬烤（h a r d b/tcey處理以去除水分；進行均向及非 均向之接觸孔乾式蝕刻除光阻；及完成積體電路之製 ^«,^,<11111 — 造。 依據本發明的一個特徵，該BPTE0S層是在低〇3濃度的 環境下進行沉積。 依據本發明的另一個特徵，該濕式緩衝氧化物蝕刻是 用緩衝氧化蝕刻液作爲緩衝劑（B u f f e r A g e n t)，其比例爲 NH4 F:HF = 10 : 1 〇 依具本發明的一進一步的特徵*該PETOS層的第一厚度 爲2 0 0 0 A，該BPTE0S層的第二厚度爲9 0 0 0 A，該S0G層 的第三厚度爲1 3 5 0 A。 依據本發明的另一進一步的特徵，該回蝕刻的第四厚 度爲5QQQA，及該緩衝氧化物蝕刻之第五厚度爲10QQA。 依據本發明所揭示之製程至少可達到下列的優點： 1 ·因本發明之製程中的BPTE0S層是在低〇3濃度的環 境中進行沉積，故可具有較髙的產量輸出（throughput)。 2 ·利用緩衝氧化物蝕刻方式將在回蝕刻程序中被硬 化之BPTE0S層的表面去除，使得後續之接觸孔蝕刻操作可 在性質均一的BPTE0S層中進行，並進而獲得理想之碗狀接 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I I —裝 II 訂 II 备 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印裝 A7 B7 五、發明説明（p) 觸窗開口以便於後續之金屬濺鍍作業及確保金屬接線之良 率。 3 ·有較佳之步階覆蓋性（step coverage)。 本發明的上述的及其它的目地*優點及特徵當與下列 的說明及隨附的圖式一起被考慮時將會更加的明顯。 [圖式簡要說明〕 第1圖至第4圖爲本發明之製造方法的一較佳實施例 在實施過程中之半導體元件的剖面圖。 [最佳實施例詳細說明〕 本發明之積體電路的製造方法之一較佳實施例將參照 隨附之圖式作一詳細的說明，其中相同的標號代表相同的 部分。 現請參照第1圖，在第1圖中顯示有-個半導體基質 1 0 ·在該半導體基質中形成有半導體元件結構，如聚矽 閘極1 1以及源極與汲極區1 2 » — t丄厚度的PETE0S層 1 3首先被沉積覆蓋於該半導體元件上。t 1的厚度較佳 地爲2 0 0 0 A。接著在該PETE0S層上沉積一 t 2厚度的 BPTE0S介電層1 4。該BPTE0S層最好是在低03濃度的環 境中進行沉積以獲得較快的沉積速率，且最好是在攝氏800 度的溫度下對其作熱流處理（FI ow )以增加BPTE0S之流動性 。此外，t2的厚度較佳地爲9000 A。 接下來的步驟爲在該BPTE0S層1 4上塗覆（coating) — t3厚度的旋施玻璃（S0G)層1 5以增進整個介電層之平坦 -6- 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） —裝 訂^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（」f) 性（Planarization)並在攝氏420度的温度下對其進行固化 處理（Curing)以去除蘊含於S0G層中有機溶劑。S0G 層的 厚度t3較佳地爲1350A。 在經過了介電層的覆蓋之後，半導體元件業已被深埋 於介電層之下*故若直接由此處向下蝕刻金屬接線之接觸 孔（contact hole)的話，則可能因爲接觸孔過深及過於狹 窄而使得後續之被濺鍍之金屬無法到達底部之半導體元件 進而影響到金屬接線的可靠度與整個產品的良率。因此， 在進行接觸孔蝕刻作業之前，需先對介電層進行回蝕刻 (etching back) ° 申請人研究後發現•現有積體電路製程中之接觸孔蝕 刻方法無法於低〇 3 BPTE0S層中形成理想之碗形接觸孔之 原因，乃在於此回蝕刻的操作上。蓋，一般現行之傅統的 接觸孔形成方法中在對介電層回蝕刻一定的厚度，如6 0 0 0 A，之後便立即進行光罩作業及接觸孔之均向與非均向蝕 刻。然而，申請人經深入研究後發現，低0 3 BPTE0S在經 過回蝕刻之後，其表面有緻密化（densified)的現象，亦艮p ，回蝕刻後之低〇 3 BPTE0S表面會產生一層緻密層 (densified layer)，故而在進行後續之接觸孔的均向蝕刻 時 > 高〇3 BPTE0S的表面的蝕刻速率較低03 BPTE0S其它 部分的蝕刻速率來的慢而在開口處產生觭角，因而無法形 成理想的碗狀接觸孔。申請人在瞭解此一存在已久的問題 的成因之後，即提出一新的蝕刻方法來克服此一問題，茲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ---------裝-- (請先閲讀背面之注意事項再填寫本頁)Printed A7 B7 by the Employees ’Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (/) [Field of the invention] The present invention relates to a manufacturing method of an integrated circuit, and more specifically, the present invention relates to the manufacturing process of an integrated circuit Method of forming contact windows [Background of the invention] In the process of integrated circuits, when various components, such as MOS, BJT and other components are formed on a semiconductor substrate, a layer is deposited on the components Dielectric thin film materials, such as BPTEOS, etc., are used as a dielectric layer (Interconnect Dielectric) between metal connections and a protective layer of the chip. In general, in order to provide better step coverage for dielectric layers such as BPTEOS, an under layer with better gap filling is deposited before the dielectric layer is deposited, Such as PETE0S. In addition, in order to make the dielectric layer have a flatter surface for subsequent photomask operations, the dielectric layer is usually coated with a layer of spin-on-glass (SOG) layer. Generally, there are two methods for depositing BPTE0S dielectric layer, one is to implement in the environment of high concentration of ozone (Hi 03), and the other is to implement in the environment of low concentration of ozone (Low 03), and each has its own Advantages and disadvantages. BPTE0S deposited under high-concentration ozone has a relatively stable quality, so it can form a better bowl-shaped opening when forming the contact window opening. The disadvantage is that the deposition rate is slower. On the contrary, BPTEOS deposited under low concentration of ozone cannot form an ideal bowl-shaped contact window opening due to its unstable quality. The advantage is that the deposition speed is faster. -3-This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) IIII n 丨 Binding I know (please read the notes on the back before filling this page) A7 printed by Employee Consumer Cooperative of Central Standards Bureau B7 V. Description of invention (yl In the process of integrated circuit, the speed of the deposition of BPTEOS dielectric layer directly affects the output efficiency of production, and the ideal shape of the contact window opening affects the reliability of the metal wiring connection. That affects the yield of the entire semiconductor device manufacturing (yield) »How to take into account the manufacturing efficiency in the deposition process of the dielectric layer and the etching process of the contact window opening, that is, the dielectric layer is deposited at a faster rate The yield rate, that is, the formation of an ideal bowl-shaped contact window opening, has always been an urgent need to break through and overcome in the field of semiconductor device manufacturing. [Invention] Therefore, a main object of the present invention is to provide a semiconductor The device process can simultaneously deposit a dielectric layer at a high rate to improve production efficiency and can form an ideal bowl-shaped contact window opening to improve half Yield of bulk components. Another object of the present invention is to provide a method for etching an ideal bowl-shaped contact opening of uranium. According to the object of the present invention, a method for depositing a high dielectric layer The manufacturing method of an integrated circuit forming a bowl-shaped contact window opening is disclosed. The method of the present invention includes the steps of: providing a semiconductor substrate and forming a semiconductor element in and on the semiconductor substrate; and on the surface of the semiconductor element Depositing a first thickness of plasma strengthened tetraethylphosphosilicate (PETE0S) layer; depositing a second thickness of boron phosphorus tetraethylphosphosilicate (BPTEOS) layer on the PETE0S layer; The BPTEOS layer is subjected to flow treatment; a third thickness spin-on-glass (SOG) layer is coated on the BPTEOS layer; the spin-on glass layer is cured; the spin-on glass layer is applied And -4- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (21〇Χ297 公 嫠) --------— installed (please read the precautions on the back before filling in this page) A7 B7 printed by the Ministry of Central Standards Bureau employee consumer cooperative ~ ------------------------------------------------- ---------------- 丨 丨 __ V. Description of the invention (>) The BPTE0S layer is etched back to etch a fourth thickness * the fourth Thickness greater than the third thickness and less than the second thickness; wet buffer oxide etching (Buffer Oxide Etch) of the BPTE0S layer after etching back; engraving a fifth with uranium; performing contact hole photoresist coverage operation; extinction 44: light Resisting hard baking (hardb / tcey treatment to remove moisture; performing uniform and non-uniform contact hole dry etching to remove the photoresist; and completing the fabrication of integrated circuits ^ «, ^, < 11111 — Manufacture. According to a feature of the present invention, the BPTEOS layer is deposited in a low O3 concentration environment. According to another feature of the present invention, the wet buffered oxide etching uses a buffered oxide etchant as a buffer (Buffer Agent), the ratio of which is NH4 F: HF = 10: 1. According to a further aspect of the present invention Features * The first thickness of the PETOS layer is 2 0 0 0 0 A, the second thickness of the BPTE0S layer is 9 0 0 0 A, and the third thickness of the S0G layer is 1 3 5 0 A. According to another further feature of the invention, the fourth thickness of the etch back is 5QQQA, and the fifth thickness of the buffer oxide etch is 10QQA. The process disclosed in accordance with the present invention can at least achieve the following advantages: 1. Because the BPTEOS layer in the process of the present invention is deposited in an environment with a low O3 concentration, it can have a relatively high throughput. 2. The buffer oxide etching method is used to remove the surface of the BPTE0S layer that is hardened in the etch back process, so that the subsequent contact hole etching operation can be performed in the BPTE0S layer with uniform properties, and then obtain the ideal bowl-shaped paper The standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) IIII-Pack II Order II equipment (please read the precautions on the back and then fill out this page) A7 B7 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Description (p) The contact window opening is convenient for subsequent metal sputtering operations and ensuring the yield of metal wiring. 3. There is better step coverage. The above and other objectives * advantages and features of the present invention will be more apparent when considered together with the following description and accompanying drawings. [Brief Description of the Drawings] FIGS. 1 to 4 are cross-sectional views of semiconductor devices during implementation of a preferred embodiment of the manufacturing method of the present invention. [Detailed description of the preferred embodiment] One of the preferred embodiments of the manufacturing method of the integrated circuit of the present invention will be described in detail with reference to the accompanying drawings, in which the same reference numerals represent the same parts. Please refer now to FIG. 1, which shows a semiconductor matrix 1 0. A semiconductor device structure such as a polysilicon gate 1 1 and source and drain regions 1 2 are formed in the semiconductor matrix »— The PETEOS layer 13 with a thickness of 1 mm is first deposited on the semiconductor element. The thickness of t 1 is preferably 200 0 0 A. Next, deposit a BPTEOS dielectric layer 14 with a thickness of t 2 on the PETEOS layer. The BPTEOS layer is preferably deposited in an environment with a low concentration of 03 to obtain a faster deposition rate, and it is best to perform heat flow treatment (FI ow) at a temperature of 800 degrees Celsius to increase the fluidity of the BPTEOS. In addition, the thickness of t2 is preferably 9000 A. The next step is to coat the spin-on-glass (S0G) layer 15 with a thickness of t3 to the BPTE0S layer 14 to improve the flatness of the entire dielectric layer-6. This paper standard uses the Chinese National Standard (CNS ) A4 specification (210X297mm)-binding ^ (please read the notes on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description ("f) Planarization and It is cured at a temperature of 420 degrees Celsius to remove the organic solvent contained in the SOG layer. The thickness t3 of the SOG layer is preferably 1350A. After being covered by the dielectric layer, the semiconductor device is already buried deep under the dielectric layer * So if the contact hole of the metal wiring is etched directly from here, it may be because the contact hole is too deep And it is too narrow, so that the subsequent sputtered metal cannot reach the bottom semiconductor device, which affects the reliability of the metal wiring and the yield of the entire product. Therefore, before the contact hole etching operation, the dielectric layer needs to be etched back. The applicant found that the contact hole etching method in the existing integrated circuit process cannot be formed in the lower 〇3 BPTE0S layer The reason for the ideal bowl-shaped contact hole lies in the operation of this etching. For the cover, the current general method of forming contact holes is to etch back the dielectric layer to a certain thickness, such as 600 0 A. Immediately afterwards, the photomask operation and the directional and non-uniform etching of the contact holes are performed. However, after in-depth research, the applicant found that the low 0 3 BPTE0S had a densified phenomenon on the surface after etch back. Also, the low 〇3 BPTE0S surface after etching back would produce a dense layer ( densified layer), so when the subsequent directional etching of the contact hole is performed > the etching rate of the surface of the high BP3 BPTE0S is low 03 The etching rate of the other parts of the BPTE0S is slow and the corners are generated at the opening, so it cannot be formed Ideal bowl-shaped contact hole. After the applicant understands the cause of this long-standing problem, he proposes a new etching method to overcome this problem. The standard of this paper is the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) ----- Install-(Please read the notes on the back before filling this page)
、1T A7 B7 經濟部中央標準局員工消費合作杜印聚 五、發明説明 詳述如下。 現請參照第2圖及第3圖，在完成SOG層的處理之後 即對SOG與BPTEOS進行回蝕刻一厚度t 4 ，而t 4的厚度較 佳地爲5000A。此時，在BPTEOS層的表面會有一緻密層1 4 ’形成。接下來，則對BPTEOS層進行濕式蝕刻（Wet Etch) —厚度爲t 5以去除該緻密層1 4 ’，如第3圖中所 示。該緩衝氧化蝕刻較佳地是以緩衝蝕刻液（B0E )來作爲 蝕刻溶液*其比例爲NH4 F : HF= 1 0 : 1，而t 5的厚度較佳地 爲 1000A 。 最後請參照第4圖，在完成緩衝氧化蝕刻後即是一般 之接觸孔的蝕刻作業，如塗覆光阻劑（P . R .)，以攝 氏120度的温度進行硬烤（hard bake )處理以去除光阻劑中 之水分，對BPTEOS層與PETE0S層進行均向與非均向蝕刻 (ISO/ANISO etxhing)以形成理想之碗狀的接觸窗開口 1 6，及去除光阻等步驟。 在上文中本發明雖以一較佳實施例被說明，然應被瞭 解的是本發明並不只限於上述的實施例。對於熟於此技藝 者而言，在不偏離本發明由F文中之申請專利範圍所界定 之範圍與精神的前題下，其它變化及修改是可被達成的》 -8- 本紙張尺度制巾賴家料（CNS ) A4規格（21GX297公簸） ---------裝------訂------4 (請先聞讀背面之注意Ϋ項再填寫本頁), 1T A7 B7 Du Yinju Employee Consumption Cooperation of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention Detailed as follows. Now referring to FIGS. 2 and 3, after the SOG layer is processed, SOG and BPTEOS are etched back to a thickness t 4, and the thickness of t 4 is preferably 5000A. At this time, a uniform dense layer 14 'is formed on the surface of the BPTEOS layer. Next, the BPTEOS layer is wet-etched (Wet Etch)-with a thickness of t 5 to remove the dense layer 1 4 ′, as shown in FIG. 3. The buffered oxide etching preferably uses buffered etching solution (BOE) as the etching solution *, the ratio of which is NH4 F: HF = 10: 1, and the thickness of t 5 is preferably 1000A. Finally, please refer to Figure 4. After the buffer oxidation etching is completed, it is the general etching operation of the contact hole, such as applying a photoresist (P.R.), and performing a hard bake treatment at a temperature of 120 degrees Celsius. In order to remove the water in the photoresist, the BPTEOS layer and the PETEOS layer are subjected to isotropic and non-isotropic etching (ISO / ANISO etxhing) to form an ideal bowl-shaped contact window opening 16 and the steps of removing the photoresist. In the above, the present invention has been described with a preferred embodiment, but it should be understood that the present invention is not limited to the above-mentioned embodiment. For those skilled in this art, other changes and modifications can be achieved without departing from the scope and spirit of the invention as defined by the scope of patent application in Article F. -8- This paper standard towel Laijia materials (CNS) A4 specifications (21GX297 public) --------- installed ------ ordered ------ 4 (please read the note Ϋ on the back and then fill in this page)