經濟部中央標準局員工消費合作社印製 ^93144 A7 B7 五、發明説明（1 ) 發明之背景 ⑴發明之領域 本發明係大致關於半導體，特別關於在積體電路（1C)晶 片形成鎢（W)層間連接（ILC)或金屬化導電層間之”介電插 塞”，而避免造成晶片缺陷之有害的”火山效應”之方法 。此方法同樣地應用於形成MOS(金屬氧化物半導體）元件 基礎之源:極、汲極、閘極之’'接觸插塞”。 (2)相關技藝之説明 半導體元件僅在已”個別化”而以指定之方式完成指定 工作之後，達到其功能狀態。”個別化”經由在半導體基 質之界定區域之金屬化而完成。此方法首先藉由形成電場 隔離區域而開始。然後，例如，在Μ 0 S方法，導電閘形成 於介電體上。源與汲極濃密地掺雜。層間介電層沈積於這 些區域上，以作爲介電絕緣體。然後，電孔在層間介電體 開放（例如，蚀刻），而後沈積於這些電孔内之金屬形成接觸 源、吸與閘區域之’’接觸插塞”。視IC晶片之整合程度而 定，一或更多具有適當電路化圖式或”個別化”之金屬層 與層間介電層交互沈積。金屬層間之連接經介電插塞” 而提供。在需要小形體尺寸之高稠密、次微米積體電路裝 置，需要3或4層之金屬化互連。 小尺寸形體用以保持裝置密度儘可能高之同時，通路密 度亦藉由堆疊一個電孔於其他之上而保持高密度，如圖1(A) 所示。如果電孔之側壁爲垂直的，其更爲可能，否則，以 尖錐之側壁，介電層必爲階級化，如圖1 (Β)。（在圖1 (Α)與 -4 - 本紙張尺度逋用中國國家橾準（CNS ) Α4規格（210X 297公釐） — 裝 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作衽印製 發明説明（ UB)，區域1〇、12各爲第一與第二層金屬層，而且區域i4 、16爲第—與第二層絕緣體，及18、2〇爲經過各絕緣體之 第7與第二層介電層。）其生成之圖式尺寸增加造成裝填密 度之大幅降低。沈積於這些垂直電孔之金屬塊稱爲"插塞,, 0 通常，在各層金屬化之整合，特別是層與層間介電體開 口之金屬插塞-其在源閘汲極上區別爲《接觸插塞”，及金 屬層本身間之”介電插塞’，，在1<:晶片之製造非常重要。 金屬沈積於表面上時，所希望的是金屬表面與其他接觸表 面閘爲固體、平滑及連續之介面。相反地，在特定之情況 下’通常發現爲彼此突起之尖峰形成之粗硬介面，反之亦 然。傳統上，此”尖峰形成”及金屬擴散至半導體基質爲 金屬化時最常遭遇之兩個問題。近來其他問題在鎢（w)，，接 觸”與”介電”插塞之金屬化過程所造成的，WF6+Ti —Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 93144 A7 B7 V. Description of the invention (1) Background of the invention (1) Field of the invention The present invention relates generally to semiconductors, in particular to the formation of tungsten (W) on integrated circuit (1C) wafers Interlayer connection (ILC) or "dielectric plug" between metallized conductive layers to avoid the harmful "volcanic effect" that causes wafer defects. This method is also applied to the formation of the MOS (Metal Oxide Semiconductor) device base source: the "contact plug" of the pole, the drain, and the gate. (2) Description of related art The semiconductor device has only been "individualized" After completing the specified work in a specified manner, it reaches its functional state. "Individualization" is accomplished by metallization in a defined area of the semiconductor matrix. This method first begins by forming an electric field isolation region. Then, for example, in M In the 0S method, a conductive gate is formed on the dielectric body. The source and the drain are heavily doped. The interlayer dielectric layer is deposited on these regions to serve as a dielectric insulator. Then, the electric hole is opened in the interlayer dielectric body (for example , Etching), and then the metal deposited in these holes forms the “contact plug” of the contact source, the suction and the gate area. Depending on the degree of integration of the IC chip, one or more metal layers with appropriate circuit patterns or "individualization" are deposited alternately with the interlayer dielectric layer. Connections between metal layers are provided through dielectric plugs. For high-density, sub-micron integrated circuit devices that require small form factors, 3 or 4 layers of metallized interconnects are required. Small form factors are used to maintain device density as much as possible At the same time, the via density is also maintained by stacking an electrical hole on top of the other, as shown in Figure 1 (A). If the sidewall of the electrical hole is vertical, it is more likely, otherwise, a sharp cone For the side walls, the dielectric layer must be hierarchical, as shown in Figure 1 (Β). (In Figure 1 (Α) and -4-This paper scale uses the Chinese National Standards (CNS) Α4 specification (210X 297 mm) — Binding line (please read the precautions on the back and then fill out this page) Printed a description of invention (UB) for the consumer consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Areas 10 and 12 are the first and second metal layers, respectively. i4, 16 are the first and second insulators, and 18, 20 are the seventh and second dielectric layers passing through each insulator.) The resulting pattern size increases and the packing density is greatly reduced. Deposited on these The metal block of the vertical electric hole is called " plug, 0 The integration of metallization of various layers, especially the metal plugs of the openings between the layers and the interlayer dielectrics-which are distinguished as "contact plugs" on the source gate drain, and the "dielectric plugs" between the metal layers themselves, in 1 <;: The manufacture of wafers is very important. When the metal is deposited on the surface, it is desirable that the metal surface and the other contact surface gate be a solid, smooth and continuous interface. Conversely, under certain circumstances, it is usually found to protrude from each other Rough and hard interface for spike formation, and vice versa. Traditionally, this "spike formation" and the diffusion of metal into the semiconductor substrate are the two most common problems encountered when metallization. Other problems recently in tungsten (w), contact "and WF6 + Ti — caused by the metallization process of the “dielectric” plug
TlFx+副產物（by-products)之"火山效應”也被廣泛地注 意將在以下敘述。 通常，美國專利第5,232,87 1號所述阻隔層用以防止尖峰 形成型問題：接觸尖峰形成會發生於元件製造時，元件暴 露於高溫的環境下。其爲有關固體溶解度之現象之—。當 兩個不類似之物質彼此接觸時，會有物質在另一物質内起 平衡濃度作用。例如，當純矽與純鋁接觸時，接觸表面之 介面起初爲平滑的。在後續製程如合金之高溫處理時，因 爲紹可支撑較大量之矽，矽可移入金屬内並且留下電洞。 反之，金屬可經濃密摻雜接合而擴散，並且對基質造成增 -5 本紙張尺度通财！]®家鱗（CNS ) A4規格（21QX297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 經濟部中央標準局員工消費合作社印製 ^9^144 A7 _ B7 五、發明説明（3 ) 加滲漏電流或短路的機會。兩種現象（矽進入鋁及鋁進入矽） 足結果爲不平滑且形成尖峰之鋁-矽介面。這過程稱爲尖峰 形成。理想上，阻隔層是爲了避免一個物質在另一物質内 之尖峰形成與溶解之發生。事實上，可能並非如此理想。 尖峰形成可藉由使用如Al-l% Si之含珍的銘合金，或使 用如鈦-鎢（Ti-W)之阻隔物質而減少。事實上，常用噴鍍之 氮化鈥（TiN)用作爲阻隔層。然而，TiN本身有問題。首先 ，其在噴鍍槽喷鍍於表面時，其本身結構爲具有間隙之柱 狀結構。間隙稱爲顆粒邊界，而且金屬化時，將使金屬有 機會經移動而到達底下之表面。如果底下之表面爲基質， 則尖峰形成與金屬擴散將發生於汲-源-閘區域，其如上所述 ，爲不希望的現象。 在先行技藝已提議許多解決尖峰形成與擴散問題之解決 方法。在一個金屬化製程中，嚐試藉由在金屬之沈積前， 以氧（〇〇分子”填充”（”填充阻隔”討論於s伍爾夫之書 "V L SI年代"，格子出版社，日落海難，加州，1 9 9 〇，第2 卷’第1 2 3頁）處理’使氧原子填充於柱與柱間的間隙或顆 粒邊界，使得金屬不能通過或移動至底下之基質。然而， 發現此乳彡興充方式在大氣室溫完成時，並不是非常有 效，因爲此時之氣體吸附處理並不適當或可靠。另—提議 更進一步，其中使用大氣但是高溫處理或電聚增強反應處 理。結果仍然不完全有效。（美國專利第5,232,87 1號）。 另一先行技藝仍使用較高溫以改良T i N整體性，如美國專 利第5,23 2,87 1號所述，基質首先塗以TiN後，基質在約 -6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 訂 故 (請先閱讀背面之注意事項再填寫本頁) A7 Β7 經濟部中央標準局員工消費合作杜印製 五、發明説明（4 6〇0°C至800eC於快速熱注入離子器（RTA)中經氮氣處理約 3 0至9 0秒。高溫造成氮化物與氮之強化反應，.比在室溫暴 露於大氣時大爲增加TiN的成分。阻隔層形成密封狀況，以 避免尖峰形成或金屬擴散至基質内。然後，金屬可沈積而 不必擔心阻隔層之整體化。不幸地，雖然解決一組問題， RT A引起生產線下游之另一组問題。一個嚴重之問題爲高 溫限制及可加於基質表面之高溫梯度，除非裝置經常地調 毛’否則將造成基質之捲繞，如果基質捲繞，石版印刷圖 式無法對齊基質之全部表面，其在IC裝置之製造爲重要之 操作。此外，在金屬處理後無法使用RT A，會造成金屬炫 化而且線變短。此外，RT A已被許多裝置失敗所困擾，並 且通常限制其用途於研究工具。 如上所述，先行技藝已專注於嚐試密封阻隔層之顆粒邊 界-以防止後續沈積金屬在這些空間内之移動，作爲在介面 避免尖峰形成與金屬擴散問題之方法。另有一先行技藝未 解決之問題。所謂’’火山效應”之問題。 火山效應爲在金屬化時已進入阻隔層顆粒邊界之特定物 質反應噴出所造成。這些物質來自於製程上的污染、或在 介電層間隱藏於電孔側壁之蝕刻化合物、或金屬化處理之 其他副產物。在鎢金屬化時，發生以下之反應： WF6 + Ti — TiFx+副產物，即， 氟化鎢（WF6)與鈦（Ti)膜層反應而產生氟化鈦（TiFx)加一些 其他之副產物。在金屬化時噴出，而且生成火山口缺陷， 如圖2區域A放大的平面圖所示，因氟化鈦（TiFx)-爲氣體易 本紙張尺度適用中國國家標準（CNS ) A4規格（2ωχ297公釐 (請先閲讀背面之注意事項再填寫本頁) •裝 ----° A7 A7 經濟部中央標準局員工消費合作社印裝 五、發明説明（5 ) 於流竄，即使顆粒邊界已，，填充”氧分子，仍容易造成火 山效應。 發明之概要 本發明之目的爲排除”火山效應”，而提供在半導體基 質於接觸區域上及連接各種金屬層之通路，簡.化鎢插塞沈 積製程整體性之方法。同時改良，|插塞，，之接觸電阻（Rc) 0 本發明之另一目的爲在該基質上改良TiN阻隔結構。 本發月之.另目的爲減短生產時間、増加輸出、降低對 於外部污染物的暴露機會、及提供操作過程與成本之節省 〇 這些目的藉由首先噴鍍在後續作爲增強氮化鈦阻隔層來 源之鈦薄膜而冗成。然後，氮化鈦噴鍍於第一鈦層上，以 作爲後續金屬沈積用之阻隔層。此時，如此製備之基質引 入鎢槽，基質在此原地暴露於指定處方之氮（NO電漿。僅 使用氮電漿以在第一層轉化更多之氮化物成更多之TiN，以 填滿顆粒邊界間之間隙，並且密封表面。因此，後續沈積 之金屬並未經TiN阻隔層而移動。此外，，，填滿”的動作由 鈦層向上，發生，以沖出任何殘渣與污染物，這些污染 物來自於先前電孔形成與清潔處理之蚀刻副產物。因此， 若要防止污染物之噴出及，，火山效應”之發生，使基質暴 露於如上所述之氮電漿，使得離子在適當溫度注入TiN阻隔 層，接著，仍在電漿之相同槽繼續沈積鎢金屬而使得製程 一氣呵成。阻隔層此時將適當地密封並無需顧慮反應 -8- 本&尺度適用中國國家標準( CNS ) A4規格（210X297公慶_巧------ (请先閱讀背面之注意事項再填寫本頁) •裝· 訂 線 293144 A7 B7The "volcanic effect" of TlFx + by-products is also widely noted and will be described below. Generally, the barrier layer described in US Patent No. 5,232,87 1 is used to prevent the spike formation problem: contact spike formation meeting Occurs when the device is manufactured, and the device is exposed to high temperatures. It is a phenomenon related to the solubility of solids. When two dissimilar substances come into contact with each other, there will be a substance that acts as a balanced concentration in the other substance. For example, When pure silicon is in contact with pure aluminum, the interface of the contact surface is initially smooth. In subsequent processes such as high-temperature treatment of alloys, because it can support a larger amount of silicon, silicon can move into the metal and leave holes. On the contrary, Metal can be diffused through dense doping and bonding, and it will increase the substrate -5 paper standard money!] ® Homescale (CNS) A4 specification (21QX297mm) (Please read the precautions on the back before filling this page) • Binding · Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 9 ^ 144 A7 _ B7 5. Invention description (3) Increase the chance of leakage current or short circuit. Two phenomena (silicon enters aluminum and aluminum Into silicon) The result is an aluminum-silicon interface that is not smooth and spikes. This process is called spike formation. Ideally, the barrier layer is to avoid the formation and dissolution of spikes in one substance in another substance. In fact, It may not be so ideal. The formation of spikes can be reduced by using precious inscription alloys such as Al-l% Si, or using barrier materials such as titanium-tungsten (Ti-W). In fact, commonly used sprayed nitride “TiN” is used as a barrier layer. However, TiN itself has problems. First, its structure is a columnar structure with gaps when it is sprayed on the surface of the spraying tank. The gap is called a particle boundary, and when metallized , Will give the metal a chance to reach the underlying surface through movement. If the underlying surface is the substrate, then the peak formation and metal diffusion will occur in the sink-source-gate area, which, as described above, is an undesirable phenomenon. The art has proposed many solutions to the problem of spike formation and diffusion. In a metallization process, an attempt is made to "fill" ("fill barrier") with oxygen (〇〇 molecules) before the deposition of the metal Yus Woolf's Book "VL SI Age", Lattice Press, Sunset Shipwreck, California, 1 9 9 〇, Volume 2 'Page 1 2 3) Treatment' to fill oxygen columns between columns The gap or particle boundary prevents the metal from passing through or moving to the underlying substrate. However, it is not very effective to find that this milk-filling method is completed at atmospheric room temperature because the gas adsorption treatment at this time is not appropriate or reliable .Also—Proposed to go further, which uses atmospheric but high temperature treatment or electropolymerization enhanced reaction treatment. The result is still not completely effective. (US Patent No. 5,232,87 1). Another prior art still uses higher temperature to improve T i N Integrity, as described in US Patent No. 5,23 2,87 1, after the substrate is first coated with TiN, the substrate is about -6-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page) A7 Β7 Employee's consumer cooperation with the Central Standards Bureau of the Ministry of Economic Affairs Du Printed 5. Description of the invention (4 60 ° C to 800eC in the rapid thermal implantation ionizer (RTA) Nitrogen treatment about 3 0 to 90 seconds. The high temperature causes the strengthening reaction between nitride and nitrogen, which greatly increases the composition of TiN than when it is exposed to the atmosphere at room temperature. The barrier layer forms a sealed condition to avoid spike formation or metal diffusion into the matrix. Then, the metal can be deposited without worrying about the integration of the barrier layer. Unfortunately, while solving one set of problems, RT A caused another set of problems downstream of the production line. A serious problem is the high temperature limit and the high temperature gradient that can be applied to the surface of the substrate. Unless the device frequently adjusts the hair, it will cause the winding of the substrate. If the substrate is wound, the lithographic pattern cannot align all the surfaces of the substrate. The manufacture of IC devices is an important operation. In addition, RT A cannot be used after metal treatment, which will cause the metal to dazzle and shorten the wire. In addition, RT A has been plagued by the failure of many devices and often limits its use to research tools. As mentioned above, the prior art has focused on trying to seal the particle boundaries of the barrier layer-to prevent the subsequent movement of the deposited metal in these spaces, as a method of avoiding the problem of spike formation and metal diffusion at the interface. There is also an unresolved issue with prior art. The so-called "volcanic effect" problem. The volcanic effect is caused by the reaction of specific substances that have entered the boundary of the barrier layer particles during metallization. These substances come from pollution in the manufacturing process or are hidden in the sidewalls of the pores between the dielectric layers. Etching compounds, or other by-products of metallization. When tungsten is metallized, the following reaction occurs: WF6 + Ti — TiFx + by-products, that is, tungsten fluoride (WF6) reacts with titanium (Ti) film to produce fluorine Titanium oxide (TiFx) plus some other by-products. It is ejected during metallization, and crater defects are generated, as shown in the enlarged plan view of area A of Figure 2, because titanium fluoride (TiFx)-is suitable for gas and paper. China National Standard (CNS) A4 specification (2ω × 297mm (please read the notes on the back before filling in this page) • Installed ---- ° A7 A7 Printed and printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Instructions (5 ) Due to flow channeling, even if the particle boundary has been filled with "oxygen molecules, it is still easy to cause volcanic effect. SUMMARY OF THE INVENTION The purpose of the present invention is to eliminate the" volcanic effect "and provide a semiconductor matrix The contact area and the paths connecting various metal layers, simplify the method of tungsten plug deposition process integrity. At the same time improve, | plug, contact resistance (Rc) 0 Another object of the present invention is on the substrate Improving the TiN barrier structure. This month ’s goal is to reduce production time, increase output, reduce exposure to external contaminants, and provide operational process and cost savings. These purposes are enhanced by first spraying in the follow-up The titanium film from the titanium nitride barrier layer is redundant. Then, titanium nitride is sputtered on the first titanium layer as a barrier layer for subsequent metal deposition. At this time, the substrate prepared in this way is introduced into the tungsten groove, and the substrate is This is exposed in situ to the prescribed nitrogen (NO plasma. Only nitrogen plasma is used to convert more nitride to more TiN in the first layer to fill the gaps between particle boundaries and seal the surface. Therefore The metal deposited subsequently does not move without the TiN barrier layer. In addition, the "filling" action takes place from the titanium layer upwards to flush out any residues and contaminants from the previous electricity Formation and cleaning of etching by-products. Therefore, to prevent the emission of pollutants and the "volcanic effect", the substrate is exposed to the nitrogen plasma as described above, so that ions are implanted into the TiN barrier layer at an appropriate temperature, and then , The tungsten metal is still deposited in the same tank of the plasma to make the process complete. The barrier layer will be properly sealed at this time and there is no need to worry about the reaction -8- This & scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 Gongqing_ Qiao ------ (please read the precautions on the back before filling in this page) • Binding · Stranding 293144 A7 B7
經濟部中央樣準局員工消費合作社印製 五、發明説明（6 ) WFdTi—TiFx+之副產物被藏於”接觸插塞，，之洞内或” 介電插塞”之侧壁内，而造成”火山效應，，的發生，如圖3 區域B之放大平面圖所見。此外，與鎢插塞整合之鈦層全面 地改良了插塞之接觸電阻（R。）。 顯而易見地因爲該二製程（在鵠沈積槽之氮電漿）之組合而 減短生產時間、增加輸出、降低暴露於外部污染物的機會 、及提供操作處理與成本之節省。並且傳統RTA之方_式無 法排除了如前所述之基質捲繞、污染與輸出之顯著問題。 圖式之簡要説明 圖1 (A)爲先行技藝顯示垂直側壁開口之橫切面圖。 圖1(B)爲先行技藝顯示壁開口之橫切面圖。 圖2爲顯示先行技藝在未暴露於電漿與注入離子之鎮_ 金屬化基質之”火山效應”之上視圖。 圖3爲本發明之方法形成之元件之上視圖，顯示在暴露於 N2電漿與注入離子之鎢_金屬化基質無火山效應”。 圖4爲接觸開口之形成後之半導體基質之橫切面圖。 圖5爲沈積Ti與TiN層後之相同半導體基質之橫切面圖。 圖6爲半導體基質之橫切面圖，其中敘述在没-源-閘區域 上之鎢M接觸插塞”。 圖7爲半導體基質之橫切面圖，其中敘述在金屬化層之間 之鎢”介電插塞”。 經隹_具體實施例之説明 現在參考圖4，顯示MOS裝置之基質10及源區域12與14 、閘1 8、及汲區域2 2與2 4，及閘氧化矽層1 6。其藉由此技 -9- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁} .裝. 丁 、τ 線 A 7 _B7_ 五、發明説明（7 ) 藝已知之方法而形成，而且因爲其對本發明並不重要，而 不在此詳細説明。應注意在圖4之基質已接受許多不同之製 程步驟，·包括電場阻隔、閘界定、源/吸植入、層間介電 、及接觸界定。在圖4之區域20爲層間介電，而且爲硼與磷 摻雜膜，其藉由如本發明使用之正矽酸四乙酯之分解而沈 積（BP-TEOS) 〇對於本發明之精神，使用之實際步驟並不 嚴格。此外，應注意，本發明步驟適用於任何有氮化鈥阻 隔層與後續金屬化製程的元件。 圖5爲鈦（Ti)與氮化鈦（TiN)沈積後之橫切面圖。區域30 與4.0各爲Ti與TiN層。膜使用反應性噴鍍方法而沈積。噴 鍍參數爲： (請先閱讀背面之注意事項再填寫本頁) .裝 訂 經濟部中央標準局員工消費合作社印製Printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The by-products of WFdTi-TiFx + are hidden in the holes of the "contact plug," or the side walls of the "dielectric plug", resulting in "The volcanic effect,", occurs as shown in the enlarged plan view of area B in Figure 3. In addition, the titanium layer integrated with the tungsten plug has completely improved the contact resistance (R.) of the plug. Obviously, due to the combination of these two processes (nitrogen plasma in the deposition tank), production time is reduced, output is increased, exposure to external contaminants is reduced, and operation and cost savings are provided. In addition, the traditional RTA method cannot eliminate the significant problems of matrix winding, contamination and output as described above. Brief Description of the Drawings Figure 1 (A) is a cross-sectional view of the prior art showing the opening of the vertical side wall. FIG. 1 (B) is a cross-sectional view of the prior art display wall opening. FIG. 2 is a top view showing the "volcanic effect" of the prior art on the metallized substrate that is not exposed to plasma and implanted ions. Fig. 3 is a top view of a device formed by the method of the present invention, showing that there is no volcanic effect on the tungsten metallized substrate exposed to N2 plasma and ion implantation. Fig. 5 is a cross-sectional view of the same semiconductor substrate after depositing Ti and TiN layers. Fig. 6 is a cross-sectional view of the semiconductor substrate, which describes the tungsten M contact plug on the non-source-gate region. Figure 7 is a cross-sectional view of a semiconductor substrate, which describes a tungsten "dielectric plug" between metallization layers. Description of specific embodiments. Referring now to FIG. 4, the substrate 10 and source regions 12 and 14 of the MOS device, the gate 18, and the drain regions 22 and 24, and the gate silicon oxide layer 16 are shown. It is based on this technique-9- This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling this page). Install. Ding, τ line A 7 _B7_ DESCRIPTION OF THE INVENTION (7) It is formed by a known method, and it is not detailed here because it is not important to the present invention. It should be noted that the substrate in FIG. 4 has accepted many different process steps, including electric field blocking, gate definition, Source / suction implantation, interlayer dielectric, and contact definition. Region 20 in FIG. 4 is interlayer dielectric, and is a boron and phosphorus doped film, which is decomposed by tetraethyl orthosilicate as used in the present invention The deposition (BP-TEOS) 〇 For the spirit of the present invention, the actual steps used are not strict. In addition, it should be noted that the steps of the present invention are applicable to any device with a nitride barrier layer and subsequent metallization process. Figure 5 is Cross-sectional view of titanium (Ti) and titanium nitride (TiN) after deposition. Regions 30 and 4.0 are Ti and TiN layers respectively. The film is deposited using a reactive sputtering method. The sputtering parameters are: (Please read the back side first Matters needing attention before filling this page). Department of the Central Bureau of Standards staff printed consumer cooperatives
表I 參數： Ti沈積 TiN 沈積 系統塵·力(mT) 2-2.5 3.5-4 噴鏡環境(seem) Ar 36 N2:100，Ar : 50 DC電力(W) 3000 6500 在本發明應注意，爲了許多理由而沈積欽膜：最重要地 ’膜在垂直側壁電孔之角落上提供良好之階段覆蓋；膜改 良鎢對SiCh之黏附性，而且可在基質接面消耗掉薄“〇2層 來改良接觸電阻；飲膜可在表面形成氧化鈦薄層而防止鵁 -10 - 本紙張尺^適用中國國家揉準（CNS ) A4規格（210X297公着 1 ---- 經濟部中央標準局員工消费合作社印製 A7 五、發明説明（8 層腐蝕，使鎢爲更佳之擴散層。 如在本發明所見，保留如上所述沈積鈦膜之優點而無有 害之火山效應。爲了此目的，在氬-氮（ar_nz)環境進行嘴 鍍沈積方法，使得氮加入Ti:w膜。氮藉由，’填充”顆粒邊 界而改良膜之阻隔性質，而實質上降低互相擴散之速率。 更重要地，其經TiN之形成而降低鈦在膜之反應性，最重要 地，T1與T1N以此方式接受原地N2 -電漿，而避免如概論部 份所述之”火山效應”。 在噴鍍方法之嚴格參數爲對Ti沈積爲2-2.5毫托耳（mT) ’及對丁 1N沈積爲3 · 5 - 4 m T之系統壓力。噴鍍環境對τ丨需要 36標準立方公分（sccm)之氬（Ar)，及對TiN需要5〇sccm之 Ar及lOOsccm之N2。應注意第一層之鈦對本發明亦是很重 要的’因爲其爲在T i N沈積後，充滿顆粒邊界之間隙所需額 外阻隔物質之來源。其較佳厚度爲4〇〇至6〇〇微米之間。 其次’本發明之主要步驟，是TiN之整體化藉由將其在鎢 沈積槽暴露於氮（N2)電漿而増強。在此環境之較佳參數爲Table I Parameters: Ti deposition TiN deposition system dust · force (mT) 2-2.5 3.5-4 spray environment (seem) Ar 36 N2: 100, Ar: 50 DC power (W) 3000 6500 In the present invention, it should be noted that in order to Films are deposited for many reasons: the most important thing is that the film provides good stage coverage at the corners of the vertical sidewall electrical holes; the film improves the adhesion of tungsten to SiCh, and can be consumed by a thin "〇2 layer at the substrate junction to improve Contact resistance; film can form a thin layer of titanium oxide on the surface to prevent 鵁 -10-This paper ruler ^ applies to the Chinese National Standard (CNS) A4 specification (210X297 public 1 ---- Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Print A7 V. Description of the invention (8 layers of corrosion make tungsten a better diffusion layer. As seen in the present invention, the advantages of depositing a titanium film as described above are retained without harmful volcanic effects. For this purpose, in argon-nitrogen (Ar_nz) The environment performs the nozzle plating deposition method, so that nitrogen is added to the Ti: w film. Nitrogen improves the barrier properties of the film by 'filling in' the particle boundary, and substantially reduces the rate of interdiffusion. More importantly, it passes TiN The formation of titanium to reduce the inversion of titanium in the film Most importantly, T1 and T1N accept in-situ N2-plasma in this way, and avoid the "volcanic effect" as described in the introduction. The strict parameters of the sputtering method are 2-2.5 milliseconds for Ti deposition Torr (mT) 'and 1N of butadiene are deposited at a system pressure of 3 · 5-4m T. The sputtering environment requires 36 standard cubic centimeters (sccm) of argon (Ar) for τ 丨 and 5〇sccm for TiN Ar and 100 sccm of N2. It should be noted that the first layer of titanium is also important for the present invention 'because it is the source of additional barrier material needed to fill the gaps between particle boundaries after TiN deposition. Its preferred thickness is Between 400 and 600 microns. Secondly, the main step of the present invention is the integration of TiN by exposing it to nitrogen (N2) plasma in the tungsten deposition tank. Better parameters in this environment for
表II (請先閲讀背面之注意事項再填寫本頁) -裝· 訂· 參數： 在鎢槽之N2-電漿環境 系統溫度 系統昼力(mT) 電漿環境 400-480〇C 300-600 N2：200-300 seem -11 本紙張尺度適用中國國家榡準（CNS ) A4规格（210X297公釐 293144 經濟.邵中央標準局員工消費合作社印裝 A7 B7 五、發明説明（9 ) DF 電力（瓦） 80-120 時間(秒） 90-120 a )較佳溫度爲約4 2 5 C。在較高之溫度，如槽溫可高達 650°C之RTA，在介電插塞製程中非常容易遭遇，，火山效應 。其主要因爲在電洞之角落（4 1)與肩（4 2)所發現，這是 由於相當不良之階段覆i及在這些位置之丁丨與丁iN膜形成之 較高縱向應力所造成之弱點，較高之溫度因結合冷染物且 膨脹上述之氣態物質（TiFx)及強迫其離開而產生火山口缺 陷。 b) ^於N2電漿之最適條件需要在〇·3至〇.6托耳之範圍之 系統壓力。在這些比傳統使用爲相當高之壓力條件下，氮 更易”填充”及”裝填”至TiN阻隔層之顆粒邊界内 c) 電漿環境包含約200-300Sccm之氮。氮有助於氮化鈦 在阻隔層之產生。其亦爲填充”氮至顆粒邊界内之來源 ，以封閉金屬擴散路徑。 d) 在電漿槽之總時間（含間斷之注入離予）爲約9 〇 ·丨2 〇秒 。比較其與RTA所需超過150秒之時間，本發明増加輸出約 3 0百分比（3 0 % )。 . 圖6爲丰導體基質橫切面圖，其中描述汲-源-閘區域之鎢 *接觸插塞’’。區域55表示此插塞。圖7仍爲半導體基質之 另一橫切面圖’其中描述金屬化層之間之辑，，介電插塞” 。區域65表示此介電插塞。處理步骤同樣應用於嫣，，接觸 插塞”與”介電插塞”之生產。 雖然本發明已參考其較佳具體實施例而特別顯示及敘述 -12 - 本紙張^度適用中國國家標準（〇^)八4規格（210父297公釐） (請先閱讀背面之注意事項再填寫本頁) 、τTable II (Please read the precautions on the back before filling in this page)-Installation · Order · Parameters: N2-plasma environment system temperature system in the tungsten tank Daytime power (mT) plasma environment 400-480〇C 300-600 N2: 200-300 seem -11 This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm 293144 economy. Shao Central Standards Bureau employee consumer cooperative printed A7 B7 V. Invention description (9) DF power (watt ) 80-120 time (seconds) 90-120 a) The preferred temperature is about 4 2 5 C. At higher temperatures, such as RTA with a bath temperature of up to 650 ° C, it is very easy to encounter in the process of dielectric plug, volcanic effect. It is mainly found in the corners (4 1) and the shoulders (4 2) of the hole, which is caused by the relatively poor stage coverage and the higher longitudinal stress formed by the Ding and Ding iN films at these locations Weaknesses, higher temperatures result in crater defects due to the combination of cold dye and expansion of the above gaseous material (TiFx) and forcing it away. b) ^ The optimal conditions for N2 plasma require a system pressure in the range of 0.3 to 0.6 Torr. Under these relatively high pressure conditions than conventional use, nitrogen is easier to "fill" and "fill" into the particle boundary of the TiN barrier layer. C) The plasma environment contains about 200-300 Sccm of nitrogen. Nitrogen contributes to the generation of titanium nitride in the barrier layer. It is also the source of filling "nitrogen into the particle boundary to close the metal diffusion path. D) The total time in the plasma tank (including the intermittent injection ion) is about 90 seconds. Compare it with RTA. It takes more than 150 seconds to increase the output of the present invention by about 30% (30%). Figure 6 is a cross-sectional view of the rich conductor substrate, which describes the tungsten * contact plug in the sink-source-gate region ''. Region 55 represents this plug. Figure 7 is still another cross-sectional view of the semiconductor substrate, which describes the compilation between the metallization layers, "dielectric plug". Area 65 represents this dielectric plug. The processing steps are also applied to the production of “Yan”, “contact plug” and “dielectric plug”. Although the present invention has been specifically shown and described with reference to its preferred specific embodiments-12-This paper is suitable for China National Standard ( 〇 ^) Eight 4 specifications (210 father 297 mm) (please read the notes on the back before filling this page), τ
A7 B7 五、發明説明（10 ) ，熟悉此技藝者應了解，可進行各種方式及細節之變化但 不背離本發明之精神與範圍。例如，在此對Μ Ο S製造所述 之相同步驟恰可應用於雙極半導體之製造。 (請先閱讀背面之注意事項再填寫本頁) .裝_ 訂 線 經濟部中央標準局員工消費合作社印製 13 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）A7 B7 V. Description of the invention (10). Those familiar with this skill should understand that various ways and details can be changed without departing from the spirit and scope of the invention. For example, the same steps described here for MOS manufacturing can be applied to the manufacturing of bipolar semiconductors. (Please read the precautions on the back before filling in this page). 装 _ 线 线 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 13-This paper standard is applicable to China National Standard (CNS) Α4 specification (210X297 mm)