TW287299B - The manufacturing method for IC contacting structure - Google Patents

The manufacturing method for IC contacting structure

Info

Publication number
TW287299B
TW287299B TW85102182A TW85102182A TW287299B TW 287299 B TW287299 B TW 287299B TW 85102182 A TW85102182 A TW 85102182A TW 85102182 A TW85102182 A TW 85102182A TW 287299 B TW287299 B TW 287299B
Authority
TW
Taiwan
Prior art keywords
layer
polysilicon
pattern
deposit
contact
Prior art date
Application number
TW85102182A
Other languages
Chinese (zh)
Inventor
Show-Gwo Wuu
Menq-Song Liang
Jong-Huei Su
Chyuan-Jong Wang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW85102182A priority Critical patent/TW287299B/en
Application granted granted Critical
Publication of TW287299B publication Critical patent/TW287299B/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

Provide a manufacturing method for reducing metal contact the surface of thin polysilicon includes following steps: (1) Provide a semiconductor substrate with 1st & 2nd polysilicon pattern and have isolating layer to form semiconductor element, and part of 2nd polysilicon pattern to be the buffer layer for producing metal contact; (2) Deposit 2nd isolating layer on 2nd polysilicon pattern; (3) Deposit & plasma etch on 3rd polysilicon pattern to form the gate of TFT; (4) Deposit 3rd isolating layer on 3rd polysilicon pattern to be the gate of gate oxide and extend to top of the buffer layer; (5) By PR pattern & anisotropic plasma etching to produce contact window on buffer layer until the 2nd polysilicon layer to form buffer layer surface; (6) Deposit the 4th polysilicon layer on 3rd isolating layer & 1st contact window and contact with buffer layer; (7) Do selective dopant on 4th polysilicon layer by PR pattern & ion implantation to form the source/drain of TFT, and do implantation on 1st contact window simultaneously; (8) Produce 4th polysilicon pattern by PR & plasma etching to form the conductive wire adjacent to source/drain and extended to 1st contact window; (9) Deposit 4th isolating layer on 4th polysilicon pattern; (10) Produce a small 2nd contact window by PR pattern & plasma etching aligned on 1st contact window; (11) Deposit 1st metal layer on 4th isolating layer & 2nd contact window and contact with 4th polysilicon layer to form electrical connection; (12) Patternlize the metal to reduce contacting with polysilicon layer area.
TW85102182A 1996-02-26 1996-02-26 The manufacturing method for IC contacting structure TW287299B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW85102182A TW287299B (en) 1996-02-26 1996-02-26 The manufacturing method for IC contacting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW85102182A TW287299B (en) 1996-02-26 1996-02-26 The manufacturing method for IC contacting structure

Publications (1)

Publication Number Publication Date
TW287299B true TW287299B (en) 1996-10-01

Family

ID=51398027

Family Applications (1)

Application Number Title Priority Date Filing Date
TW85102182A TW287299B (en) 1996-02-26 1996-02-26 The manufacturing method for IC contacting structure

Country Status (1)

Country Link
TW (1) TW287299B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1327531C (en) * 2003-05-19 2007-07-18 友达光电股份有限公司 Low-temperature polysilicon thin film transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1327531C (en) * 2003-05-19 2007-07-18 友达光电股份有限公司 Low-temperature polysilicon thin film transistor

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