TW287299B - The manufacturing method for IC contacting structure - Google Patents
The manufacturing method for IC contacting structureInfo
- Publication number
- TW287299B TW287299B TW85102182A TW85102182A TW287299B TW 287299 B TW287299 B TW 287299B TW 85102182 A TW85102182 A TW 85102182A TW 85102182 A TW85102182 A TW 85102182A TW 287299 B TW287299 B TW 287299B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- polysilicon
- pattern
- deposit
- contact
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
Provide a manufacturing method for reducing metal contact the surface of thin polysilicon includes following steps: (1) Provide a semiconductor substrate with 1st & 2nd polysilicon pattern and have isolating layer to form semiconductor element, and part of 2nd polysilicon pattern to be the buffer layer for producing metal contact; (2) Deposit 2nd isolating layer on 2nd polysilicon pattern; (3) Deposit & plasma etch on 3rd polysilicon pattern to form the gate of TFT; (4) Deposit 3rd isolating layer on 3rd polysilicon pattern to be the gate of gate oxide and extend to top of the buffer layer; (5) By PR pattern & anisotropic plasma etching to produce contact window on buffer layer until the 2nd polysilicon layer to form buffer layer surface; (6) Deposit the 4th polysilicon layer on 3rd isolating layer & 1st contact window and contact with buffer layer; (7) Do selective dopant on 4th polysilicon layer by PR pattern & ion implantation to form the source/drain of TFT, and do implantation on 1st contact window simultaneously; (8) Produce 4th polysilicon pattern by PR & plasma etching to form the conductive wire adjacent to source/drain and extended to 1st contact window; (9) Deposit 4th isolating layer on 4th polysilicon pattern; (10) Produce a small 2nd contact window by PR pattern & plasma etching aligned on 1st contact window; (11) Deposit 1st metal layer on 4th isolating layer & 2nd contact window and contact with 4th polysilicon layer to form electrical connection; (12) Patternlize the metal to reduce contacting with polysilicon layer area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW85102182A TW287299B (en) | 1996-02-26 | 1996-02-26 | The manufacturing method for IC contacting structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW85102182A TW287299B (en) | 1996-02-26 | 1996-02-26 | The manufacturing method for IC contacting structure |
Publications (1)
Publication Number | Publication Date |
---|---|
TW287299B true TW287299B (en) | 1996-10-01 |
Family
ID=51398027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW85102182A TW287299B (en) | 1996-02-26 | 1996-02-26 | The manufacturing method for IC contacting structure |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW287299B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1327531C (en) * | 2003-05-19 | 2007-07-18 | 友达光电股份有限公司 | Low-temperature polysilicon thin film transistor |
-
1996
- 1996-02-26 TW TW85102182A patent/TW287299B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1327531C (en) * | 2003-05-19 | 2007-07-18 | 友达光电股份有限公司 | Low-temperature polysilicon thin film transistor |
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MK4A | Expiration of patent term of an invention patent |