CN1327531C - Low-temperature polysilicon thin film transistor - Google Patents
Low-temperature polysilicon thin film transistor Download PDFInfo
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- CN1327531C CN1327531C CNB031237339A CN03123733A CN1327531C CN 1327531 C CN1327531 C CN 1327531C CN B031237339 A CNB031237339 A CN B031237339A CN 03123733 A CN03123733 A CN 03123733A CN 1327531 C CN1327531 C CN 1327531C
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Abstract
The present invention relates to a low-temperature polysilicon thin film electrical crystal structure which comprises a plurality of polysilicon layers arranged on a base plate, a gate dielectric layer, a gate polar, an intermediate dielectric layer, a plurality of source polar contact windows/draining polar contact windows, and a source polar metal layer/draining polar metal layer, wherein each polysilicon layer comprises a source polar region, a draining polar region, and a channel region positioned between the source polar region and the draining polar region; the polysilicon layers are covered by the gate dielectric layer; the gate polar is arranged on the gate dielectric layer which is arranged on the upper part of the channel region; the gate polar is covered by the intermediate dielectric layer; the source polar contact windows/draining polar contact windows are positioned in the intermediate dielectric layer and the gate dielectric layer; each source polar contact window/draining polar contact window contacts the corresponding source polar region/draining polar region in an electrical property contact mode; the source polar metal layer/draining polar metal layer is formed on the intermediate dielectric layer; the source polar metal layer/draining polar metal layer is connected with the source polar contact windows/draining polar contact windows in an electrical property contact mode. The present invention solves problems of deterioration and poor reliability of components of the existing public-known low-temperature polysilicon thin film electrical crystal because current is too large in the process of large-current operation, and furthermore, the present invention has the efficiency suitable for practicality.
Description
Technical field
The present invention relates to the structure of the thin-film transistor in a kind of electricity field essential electronic element, particularly relate to a kind of structure of low-temperature polysilicon film transistor.
Background technology
Low-temperature polysilicon film transistor is a kind of technology that is different from general traditional amorphous silicon film transistor (Amorphous Silicon TFT), and its electron mobility can reach 200cm
2More than/the V-sec, therefore can make thin-film transistor element do forr a short time, and aperture opening ratio (Aperture Ratio) is increased, and then increase display brightness, reduce the function of power consumption.In addition, because the increase of electron mobility can simultaneously be manufactured in glass substrate in company with the thin-film transistor processing procedure part drive circuit, significantly promote the characteristic and the reliability of display panels, make the panel manufacturing cost significantly reduce, so manufacturing cost is low than the amorphous silicon film transistor LCD.In addition, because of the low-temperature polysilicon film transistor LCD has thin thickness, in light weight, characteristics such as resolution is good, therefore be particularly suitable for being applied to require on the portable terminal product of light and handy power saving.
See also shown in Figure 1A and Figure 1B, Figure 1A is the last TV structure schematic diagram that has known low-temperature polysilicon film transistor now, and Figure 1B is the generalized section of I-I ' section among Figure 1A.Should have known low-temperature polysilicon film transistor now, it comprises a polysilicon layer 106 (comprising source area 12, drain region 14, channel region 13), a grid 108, one source pole metal level 102, a drain metal layer 104, a gate dielectric layer 107, an intermediate dielectric layer (inter-layer dielectric layer) 109 and contact hole 12a, 14a; Wherein:
This polysilicon layer 106 is to be configured on the substrate 100, and is to be formed with two doped regions (source area 12 and drain region 14) and the channel region 13 between source area 12 and drain region 14 in the polysilicon layer 106.
This gate dielectric layer 107 is to cover polysilicon layer 106.And this grid 108 is formed on the gate dielectric layer 107 of channel region 13 tops.In addition, intermediate dielectric layer 109 is formed in the top of substrate 100, cover gate 108.
Moreover, this contact hole 12a, 14a, be to be configured in intermediate dielectric layer 109 and the gate dielectric layer 107, and source metal 102 and drain metal layer 104 are formed on the intermediate dielectric layer 109, and source metal 102 is to electrically connect with source area 12 and drain region 14 by contact hole 12a, 14a with drain metal layer 104.
Above-mentioned low-temperature polysilicon film transistor, its channel length are to be L, and channel width is to be W (shown in Figure 1A), and channel width-over-length ratio is W/L, and therefore general low-temperature polysilicon film transistor all is the design of big breadth length ratio.Yet, the above-mentioned low-temperature polysilicon film transistor of traditional big breadth length ratio that has now is when the operation of big electric current, element causes deterioration easily because of electric current is excessive, make the critical voltage (Threshold Voltage) and the subcritical slope (sub-Threshold Swing) of element become big, and cause the reliability of element not good.
This shows that the structure of above-mentioned existing low-temperature polysilicon film transistor still has many defectives, and demands urgently further being improved.
The problem that exists for the structure that solves above-mentioned low-temperature polysilicon film transistor, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the structure of above-mentioned existing low-temperature polysilicon film transistor exists, the inventor is based on abundant practical experience and professional knowledge thereof, actively studied innovation, through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective of the structure existence of existing low-temperature polysilicon film transistor, and provide a kind of structure of novel low-temperature polysilicon film transistor, technical problem underlying to be solved is to make its low-temperature polysilicon film transistor that can solve existing known big breadth length ratio when the operation of big electric current, element causes deterioration easily because of electric current is excessive, thereby cause the not good problem of reliability of element, be very suitable for practical good effect and have.
Purpose of the present invention and to solve its technical problem underlying be to adopt following technical scheme to realize.The structure of a kind of low-temperature polysilicon film transistor that proposes according to the present invention, it comprises: a plurality of polysilicon layers, be configured on the substrate, wherein include one source pole district, a drain region and the channel region between this source area and this drain region in each this polysilicon layer; One gate dielectric layer covers on this polysilicon layer; One grid is configured on this gate dielectric layer of this channel region top; One intermediate dielectric layer is formed on the top of this substrate, covers this grid; A plurality of source electrode contact holes are arranged in this intermediate dielectric layer and this gate dielectric layer, and each this source electrode contact hole is electrically to contact with corresponding wherein this source area; A plurality of drain electrode contact holes are arranged in this intermediate dielectric layer and this gate dielectric layer, and each this drain electrode contact hole is electrically to contact with corresponding wherein this drain region; The one source pole metal level is formed on this intermediate dielectric layer, and wherein this source metal is to electrically connect with this source electrode contact hole; And a drain metal layer, be formed on this intermediate dielectric layer, wherein this drain metal layer is and this drain electrode contact hole electrically connects; Wherein each this source/drain region/channel region and this grid are to constitute a sub-thin-film transistor, and the channel width of each this sub-thin-film transistor is W, and channel length is L.
The object of the invention to solve the technical problems can also be further achieved by the following technical measures.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this sub-thin-film transistor are to be a p type thin-film transistor.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this sub-thin-film transistor are to be a n type thin-film transistor.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this n type thin-film transistor more comprises a lightly mixed drain area, be configured in each this source/drain region with and channel region between.
The structure of aforesaid low-temperature polysilicon film transistor, the channel width-over-length ratio of wherein said each this sub-thin-film transistor (W/L) is between 0.1 to 8.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said grid are to be a linear grid, and this source metal and this drain metal layer are to be respectively a linear source metal and a linear drain metal layer.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said grid is to be a U-shaped grid, this source metal is the inside that correspondence is configured in this U-shaped grid, and this drain metal layer is a U-shaped drain metal layer that is configured in this U type grid outside for correspondence.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said source metal has a plurality of source electrode metal layer contacting portions and one source pole metal level connecting portion, and each this source metal contact site is to electrically connect with each this source electrode contact hole, and this source metal connecting portion is that this source metal contact site is connected in series.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said drain metal layer has a plurality of drain metal layer contact sites and a drain metal layer connecting portion, and each this drain metal layer contact site is to electrically connect with each this drain electrode contact hole respectively, and this drain metal layer connecting portion is that this drain metal layer contact site is connected in series.
Purpose of the present invention and solve its technical problem underlying and also realize by the following technical solutions.The structure of a kind of low-temperature polysilicon film transistor that proposes according to the present invention, it comprises: a grid is configured on the substrate; One gate dielectric layer is formed on the top of this substrate, covers this grid; A plurality of polysilicon layers are configured on this gate dielectric layer, wherein include one source pole district, a drain region and the channel region between this source area and this drain region in each this polysilicon layer, and this channel region are the tops that is positioned at this grid; One intermediate dielectric layer is formed on the top of this substrate, covers this polysilicon layer; A plurality of source electrode contact holes are arranged in this intermediate dielectric layer, and each this source electrode contact hole is electrically to contact with corresponding wherein this source area; A plurality of drain electrode contact holes are arranged in this intermediate dielectric layer, and each this drain electrode contact hole is electrically to contact with corresponding wherein this drain region; The one source pole metal level is formed on this intermediate dielectric layer, and wherein this source metal is to electrically connect with this source electrode contact hole; And a drain metal layer, be formed on this intermediate dielectric layer, wherein this drain metal layer is and this drain electrode contact hole electrically connects; Wherein each this source/drain region/channel region and this grid are to constitute a sub-thin-film transistor, and the channel width of each this sub-thin-film transistor is W, and channel length is L.
The object of the invention to solve the technical problems can also be further achieved by the following technical measures.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this sub-thin-film transistor are to be a p type thin-film transistor.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this sub-thin-film transistor are to be a n type thin-film transistor.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said each this n type thin-film transistor more comprises a lightly mixed drain area, be configured in each this source/drain region with and channel region between.
The structure of aforesaid low-temperature polysilicon film transistor, the channel width-over-length ratio of wherein said each this sub-thin-film transistor (W/L) is between 0.1 to 8.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said grid are to be a linear grid, and this source metal and this drain metal layer are to be respectively a linear source metal and a linear drain metal layer.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said grid is to be a U-shaped grid, this source metal is the inside that correspondence is configured in this U-shaped grid, and this drain metal layer is a U-shaped drain metal layer that is configured in this U type grid outside for correspondence.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said source metal has a plurality of source electrode metal layer contacting portions and one source pole metal level connecting portion, and each this source metal contact site is to electrically connect with each this source electrode contact hole, and this source metal connecting portion is that this source metal contact site is connected in series.
The structure of aforesaid low-temperature polysilicon film transistor, wherein said drain metal layer has a plurality of drain metal layer contact sites and a drain metal layer connecting portion, and each this drain metal layer contact site is to electrically connect with each this drain electrode contact hole respectively, and this drain metal layer connecting portion is that this drain metal layer contact site is connected in series.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, major technique of the present invention thes contents are as follows:
The present invention proposes a kind of structure of low-temperature polysilicon film transistor, and it includes several polysilicon layers, a gate dielectric layer, a grid, an intermediate dielectric layer, several source electrode contact holes, several drain contact hole, one source pole metal level and drain metal layer.Wherein, several polysilicon layers are to be configured on the substrate, and are to include one source pole district, a drain region and the channel region between source area and drain region in each polysilicon layer.Gate dielectric layer is the top that is positioned at substrate, covers above-mentioned polysilicon layer.In addition, grid is to be configured on the gate dielectric layer of channel region top, and intermediate dielectric layer is formed in the top of substrate, cover grid.In addition, several source electrode contact holes be arranged in intermediate dielectric layer with the door dielectric layer, and each source electrode contact hole is electrically to contact with corresponding wherein one source pole district.Same, several drain electrode contact holes be arranged in intermediate dielectric layer with the door dielectric layer, and each drain electrode contact hole is electrically to contact with a corresponding wherein drain region.Moreover source metal is formed on the intermediate dielectric layer, and wherein source metal is to electrically connect with several above-mentioned source electrode contact holes.And drain metal layer is formed on the intermediate dielectric layer, and wherein drain metal layer is to electrically connect with several above-mentioned drain electrode contact holes.At this, each source/drain region/channel region and grid are to constitute a sub-thin-film transistor, and the channel width of each sub-thin-film transistor is W, and channel length is L, and its breadth length ratio (W/L) is between 0.1 to 8.
The present invention proposes a kind of structure of low-temperature polysilicon film transistor, and it comprises a grid, a gate dielectric layer, several polysilicon layers, an intermediate dielectric layer, several source electrode contact holes, several drain contact hole, one source pole metal level and drain metal layer.Wherein, grid is to be configured on the substrate, and gate dielectric layer is formed in the top of substrate, cover grid.In addition, several polysilicon layers are to be configured on the gate dielectric layer, wherein in each polysilicon layer be to include one source pole district, a drain region and the channel region between source area and drain region, and channel region are the tops that is positioned at grid.Intermediate dielectric layer is formed in the top of substrate, covers polysilicon layer.In addition, several source electrode contact holes are to be arranged in intermediate dielectric layer, and each source electrode contact hole is electrically to contact with corresponding wherein one source pole district.Same, several drain electrode contact holes are to be arranged in intermediate dielectric layer, and each drain electrode contact hole is electrically to contact with a corresponding wherein drain region.Moreover source metal is formed on the intermediate dielectric layer, and wherein source metal is to electrically connect with several above-mentioned source electrode contact holes.And drain metal layer is formed on the intermediate dielectric layer, and wherein drain metal layer is to electrically connect with several above-mentioned drain electrode contact holes.At this, each source/drain region/channel region to be being to constitute a sub-thin-film transistor with gate pole, and the channel width of each sub-thin-film transistor is W, and channel length is L, and its breadth length ratio (W/L) is between 0.1 to 8.
Because low-temperature polysilicon film transistor of the present invention is to be made of several sub-film transistors institute in parallel, so when element in when operation, the electric current of each sub-thin-film transistor of flowing through is the 1/N (N is the sum of sub-thin-film transistor) of total current, therefore can avoid under the operation of big electric current, can causing the problem of element deterioration, be very suitable for practical effect and have.
In sum, the structure of the low-temperature polysilicon film transistor that the present invention is special, mainly comprising several polysilicon layers, be configured on the substrate, wherein is to include one source pole district, a drain region and the channel region between source area and drain region in each polysilicon layer; One gate dielectric layer covers polysilicon layer; One grid is configured on the gate dielectric layer of channel region top; One intermediate dielectric layer, cover grid; Several source electrode contact hole/drain electrode contact holes are arranged in intermediate dielectric layer and gate dielectric layer, and each source electrode contact hole/drain electrode contact hole is electrically to contact with corresponding source/drain region; And one source pole metal level/drain metal layer, be formed on the intermediate dielectric layer, wherein source metal/drain metal layer is to electrically connect with source electrode contact hole/drain electrode contact hole.By said structure, can solve the low-temperature polysilicon film transistor element when the operation of big electric current that has known big breadth length ratio now and cause deterioration easily because of electric current is excessive, thereby cause the not good problem of reliability of element, be very suitable for practical good effect and have.It has above-mentioned advantage and practical value, and having there is no similar structural design in like product publishes or uses, no matter it is structurally or bigger improvement is all arranged on the function, and have large improvement technically, and produced handy and practical effect, and have the effect of enhancement really, thus be suitable for practicality more, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Figure 1A be existing known low-temperature polysilicon film transistor on look schematic diagram.
Figure 1B is the generalized section that has known low-temperature polysilicon film transistor now.
Fig. 2 be a preferred embodiment of the present invention low-temperature polysilicon film transistor on look schematic diagram.
Fig. 2 A is the generalized section of the low-temperature polysilicon film transistor of a preferred embodiment of the present invention.
Fig. 2 B is the generalized section of the low-temperature polysilicon film transistor of another preferred embodiment of the present invention.
Fig. 3 be the present invention again a preferred embodiment low-temperature polysilicon film transistor on look schematic diagram.
Fig. 4 be another preferred embodiment of the present invention low-temperature polysilicon film transistor on look schematic diagram.
Fig. 5 be another preferred embodiment of the present invention low-temperature polysilicon film transistor on look schematic diagram.
100: substrate 102,302,502: source metal
104,304,5 04: drain metal layer 106,206a, 206b to 206n: polysilicon layer
107: gate dielectric layer 108: grid
109: intermediate dielectric layer 12,202a: source area
13,203a: channel region 14,204a: drain region
12a, 12b to 12n: source electrode contact hole 14a, 14b to 14n: drain electrode contact hole
201a: lightly mixed drain area 302a, 502a: source metal connecting portion
304b, 504b: drain metal layer connecting portion L: channel length
W, Wa, Wb to Wn: channel width
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, its embodiment of structure, structure, feature and the effect thereof of the low-temperature polysilicon film transistor that foundation the present invention is proposed, describe in detail as after.
See also shown in Fig. 2, Fig. 2 A, Fig. 2 be a preferred embodiment of the present invention a kind of low-temperature polysilicon film transistor on look schematic diagram, Fig. 2 A is the generalized section of II-II ' section among Fig. 2.The structure of low-temperature polysilicon film transistor of the present invention, it comprises several polysilicon layers 206a, 206b to 206n, a gate dielectric layer 107, a grid 108, an intermediate dielectric layer 109, several source electrode contact holes 12a, 12b to 12n, several drain electrode contact holes 14a, 14b to 14n, one source pole metal level 102 and a drain metal layer 104; Wherein:
Above-mentioned several polysilicon layers 206a, 206b to 206n is configured on the substrate 100, and be to include one source pole district, a drain region and the channel region between source area and drain region among each polysilicon layer 206a, 206b to 206n, polysilicon layer 206a with Fig. 2 A is an example, and this polysilicon layer 206a includes one source pole district 202a, a drain region 204a and the channel region 203a between source area 202a and drain region 204a.
Above-mentioned gate dielectric layer 107 is that the top that is positioned at substrate 100 is set, and covers polysilicon layer 206a, 206b to 206n.In addition, above-mentioned grid 108 is to be configured on the gate dielectric layer 107, and it is the top that correspondence is configured in the channel region of polysilicon layer 206a, 206b to 206n.And above-mentioned intermediate dielectric layer 109 is formed in the top of substrate 100, cover grid 108.
In addition, above-mentioned several source electrode contact holes 12a, 12b to 12n be arranged in intermediate dielectric layer 109 with door dielectric layer 107, and each source electrode contact hole 12a, 12b to 12n electrically contact (for example source electrode contact hole 12a electrically contacts with source area 202a) with corresponding wherein one source pole district.Same, several drain electrodes contact hole 14a, 14b to 14n be arranged in intermediate dielectric layer 109 with door dielectric layer 107, and each drain electrode contact hole 14a, 14b to 14n electrically contact (the contact hole 14a that for example drains electrically contacts with drain region 204a) with a corresponding wherein drain region.
Moreover, above-mentioned source metal 102, be formed on the intermediate dielectric layer 109, wherein source metal 102 is to electrically connect with source electrode contact hole 12a, 12b to 12n, so that the source area in each polysilicon layer 206,206a to 206n has the relation of electric connection.And above-mentioned drain metal layer 104 is formed on the intermediate dielectric layer 109, and wherein drain metal layer 104 is to electrically connect with drain electrode contact hole 14a, 14b to 14n, so that there is the relation of electric connection the drain region among each polysilicon layer 206a, 206b to 206n.
At this, source/drain region/the channel region of each polysilicon layer 206a, 206b to 206n and grid 108 are to constitute a sub-thin-film transistor, and the channel width of this each sub-thin-film transistor is Wa, Wb to Wn, channel length is L, and the channel width-over-length ratio of each sub-thin-film transistor (Wa/L, Wb/L to Wn/L) for example is between 0.1 to 8.
In a preferred embodiment, each sub-thin-film transistor is the thin-film transistor for same form, and for example each sub-thin-film transistor all is a p type thin-film transistor, or each sub-thin-film transistor all is a n type thin-film transistor.If above-mentioned sub-thin-film transistor is to be n type thin-film transistor, then the source/drain region of each sub-thin-film transistor with and channel region between more include a lightly doped drain region, for example shown in Fig. 2 A, also include lightly doped drain region 201a between the source/drain region 202a/204a in polysilicon layer 206a and its channel region 203a.
Therefore, low-temperature polysilicon film transistor of the present invention is to be formed in parallel by several sub-thin-film transistors, and each sub-thin-film transistor is to share same grid 108, the source area of each sub-thin-film transistor is to be electrically connected to same source metal 102, and the drain region of each sub-thin-film transistor is to be electrically connected to same drain metal layer 104.Because the channel length of each sub-thin-film transistor is L, channel width then is Wa, Wb to Wn, thus the raceway groove of low-temperature polysilicon film transistor wide than (W/L) be for:
W/L＝(Wa+Wb+........+Wn)/L
Low-temperature polysilicon film transistor of the present invention is to be formed in parallel by several sub-thin-film transistors with small channel breadth length ratio, when in big current practice, the electric current of each sub-thin-film transistor of flowing through is the 1/N (N is the sum of sub-thin-film transistor) of total electricity, in other words, the flow through electric current of each sub-thin-film transistor is:
Ix＝I×Wx/(Wa+Wb+........+Wn)
Ix: the wherein electric current of a sub-thin-film transistor of flowing through
I: total current
Wx: the channel width of a sub-thin-film transistor wherein
Therefore, the present invention can avoid element to cause the problem of element deterioration because of electric current is excessive.
At the low-temperature polysilicon film transistor shown in Fig. 2 A, be for grid at top type low-temperature polysilicon film transistor (Top Gate LTPS-TFT), yet, the present invention only can be used in the low-temperature polysilicon film transistor of this kind form, the present invention can also be applied in grid at bottom type low-temperature polysilicon film transistor (Bottom Gate LTPS-TFT), shown in Fig. 2 B.Be to show the wherein profile of a sub-thin-film transistor in Fig. 2 B, wherein grid 108 is to be configured on the substrate 100, and polysilicon layer 206a is the top of configuration grid 108, and also include a gate dielectric layer 107 between grid 108 and the polysilicon layer 206a, except the configuration mode of grid 108 and polysilicon layer 206a and Fig. 2 A to some extent the difference, other member and configuration mode are then identical with Fig. 2 A.
The structure of low-temperature polysilicon film transistor of the present invention is to be made of several sub-thin-film transistors institute in parallel, its arrangement is except as shown in Figure 2, be that grid 108 is to be a linear grid, source metal 102 is to be respectively a linear source metal and a linear drain metal layer with drain metal layer 104, and the arrangement of low-temperature polysilicon film transistor of the present invention can also be as shown in Figure 3.
See also shown in Figure 3, source metal 302 has several source metal contact site 302b and one source pole metal level connecting portion 302a, and each source metal contact site 302b electrically connects with each source electrode contact hole 12a, 12b to 12n, and source metal connecting portion 302a is connected in series several source metal contact sites 302b.In addition, drain metal layer 304 has several drain metal layer contact site 304b and a drain metal layer connecting portion 304a, and each drain metal layer contact site 304b electrically connects with each drain electrode contact hole 14a, 14b to 14n respectively, and drain metal layer connecting portion 304a is connected in series several drain metal layer contact sites 304b.
In another preferred embodiment, the arrangement of this low-temperature polysilicon film transistor can be as shown in Figure 4, be that its grid 408 is to be a U-shaped grid, be configured in the inside of U-shaped grid 408 and source metal 402 is correspondences, drain metal layer 404 is U-shaped drain metal layer that are configured in U type grid 408 outsides for correspondence.This kind arrangement can be provided with more sub-thin-film transistor in single low-temperature polysilicon film transistor.
In another preferred embodiment, the arrangement of this low-temperature polysilicon film transistor can be as shown in Figure 5, with Fig. 4 same be that its grid 408 is to be a U-shaped grid, be configured in the inside of U-shaped grid 408 and source metal 502 is correspondences, drain metal layer 504 is U-shaped drain metal layer that are configured in U type grid 408 outsides for correspondence.In addition, source metal 502 has several source metal contact site 502b and one source pole metal level connecting portion 502a, and each source metal contact site 502b electrically connects with each source electrode contact hole 12a, 12b to 12n, and source metal connecting portion 502a is connected in series several source metal contact sites 502b.In addition, drain metal layer 504 has several drain metal layer contact site 504b and a drain metal layer connecting portion 504a, and each drain metal layer contact site 504b electrically connects with each drain electrode contact hole 14a, 14b to 14n respectively, and drain metal layer connecting portion 504a is connected in series several drain metal layer contact sites 504b.
Above for embodiment be for several by several sub-thin-film transistors and be unified into the layout of a low-temperature polysilicon film transistor, yet the present invention is limited in the above-mentioned arrangement of lifting.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of structure of low-temperature polysilicon film transistor is characterized in that it comprises:
A plurality of polysilicon layers are configured on the substrate, wherein include one source pole district, a drain region and the channel region between this source area and this drain region in each this polysilicon layer;
One gate dielectric layer covers on this polysilicon layer;
One grid is configured on this gate dielectric layer of this channel region top;
One intermediate dielectric layer is formed on the top of this substrate, covers this grid;
A plurality of source electrode contact holes are arranged in this intermediate dielectric layer and this gate dielectric layer, and each this source electrode contact hole is electrically to contact with corresponding wherein this source area;
A plurality of drain electrode contact holes are arranged in this intermediate dielectric layer and this gate dielectric layer, and each this drain electrode contact hole is electrically to contact with corresponding wherein this drain region;
The one source pole metal level is formed on this intermediate dielectric layer, and wherein this source metal is to electrically connect with this source electrode contact hole; And
One drain metal layer is formed on this intermediate dielectric layer, and wherein this drain metal layer is to electrically connect with this drain electrode contact hole;
Wherein each this source/drain region/channel region and this grid are to constitute a sub-thin-film transistor, and the channel width of each this sub-thin-film transistor is W, and channel length is L.
2, the structure of low-temperature polysilicon film transistor according to claim 1 is characterized in that wherein said each this sub-thin-film transistor is to be a p type thin-film transistor.
3, the structure of low-temperature polysilicon film transistor according to claim 1 is characterized in that wherein said each this sub-thin-film transistor is to be a n type thin-film transistor.
4, the structure of low-temperature polysilicon film transistor according to claim 3 is characterized in that wherein said each this n type thin-film transistor more comprises a lightly mixed drain area, be configured in each this source/drain region with and channel region between.
5, the structure of low-temperature polysilicon film transistor according to claim 1, the channel width-over-length ratio W/L that it is characterized in that wherein said each this sub-thin-film transistor is between 0.1 to 8.
6, the structure of low-temperature polysilicon film transistor according to claim 1, it is characterized in that wherein said grid is to be a linear grid, and this source metal and this drain metal layer are to be respectively a linear source metal and a linear drain metal layer.
7, the structure of low-temperature polysilicon film transistor according to claim 1, it is characterized in that wherein said grid is to be a U-shaped grid, this source metal is the inside that correspondence is configured in this U-shaped grid, and this drain metal layer is a U-shaped drain metal layer that is configured in this U type grid outside for correspondence.
8, the structure of low-temperature polysilicon film transistor according to claim 1, it is characterized in that wherein said source metal has a plurality of source electrode metal layer contacting portions and one source pole metal level connecting portion, and each this source metal contact site is to electrically connect with each this source electrode contact hole, and this source metal connecting portion is that this source metal contact site is connected in series.
9, the structure of low-temperature polysilicon film transistor according to claim 1, it is characterized in that wherein said drain metal layer has a plurality of drain metal layer contact sites and a drain metal layer connecting portion, and each this drain metal layer contact site is to electrically connect with each this drain electrode contact hole respectively, and this drain metal layer connecting portion is that this drain metal layer contact site is connected in series.
10, a kind of structure of low-temperature polysilicon film transistor is characterized in that it comprises:
One grid is configured on the substrate;
One gate dielectric layer is formed on the top of this substrate, covers this grid;
A plurality of polysilicon layers are configured on this gate dielectric layer, wherein include one source pole district, a drain region and the channel region between this source area and this drain region in each this polysilicon layer, and this channel region are the tops that is positioned at this grid;
One intermediate dielectric layer is formed on the top of this substrate, covers this polysilicon layer;
A plurality of source electrode contact holes are arranged in this intermediate dielectric layer, and each this source electrode contact hole is electrically to contact with corresponding wherein this source area;
A plurality of drain electrode contact holes are arranged in this intermediate dielectric layer, and each this drain electrode contact hole is electrically to contact with corresponding wherein this drain region;
The one source pole metal level is formed on this intermediate dielectric layer, and wherein this source metal is to electrically connect with this source electrode contact hole; And
One drain metal layer is formed on this intermediate dielectric layer, and wherein this drain metal layer is to electrically connect with this drain electrode contact hole;
Wherein each this source/drain region/channel region and this grid are to constitute a sub-thin-film transistor, and the channel width of each this sub-thin-film transistor is W, and channel length is L.
11, the structure of low-temperature polysilicon film transistor according to claim 10 is characterized in that wherein said each this sub-thin-film transistor is to be a p type thin-film transistor.
12, the structure of low-temperature polysilicon film transistor according to claim 10 is characterized in that wherein said each this sub-thin-film transistor is to be a n type thin-film transistor.
13, the structure of low-temperature polysilicon film transistor according to claim 12 is characterized in that wherein said each this n type thin-film transistor more comprises a lightly mixed drain area, be configured in each this source/drain region with and channel region between.
14, the structure of low-temperature polysilicon film transistor according to claim 10, the channel width-over-length ratio W/L that it is characterized in that wherein said each this sub-thin-film transistor is between 0.1 to 8.
15, the structure of low-temperature polysilicon film transistor according to claim 10, it is characterized in that wherein said grid is to be a linear grid, and this source metal and this drain metal layer are to be respectively a linear source metal and a linear drain metal layer.
16, the structure of low-temperature polysilicon film transistor according to claim 10, it is characterized in that wherein said grid is to be a U-shaped grid, this source metal is the inside that correspondence is configured in this U-shaped grid, and this drain metal layer is a U-shaped drain metal layer that is configured in this U type grid outside for correspondence.
17, the structure of low-temperature polysilicon film transistor according to claim 10, it is characterized in that wherein said source metal has a plurality of source electrode metal layer contacting portions and one source pole metal level connecting portion, and each this source metal contact site is to electrically connect with each this source electrode contact hole, and this source metal connecting portion is that this source metal contact site is connected in series.
18, the structure of low-temperature polysilicon film transistor according to claim 10, it is characterized in that wherein said drain metal layer has a plurality of drain metal layer contact sites and a drain metal layer connecting portion, and each this drain metal layer contact site is to electrically connect with each this drain electrode contact hole respectively, and this drain metal layer connecting portion is that this drain metal layer contact site is connected in series.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031237339A CN1327531C (en) | 2003-05-19 | 2003-05-19 | Low-temperature polysilicon thin film transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031237339A CN1327531C (en) | 2003-05-19 | 2003-05-19 | Low-temperature polysilicon thin film transistor |
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| CN1549349A CN1549349A (en) | 2004-11-24 |
| CN1327531C true CN1327531C (en) | 2007-07-18 |
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| CNB031237339A Expired - Lifetime CN1327531C (en) | 2003-05-19 | 2003-05-19 | Low-temperature polysilicon thin film transistor |
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| CN105742294B (en) * | 2016-03-23 | 2019-01-15 | 深圳市华星光电技术有限公司 | The production method of TFT substrate and TFT substrate obtained |
| US10825839B2 (en) * | 2016-12-02 | 2020-11-03 | Innolux Corporation | Touch display device |
| CN106856210B (en) * | 2017-02-16 | 2019-08-02 | 北京京东方光电科技有限公司 | Thin film transistor and its manufacturing method, display base plate and display device |
| US10749036B2 (en) | 2018-08-03 | 2020-08-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof |
| CN109256429B (en) * | 2018-08-03 | 2021-01-26 | Tcl华星光电技术有限公司 | Oxide semiconductor thin film transistor and manufacturing method thereof |
| CN110137261A (en) * | 2018-10-29 | 2019-08-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW287299B (en) * | 1996-02-26 | 1996-10-01 | Taiwan Semiconductor Mfg | The manufacturing method for IC contacting structure |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW287299B (en) * | 1996-02-26 | 1996-10-01 | Taiwan Semiconductor Mfg | The manufacturing method for IC contacting structure |
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