CN100454579C - Self-driving LDMOS transistor - Google Patents
Self-driving LDMOS transistor Download PDFInfo
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- CN100454579C CN100454579C CNB2006101031017A CN200610103101A CN100454579C CN 100454579 C CN100454579 C CN 100454579C CN B2006101031017 A CNB2006101031017 A CN B2006101031017A CN 200610103101 A CN200610103101 A CN 200610103101A CN 100454579 C CN100454579 C CN 100454579C
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- controlled transistor
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 230000037361 pathway Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000005516 deep trap Effects 0.000 claims 7
- 230000000295 complement effect Effects 0.000 claims 3
- 239000004020 conductor Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
The present invention provides a self-driven LDMOS which uses a parasitic resistor which is positioned between a drain terminal and an auxiliary zone. The parasitic resistor is formed between two depletion boundaries of a quasi-connection N-shaped well. When the two depletion boundaries are pinched off, the grid voltage potential of a grid terminal is maintained at the drain voltage potential of a drain terminal. Because the grid voltage potential is equal to or higher than starting threshold voltage, the LDMOS is correspondingly switched on. Besides, when the parasitic resistor is made, no extra grain space and mask processing are not needed; in addition, the parasitic resistor of the present invention can not lower the breakdown voltage and the operating speed of the LDMOS; in addition, the grid voltage potential can not change with the drain voltage potential increasing when the two depletion boundaries are pinched off.
Description
Technical field
The present invention relates to semiconductor technology, or rather, the present invention relates to ldmos transistor technology.
Background technology
The self-driving LDMOS transistor technology is suggested successively, and wherein a kind of technology comprises that the actuation threshold voltage that injects ldmos transistor with extra ion is adjusted to the low voltage current potential.Yet the inferior position of this technology is the puncture voltage of higher leakage current, reduction and extra mask process cost.Another technology utilizes the capacitor parasitics (parasitic drain-to-gate capacitor) of drain-to-gate to come the coupled gates voltage potential, to make self-driving LDMOS transistor.Yet the electric capacity of the capacitor parasitics of drain-to-gate changes in response to the depletion capacitor that is connected in series, and therefore the grid voltage current potential can not be controlled at required voltage potential exactly.Another technology is then utilized voltage divider, it is formed by the high value polycrystalline resistor (high resistance poly resistor) between the grid of ldmos transistor and drain electrode with from the resistor that grid is connected to substrate, to be provided for the grid voltage current potential of conducting ldmos transistor.Yet the inferior position of this invention comprises that the high value of polycrystalline resistor changes, extra mask process cost and tube core greatly take up room.
Summary of the invention
The present invention proposes a kind of self-driving LDMOS transistor, and it utilizes the parasitic resistor between drain terminal and auxiliary area.Parasitic resistor is formed between two depletion boundaries.When two depletion boundaries pinch ofves, the grid voltage current potential of ldmos transistor is maintained at the drain voltage current potential at drain terminal place.With LDNMOS is example, owing to the actuation threshold voltage that the grid voltage current potential is designed to be equal to or higher than ldmos transistor, so correspondingly conducting of ldmos transistor.
According to the present invention, making parasitic resistor does not need extra mask process and extra crystal grain space.In addition, parasitic resistor of the present invention can not reduce the puncture voltage and the service speed of ldmos transistor.In addition, when two depletion boundaries pinch ofves, the grid voltage current potential is no longer responded the increase of drain voltage current potential and is changed.
Should be appreciated that the general description of front and following detailed are exemplary, and be intended to provide the of the present invention further explaination of being advocated.Further target and advantage will be by becoming obvious to subsequently the description and the consideration of accompanying drawing.
Description of drawings
The present invention includes accompanying drawing providing, and accompanying drawing is incorporated in this specification and is formed wherein a part into to further understanding of the present invention.The description of drawings embodiments of the invention, and with describe content one and be used from explaination principle of the present invention.
Fig. 1 shows the cross-sectional view of self-driving LDMOS transistor according to an embodiment of the invention.
Fig. 2 shows the cross-sectional view according to the self-driving LDMOS transistor with two depletion boundaries of the embodiment of the invention.
Fig. 3 shows the performance plot of the grid voltage current potential of self-driving LDMOS transistor to the drain voltage current potential.
Embodiment
Fig. 1 shows the cross-sectional view of self-driving LDMOS transistor 100 according to the preferred embodiment of the invention.Ldmos transistor 100 comprises P type substrate 90, and its electrical resistivity range is from 10ohm-cm to 100ohm-cm.Standard with N type conductive ion connects dark N type trap (quasi-linked deep N-typewell) 210 and is formed in the P type substrate 90.The accurate scope that connects the doping content of dark N type trap 210 is from 1.7E17/cm
3To 8.3E18/cm
3The accurate scope that connects the degree of depth of dark N type trap 210 is to 10 μ m from 2 μ m.The accurate N type trap 210 that connects has the gap, and it has width G, scope between 0 μ m between the 20 μ m.Wherein, the accurate step that connects dark N type trap 210 of formation also is included in 1000 ℃～1200 ℃ heat of carrying out 6～12 hours down and drives in processing.
As shown in fig. 1, the dark N type trap 210 of accurate connection has discontinuous polarity distributed architecture 220, and it is made up of accurate dark N type trap 210 of connection of part and part P type substrate 90.Described discontinuous polarity distributed architecture 220 is parallel to the conductive channel 81 of ldmos transistor 100.P type trap 35 (also can be implemented by P type body (P-type body)) is formed at described standard with the P type trap 25 with P-type conduction ion and is connected in the dark N type trap 210.The scope of P type trap 25 and 35 doping content is from 3.3E17/cm
3To 1E19/cm
3The scope of the P type trap 25 and 35 the degree of depth is to 5 μ m from 1 μ m.Wherein, the step that forms P type trap 25 and 35 more is included in 900 ℃～1100 ℃ heat of carrying out 2～6 hours down and drives in processing.In addition, field oxide 330,331 and 332 is formed at P type substrate 90 tops in order to as isolation structure.
Grid oxic horizon 82 is formed on the conduction pathway 81.The scope of the thickness of grid oxic horizon 82 is from 300
To 1000
Polysilicon gate layer 80 is formed at grid oxic horizon 82 and field oxide 330 tops, is used for controlling the electric current of conduction pathway 81.
Next, on P type substrate 90, form dielectric layer 120.Electrode 60 (for example metal level) is connected with the drain region, to form the drain terminal of ldmos transistor 100.Electrode 70 (for example metal level) is connected with contact area with the source region, to form the source terminal of ldmos transistor 100.Dielectric layer 150 is formed at P type substrate 90 tops.Electrode 86 (for example metal level) is connected with polysilicon gate layer 80 with auxiliary area, and this makes the voltage potential equalization of polysilicon gate layer 80 and auxiliary area.
Referring to Fig. 2 and Fig. 3, when the positive voltage current potential is applied to the drain terminal of ldmos transistor 100, the drain voltage current potential V at the drain terminal place of transistor 100
DTo connect dark N type trap 210 via standard and conduct, to set up grid voltage current potential V at polysilicon gate layer 80 place
GAs shown in Figure 3, grid voltage current potential V
GAlong with drain voltage current potential V
DLinear ratio ground increases.
Cause reverse bias owing to the positive voltage current potential is applied to the drain terminal of ldmos transistor 100, so as drain voltage current potential V
DWhen increasing continuously, two depletion boundaries 30a and 30b will form and start approaching each other.Parasitic resistor is formed between drain terminal and the auxiliary area.The resistance of parasitic resistor changes according to the average distance between two depletion boundaries 30a and the 30b.When two depletion boundaries 30a and 30b pinch off (it is defined as the pinch off situation), the grid voltage current potential V at polysilicon gate layer 80 place
GTo no longer increase.Simultaneously, grid voltage current potential V
GBe maintained at predetermined voltage potential V
PINCH-OFF, be example with LDNMOS, it is designed to be equal to or higher than the actuation threshold voltage of ldmos transistor 100.Therefore, ldmos transistor 100 is with correspondingly conducting.In addition, when two depletion boundaries 30a and 30b pinch off, the impedance of parasitic resistor is higher, thereby has realized the utmost point low current leakage of ldmos transistor 100.The standby power consumption that therefore, can show the reduction ldmos transistor 100 that lands.Therefore improve the operating efficiency of ldmos transistor.
Two the depletion boundaries 30a of gap collocation that have width and be G help to form the accurate pinch off structure that is connected dark N type trap 210 with 30b.In addition, ldmos transistor 100 is voltage-controlled transistor and does not need to understand the external circuit in the outer crystal grain space of occupying volume to form self-driven structure.This has further reduced manufacturing cost.
It will be apparent to those skilled in the art that, can under the situation that does not break away from category of the present invention or spirit, make various modifications and variations structure of the present invention.In view of aforementioned content, if modifications and variations of the present invention in the category of claims and its equivalent, then these modifications and variations are contained in the present invention.
Claims (9)
1. a voltage-controlled transistor comprises voltage control terminal, source terminal and drain terminal; The change in voltage at the corresponding described drain terminal of the voltage potential at wherein said voltage control terminal place place and changing; When the pinch off situation of described voltage-controlled transistor takes place, the voltage potential at described voltage control terminal place will be controlled to maintain predetermined voltage potential; When the voltage potential at described voltage control terminal place surpassed described predetermined voltage potential, the voltage potential at described voltage control terminal place will no longer change along with the drain voltage potential change at described drain terminal place; Wherein discontinuous polarity distributed architecture is formed between described drain terminal and the described voltage control terminal; Described voltage control terminal is connected to the auxiliary area that has identical doping polarity with described drain terminal; Two depletion boundaries of wherein said drain voltage control of Electric potentials; When described two depletion boundaries pinch ofves, the voltage potential at described voltage control terminal place will be controlled to maintain described predetermined voltage potential.
2. voltage-controlled transistor according to claim 1, wherein as long as described voltage control terminal is controlled to maintain described predetermined voltage potential, described voltage-controlled transistor is with regard to conducting.
3. voltage-controlled transistor according to claim 1, wherein complementary doped region is arranged between the described drain terminal and described voltage control terminal of described voltage-controlled transistor, the doping polarity complementation of the doping polarity of wherein said complementary doped region and the described drain terminal of described voltage-controlled transistor.
4. voltage-controlled transistor according to claim 1, wherein said discontinuous polarity distributed architecture is made up of doped region, the doping polarity complementation of the doping polarity of described doped region and described drain terminal, wherein said doped region are parallel to the conduction pathway of described voltage-controlled transistor and help described two depletion boundaries pinch ofves.
5. voltage-controlled transistor, utilize bias voltage to change by two depletion boundaries that produce between complementary ion, described two depletion boundaries that the resistance value of the parasitic resistor between the drain terminal of wherein said voltage-controlled transistor and the voltage control terminal is controlled according to the drain voltage current potential at described drain terminal place and changing, wherein when described two depletion boundaries pinch ofves, the voltage potential at described voltage control terminal place is maintained at the described drain voltage current potential at described drain terminal place.
6. voltage-controlled transistor according to claim 5, wherein when the voltage potential at described voltage control terminal place is maintained at predetermined voltage potential, described voltage-controlled transistor conducting.
7. technology that is used to make voltage-controlled transistor comprises following steps:
Substrate is provided;
In described substrate, form the accurate deep trap that connects;
In described substrate, form doping polarity is connected the doping polarity complementation of deep trap with described standard trap;
On described substrate, form oxide layer, be used to serve as isolation structure;
Above described accurate connection deep trap, form grid oxic horizon;
Form a plurality of heavily doped regions in the deep trap in described accurate the connection; With
Form a plurality of conductors, the grid that is used to connect described voltage-controlled transistor is connected deep trap with described standard.
8. the technology that is used to make voltage-controlled transistor according to claim 7, the step that wherein forms described accurate connection deep trap also is included in 1000 ℃～1200 ℃ heat of carrying out 6～12 hours down and drives in processing.
9. the technology that is used to make voltage-controlled transistor according to claim 7 wherein forms doping polarity is connected the doping polarity complementation of deep trap with described standard the step of described trap and also is included in 900 ℃～1100 ℃ heat of carrying out 2～6 hours down and drives in processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101031017A CN100454579C (en) | 2006-07-03 | 2006-07-03 | Self-driving LDMOS transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101031017A CN100454579C (en) | 2006-07-03 | 2006-07-03 | Self-driving LDMOS transistor |
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| Publication Number | Publication Date |
|---|---|
| CN1877862A CN1877862A (en) | 2006-12-13 |
| CN100454579C true CN100454579C (en) | 2009-01-21 |
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| CNB2006101031017A Expired - Fee Related CN100454579C (en) | 2006-07-03 | 2006-07-03 | Self-driving LDMOS transistor |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789444A (en) * | 2010-01-28 | 2010-07-28 | 上海宏力半导体制造有限公司 | First layer of metal capable of increasing breakdown voltage of MOS transistor |
| CN103050512A (en) * | 2011-10-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | Non-epitaxial high-voltage insulating N-type LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure |
| CN105870188B (en) * | 2016-04-19 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS device and process |
| CN105810740B (en) * | 2016-04-19 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS device and process |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475870B1 (en) * | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
| US6570219B1 (en) * | 1996-11-05 | 2003-05-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| CN1641886A (en) * | 2004-01-16 | 2005-07-20 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN1661812A (en) * | 2004-02-24 | 2005-08-31 | 崇贸科技股份有限公司 | High voltage LDMOS transistor having an isolated structure |
-
2006
- 2006-07-03 CN CNB2006101031017A patent/CN100454579C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6570219B1 (en) * | 1996-11-05 | 2003-05-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| US6475870B1 (en) * | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
| CN1641886A (en) * | 2004-01-16 | 2005-07-20 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN1661812A (en) * | 2004-02-24 | 2005-08-31 | 崇贸科技股份有限公司 | High voltage LDMOS transistor having an isolated structure |
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| CN1877862A (en) | 2006-12-13 |
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