CN117476686A - Display panel and manufacturing method thereof - Google Patents

Display panel and manufacturing method thereof Download PDF

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Publication number
CN117476686A
CN117476686A CN202310415576.3A CN202310415576A CN117476686A CN 117476686 A CN117476686 A CN 117476686A CN 202310415576 A CN202310415576 A CN 202310415576A CN 117476686 A CN117476686 A CN 117476686A
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China
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sub
semiconductor layer
display panel
region
layer
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罗传宝
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202310415576.3A priority Critical patent/CN117476686A/en
Publication of CN117476686A publication Critical patent/CN117476686A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the application discloses a display panel and a manufacturing method of the display panel, wherein at least one thin film transistor comprises: the semiconductor layer comprises a first sub-semiconductor layer and a second sub-semiconductor layer which are arranged on a substrate, the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at the first end part of the first sub-semiconductor layer, the semiconductor layer comprises a source electrode area and a drain electrode area which are positioned at the opposite ends, the source electrode area is positioned at the second end part of the first sub-semiconductor layer which is far away from the first end part, and the drain electrode area is positioned at least at the first sub-part; the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with the drain electrode region part positioned at the first sub-part; wherein the resistivity of the material of the undoped second sub-semiconductor layer is smaller than the resistivity of the material of the undoped first sub-semiconductor layer. The method and the device can avoid the threshold voltage from significantly changing due to carrier degradation.

Description

Display panel and manufacturing method thereof
Technical Field
The present disclosure relates to the field of display, and in particular, to a display panel and a method for manufacturing the display panel.
Background
With the development of display technology, display panels have been widely used in people's lives, such as display screens of mobile phones, computers, televisions, and the like. With the progress of life and the development of technology, display performance requirements of display panels are higher and higher, pixel electrodes in the display panels are driven by thin film transistors, and the performance of the thin film transistors directly influences the performance of the display panels.
However, the conventional thin film transistor has a problem that the threshold voltage significantly fluctuates due to carrier degradation when the thin film transistor is operated at a high gate voltage.
Disclosure of Invention
The embodiment of the application provides a display panel and a manufacturing method of the display panel, which can solve the problem that the threshold voltage is obviously changed due to carrier degradation when the existing thin film transistor works under high gate voltage.
The embodiment of the application provides a display panel, including a substrate and set up in a plurality of thin film transistors on the substrate, at least one thin film transistor includes:
the semiconductor layer comprises a first sub-semiconductor layer and a second sub-semiconductor layer which are arranged on the substrate, the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer with the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at a first end part of the first sub-semiconductor layer, the semiconductor layer comprises a source region and a drain region which are positioned at opposite ends, the source region is positioned at a second end part of the first sub-semiconductor layer which is far away from the first end part, and the drain region is positioned at least at the first sub-part;
a source electrode and a drain electrode, wherein the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with a drain electrode region part positioned at the first sub-part;
wherein the resistivity of the material of the undoped second sub-semiconductor layer is smaller than the resistivity of the material of the undoped first sub-semiconductor layer.
Optionally, in some embodiments of the present application, the second sub-semiconductor layer further includes a second sub-portion connected to the first sub-portion, and the second sub-portion is lapped on the first end portion.
Optionally, in some embodiments of the present application, the drain region is further located partially at the first end of the first sub-semiconductor layer.
Optionally, in some embodiments of the present application, the resistance at the drain region site of the second sub-semiconductor layer is less than the resistance at the drain region site of the first sub-semiconductor layer.
Optionally, in some embodiments of the present application, the thin film transistor further includes:
a gate insulating layer disposed on the semiconductor layer;
the grid electrode is arranged on the grid electrode insulating layer;
and the source electrode and the drain electrode are arranged on the interlayer insulating layer.
Optionally, in some embodiments of the present application, an orthographic projection of the gate electrode on the substrate at least partially overlaps an orthographic projection of the second sub-site on the substrate.
Optionally, in some embodiments of the present application, the materials of the first sub-semiconductor layer and the second sub-semiconductor layer are both oxide semiconductor materials.
Optionally, in some embodiments of the present application, the material of the first sub-semiconductor layer is a crystalline oxide semiconductor material or a rare earth doped oxide semiconductor material.
Optionally, in some embodiments of the present application, the material of the first sub-semiconductor layer is an oxide semiconductor material, and the material of the second sub-semiconductor layer is a non-oxide semiconductor material.
Correspondingly, the embodiment of the application also provides a manufacturing method of the display panel, which comprises the following steps:
providing a substrate;
forming a semiconductor layer on the substrate, wherein forming the semiconductor layer comprises forming a first sub-semiconductor layer and forming a second sub-semiconductor layer, wherein the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at a first end part of the first sub-semiconductor layer, and the resistivity of the material of the undoped second sub-semiconductor layer is smaller than that of the material of the undoped first sub-semiconductor layer;
forming a gate insulating layer on the semiconductor layer, and forming a gate electrode on the gate insulating layer;
a doping process is carried out on the semiconductor layer to form a source electrode region and a drain electrode region, the source electrode region and the drain electrode region are located at two opposite ends of the semiconductor layer, the source electrode region is located at a second end part of the first sub-semiconductor layer, which is far away from the first end part, and the drain electrode region is located at least at the first sub-part;
forming an interlayer insulating layer on the gate electrode;
forming a source electrode and a drain electrode on the interlayer insulating layer, wherein the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with the drain electrode region part at the first sub-part
In an embodiment of the present application, a display panel and a method for manufacturing the display panel are provided, the display panel includes a substrate and a plurality of thin film transistors disposed on the substrate, at least one thin film transistor includes: the semiconductor layer comprises a first sub-semiconductor layer and a second sub-semiconductor layer which are arranged on a substrate, the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at the first end part of the first sub-semiconductor layer, the semiconductor layer comprises a source electrode area and a drain electrode area which are positioned at the opposite ends, the source electrode area is positioned at the second end part of the first sub-semiconductor layer which is far away from the first end part, and the drain electrode area is positioned at least at the first sub-part; the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with the drain electrode region part positioned at the first sub-part; wherein the resistivity of the material of the undoped second sub-semiconductor layer is smaller than the resistivity of the material of the undoped first sub-semiconductor layer. According to the thin film transistor, the drain region is made of the semiconductor material with lower resistance, the thin film transistor is of a double-layer structure, the carrier concentration is higher, the voltage drop of the drain voltage at the drain region can be greatly reduced due to the higher carrier concentration at the drain region under the condition of higher drain voltage, the electric field is weakened at the lower voltage drop, so that the movement of hot carriers can be reduced, the threshold voltage is obviously changed due to carrier degradation is avoided, and the performance of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a first part of a film layer of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a second partial film layer of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating steps of a method for manufacturing a display panel according to a second embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a first intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating a second intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a third intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating a fourth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating a fifth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 9 is a schematic diagram illustrating a sixth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 10 is a schematic diagram illustrating a seventh intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure;
fig. 11 is a schematic diagram illustrating an eighth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
The application provides a display panel, the display panel includes the base and sets up a plurality of thin film transistors on the base, and at least one thin film transistor includes: the semiconductor layer comprises a first sub-semiconductor layer and a second sub-semiconductor layer which are arranged on a substrate, the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at the first end part of the first sub-semiconductor layer, the semiconductor layer comprises a source electrode area and a drain electrode area which are positioned at the opposite ends, the source electrode area is positioned at the second end part of the first sub-semiconductor layer which is far away from the first end part, and the drain electrode area is positioned at least at the first sub-part; the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with the drain electrode region part positioned at the first sub-part; wherein the resistivity of the material of the undoped second sub-semiconductor layer is smaller than the resistivity of the material of the undoped first sub-semiconductor layer. The application also provides a manufacturing method of the display panel, and the manufacturing method is described in detail below. The following description of the embodiments is not intended to limit the preferred embodiments.
Example 1
Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of a first partial film layer of a display panel according to a first embodiment of the present disclosure; fig. 2 is a schematic cross-sectional view of a second partial film layer of a display panel according to an embodiment of the disclosure.
The present application provides a display panel 100, the display panel 100 includes a substrate 11 and a plurality of thin film transistors disposed on the substrate 11, at least one thin film transistor including a semiconductor layer 145, a source electrode 191 and a drain electrode 192. The semiconductor layer 145 includes a first sub-semiconductor layer 14 and a second sub-semiconductor layer 15 disposed on the substrate 11, the second sub-semiconductor layer 15 includes at least a first sub-portion 151 disposed in the same layer as the first sub-semiconductor layer 14, the first sub-portion 151 is connected to the first sub-semiconductor layer 14 at a first end 1401 of the first sub-semiconductor layer 14, the semiconductor layer 145 includes a source region 1452 and a drain region 1453 located at opposite ends, the source region 1452 is located at a second end 1402 of the first sub-semiconductor layer 14 away from the first end 1401, and the drain region 1453 is located at least at the first sub-portion 151; source 191 is directly connected to source region 1452 and drain 192 is directly connected to a portion of drain region 1453 located at first sub-portion 151; wherein the resistivity of the material of the undoped second sub-semiconductor layer 15 is smaller than the resistivity of the material of the undoped first sub-semiconductor layer 14.
Specifically, the semiconductor layer 145 includes a first sub-semiconductor layer 14 and a second sub-semiconductor layer 15 disposed on the substrate 11, and the undoped second sub-semiconductor layer 15 has a material having a resistivity smaller than that of the undoped first sub-semiconductor layer 14. I.e. the materials of the first sub-semiconductor layer 14 and the second sub-semiconductor layer 15 are different and the material of the second sub-semiconductor layer 15 is smaller than the resistivity of the material of the first sub-semiconductor layer 14.
Specifically, the second sub-semiconductor layer 15 includes at least a first sub-portion 151 disposed on the same layer as the first sub-semiconductor layer 14, the first sub-portion 151 is connected to the first sub-semiconductor layer 14 at a first end 1401 of the first sub-semiconductor layer 14, the first sub-portion 151 of the second sub-semiconductor layer 15 is disposed on the same layer as the first sub-semiconductor layer 14, and fig. 1 illustrates that the first sub-portion 151 and the first sub-semiconductor layer 14 of the second sub-semiconductor layer 15 are disposed on the buffer layer 13.
Specifically, the source electrode 191 is directly connected to the source region 1452 through a via hole, the drain electrode 192 is directly connected to the drain region 1453 located at the first sub-portion 151 through another via hole, and the drain electrode 192 is electrically connected to the first sub-semiconductor layer 14 through the drain electrode 192.
Specifically, fig. 1 illustrates that the source region 1452 and the channel 1451 of the semiconductor layer 145 are located in the first sub-semiconductor layer 14, and the drain region 1453 is located in at least the first sub-portion 151 of the second sub-semiconductor layer 15.
In the thin film transistor of the present embodiment, the drain region 1453 is made of a semiconductor material with lower resistance (i.e., the second sub-semiconductor layer 15), and has a double-layer structure, so that the higher carrier concentration can greatly reduce the voltage drop of the drain voltage at the location where the higher carrier concentration is, and the lower the voltage drop is, the weaker the electric field is, so that the movement of hot carriers can be reduced, thereby avoiding the occurrence of significant variation of threshold voltage caused by carrier degradation and improving the performance of the display panel.
In some embodiments, the second sub-semiconductor layer 15 further includes a second sub-portion 152 connected to the first sub-portion 151, the second sub-portion 152 being disposed on the first end 1401.
Specifically, as shown in fig. 1 and 2, the first sub-portion 151 and the second sub-portion 152 are connected to each other to form a whole, the second sub-portion 152 is disposed on the first end portion 1401, the first sub-portion 151 is located at one side of the first end portion 1401, and poor contact between the first sub-semiconductor layer 14 and the second sub-semiconductor layer 15 can be avoided during the manufacturing process of the display panel 100 or the thin film transistor, so that stability and manufacturing yield of the thin film transistor can be improved.
In some embodiments, the drain region 1453 is also partially located at the first end 1401 of the first sub-semiconductor layer 14.
Specifically, as shown in fig. 2, the drain region 1453 includes the first end portion 1401 of the first sub-semiconductor layer 14 and the first sub-portion 151 of the second sub-semiconductor layer, and during the manufacturing process of the display panel and the thin film transistor, the contact portion between the first end portion 1401 and the first sub-portion 151 may be entirely doped, thereby improving the stability and the manufacturing yield of the thin film transistor.
In some embodiments, the resistance at the location of the drain region 1453 of the second sub-semiconductor layer 15 is smaller than the resistance at the location of the drain region 1453 of the first sub-semiconductor layer 14.
Specifically, the drain region 1453 is doped at the same time at the drain region 1453 of the second sub-semiconductor layer 15 and the drain region 1453 of the first sub-semiconductor layer 14 in one ion implantation process, so that the ion doping concentrations at the drain region 1453 of the second sub-semiconductor layer 15 and the drain region 1453 of the first sub-semiconductor layer 14 are the same, such that the resistance at the drain region 1453 of the second sub-semiconductor layer 15 is smaller than the resistance at the drain region 1453 of the first sub-semiconductor layer 14.
In some embodiments, the thin film transistor further comprises: a gate insulating layer 16 disposed on the semiconductor layer; a gate electrode 17 disposed on the gate insulating layer 16; an interlayer insulating layer 18 is provided on the gate electrode 17, and a source electrode 191 and a drain electrode 192 are provided on the interlayer insulating layer 18.
Specifically, the thin film transistor includes a semiconductor layer 145, a gate insulating layer 16, a gate electrode 17, an interlayer insulating layer 18, a source electrode 191, and a drain electrode 192.
Specifically, fig. 1 and 2 illustrate that the layer structure of the display panel 100 includes sequentially stacked: the pixel electrode comprises a substrate 11, a light shielding layer 12 arranged on the substrate 11, a buffer layer 13 arranged on the light shielding layer 12, a semiconductor layer 145 arranged on the buffer layer 13, a gate insulating layer 16 arranged on the semiconductor layer 145, a gate 17 arranged on the gate insulating layer 16, an interlayer insulating layer 18 arranged on the gate 17, a source-drain metal layer 19 arranged on the interlayer insulating layer 18, a first insulating layer 20 arranged on the source-drain metal layer 19 and a pixel electrode 21 arranged on the first insulating layer 20. The source-drain metal layer 19 is patterned to form a source electrode 191 and a drain electrode 192, and the pixel electrode 21 is connected or electrically connected to the drain electrode 192. The semiconductor layer 145 includes a first sub-semiconductor layer 14 and a second sub-semiconductor layer disposed on the first sub-semiconductor layer 14.
In some embodiments, the orthographic projection of gate 17 onto substrate 11 at least partially overlaps the orthographic projection of second sub-portion 152 onto substrate 11.
Specifically, as shown in fig. 1, the orthographic projection of the gate 17 on the substrate 11 at least partially overlaps with the orthographic projection of the second sub-portion 152 on the substrate 11, i.e., the second sub-portion 152 is at least partially disposed directly under the gate 17.
In some embodiments, the materials of the first sub-semiconductor layer 14 and the second sub-semiconductor layer 15 are both oxide semiconductor materials.
Specifically, in the thin film transistor in which the first semiconductor layer 14 is an oxide semiconductor material, when the thin film transistor is operated at a high gate voltage, the problem that the threshold voltage significantly fluctuates due to carrier degradation is more serious, the oxide semiconductor material is also used as the material of the second semiconductor layer 15, and the resistivity of the material of the undoped second semiconductor layer 15 is smaller than that of the undoped first semiconductor layer 14, so that the carrier concentration in the thin film transistor is higher, and in the case of higher drain voltage, the voltage drop of the drain voltage at the place can be greatly reduced by the higher carrier concentration, and the lower the voltage drop, the weaker the electric field is, so that the movement of hot carriers can be reduced, thereby avoiding the occurrence of significant fluctuation of the threshold voltage due to carrier degradation, and improving the performance of the display panel.
In some embodiments, the material of the first sub-semiconductor layer 14 is a crystalline oxide semiconductor material or a rare earth doped oxide semiconductor material.
Specifically, the material of the first sub-semiconductor layer 14 is a crystalline oxide semiconductor material or a rare earth doped oxide semiconductor material, and the resistance of the first sub-semiconductor layer 14 can be made larger.
In some embodiments, the material of the first sub-semiconductor layer 14 is an oxide semiconductor material, and the material of the second sub-semiconductor layer 15 is a non-oxide semiconductor material.
Specifically, in the thin film transistor in which the first sub-semiconductor layer 14 is an oxide semiconductor material, the problem of significant variation in threshold voltage due to carrier degradation is more serious when the thin film transistor is operated at a high gate voltage, and in this case, the material of the second sub-semiconductor layer may also be a non-oxide semiconductor material as long as the specific resistance of the material of the undoped second sub-semiconductor layer 15 is smaller than that of the material of the undoped first sub-semiconductor layer 14.
Example two
The present embodiment provides a method for manufacturing a display panel, and the display panel of any of the above embodiments may be manufactured by the method for manufacturing a display panel of the present embodiment.
Referring to fig. 3 to 10, fig. 3 is a schematic diagram illustrating steps of a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 4 is a schematic diagram illustrating a first intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 5 is a schematic diagram illustrating a second intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 6 is a schematic diagram illustrating a third intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 7 is a schematic diagram illustrating a fourth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 8 is a schematic diagram illustrating a fifth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 9 is a schematic diagram illustrating a sixth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 10 is a schematic diagram illustrating a seventh intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure; fig. 11 is a schematic diagram illustrating an eighth intermediate process of a manufacturing method of a display panel according to a second embodiment of the present disclosure.
As shown in fig. 3, the present embodiment provides a method for manufacturing a display panel, including the steps of: s100, S200, S300, S400, S500, and S600.
S100, providing a substrate.
Specifically, as shown in fig. 4, a substrate 11 is provided, a light shielding layer 12 is formed on the substrate 11, the material of the light shielding layer 12 may be Mo or Mo/Al or Mo/Cu or MoTi/Cu/MoTi or Ti/Al/Ti or Ti/Cu/Ti or Mo/Cu/IZO or IZO/Cu/IZO or Mo/Cu/ITO, and the patterning is performed.
And S200, forming a semiconductor layer on the substrate, wherein the forming of the semiconductor layer comprises the steps of forming a first sub-semiconductor layer and then forming a second sub-semiconductor layer, wherein the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at the first end part of the first sub-semiconductor layer, and the resistivity of the material of the undoped second sub-semiconductor layer is smaller than that of the material of the undoped first sub-semiconductor layer.
Specifically, as shown in fig. 4, 5, and 6, the buffer layer 13 is formed on the light shielding layer 12, and the semiconductor 145 is formed on the buffer layer 13.
Specifically, forming the semiconductor layer 145 on the substrate 11 includes forming the first sub-semiconductor layer 14 first and forming the second sub-semiconductor layer 15 later, wherein the second sub-semiconductor layer 15 includes at least a first sub-portion 151 disposed in the same layer as the first sub-semiconductor layer 14, the first sub-portion 151 connecting the first sub-semiconductor layer 14 at a first end 1401 of the first sub-semiconductor layer 14, wherein a resistivity of a material of the undoped second sub-semiconductor layer 15 is smaller than a resistivity of a material of the undoped first sub-semiconductor layer 14.
Specifically, the patterned first sub-semiconductor layer 14 may be formed first, and then the patterned second sub-semiconductor layer 15 may be formed.
S300, forming a gate insulating layer on the semiconductor layer, and forming a gate electrode on the gate insulating layer.
Specifically, as shown in fig. 7, a gate insulating layer 16 is formed on the semiconductor layer 145, and a gate electrode 17 is formed on the gate insulating layer 16.
Specifically, the film material of the gate insulating layer can be SiO x Or Al2O 3 /SiN x /SiO x ，SiO x /SiN x /SiO x Etc., the film material of the gate electrode 17 may be Mo, or Mo/Al, or Mo/Cu, or MoTi/Cu/MoTi, or Ti/Al/Ti, or Ti/Cu/Ti, or Mo/Cu/IZO, or IZO/Cu/IZO, or Mo/Cu/ITO, and patterning thereof, followed by patterning the gate insulating layer by self-alignment, and doping of the source and drain regions is completed.
S400, a doping process is carried out on the semiconductor layer to form a source region and a drain region, the source region and the drain region are located at two opposite ends of the semiconductor layer, the source region is located at a second end of the first sub-semiconductor layer far away from the first end, and the drain region is located at least at the first sub-position.
Specifically, as shown in fig. 8, a doping process is performed on the semiconductor layer 145 to form a source region 1452 and a drain region 1453, the source region 1452 and the drain region 1453 are located at opposite ends of the semiconductor layer 145, the source region 1452 is located at a second end 1402 of the first sub-semiconductor layer 14 away from the first end 1401, and the drain region 1453 is located at least at the first sub-portion 151.
And S500, forming an interlayer insulating layer on the gate electrode.
Specifically, as shown in fig. 9, an interlayer insulating layer 18 is formed on the gate electrode 16.
Specifically, the interlayer insulating layer 18 may be SiO x Or SiN x Or SiN x /SiO x Or SiNO x Etc., and patterning it.
And S600, forming a source electrode and a drain electrode on the interlayer insulating layer, wherein the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with a drain electrode region part positioned at the first sub-part.
Specifically, as shown in fig. 10, a source electrode 191 and a drain electrode 192 are formed on the interlayer insulating layer 18, the source electrode 191 is directly connected to the source region 1452, and the drain electrode 192 is directly connected to a portion of the drain region 1453 located at the first sub-portion 151.
Specifically, the material of the source electrode 191 and the drain electrode 192 may be Mo, mo/Al, mo/Cu, moTi/Cu/MoTi, ti/Al/Ti, ti/Cu/Ti, mo/Cu/IZO, IZO/Cu/IZO, or Mo/Cu/ITO, and patterning thereof.
Further, as shown in fig. 11, the manufacturing method of the display panel may further include: a first insulating layer 20 is formed on the source electrode 191 and the drain electrode 192, and a pixel electrode 21 is formed on the first insulating layer 20, the pixel electrode 21 being connected to the drain electrode 192.
Specifically, the first insulating layer 20 may be SiO x Or SiN x Or SiN x /SiO x Or SiNO x Etc., and patterning.
Specifically, the material of the pixel electrode 21 may be ITO, or IZO, or ITO/Ag/ITO, or IZO/Ag/IZO, or Mo/Cu, or MoTi/Cu/MoTi, or the like.
It should be noted that, the structure or material of the display panel manufactured in the second embodiment is the same as that of the display panel in any one of the first embodiments, and has the beneficial effects in the first embodiment, which is not described herein.
The foregoing has described in detail a display panel and a method for manufacturing the display panel provided in the embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, and the description of the foregoing examples is only for aiding in understanding the method and core concept of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A display panel comprising a substrate and a plurality of thin film transistors disposed on the substrate, at least one of the thin film transistors comprising:
the semiconductor layer comprises a first sub-semiconductor layer and a second sub-semiconductor layer which are arranged on the substrate, the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer with the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at a first end part of the first sub-semiconductor layer, the semiconductor layer comprises a source region and a drain region which are positioned at opposite ends, the source region is positioned at a second end part of the first sub-semiconductor layer which is far away from the first end part, and the drain region is positioned at least at the first sub-part;
a source electrode and a drain electrode, wherein the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with a drain electrode region part positioned at the first sub-part;
wherein the resistivity of the material of the undoped second sub-semiconductor layer is smaller than the resistivity of the material of the undoped first sub-semiconductor layer.
2. The display panel of claim 1, wherein the second sub-semiconductor layer further comprises a second sub-portion connecting the first sub-portion, the second sub-portion overlying the first end portion.
3. The display panel of claim 1, wherein the drain region is further located partially at the first end of the first sub-semiconductor layer.
4. The display panel of claim 3, wherein a resistance of a drain region portion located in the second sub-semiconductor layer is smaller than a resistance of a drain region portion located in the first sub-semiconductor layer.
5. The display panel according to any one of claims 1 to 4, wherein the thin film transistor further comprises:
a gate insulating layer disposed on the semiconductor layer;
the grid electrode is arranged on the grid electrode insulating layer;
and the source electrode and the drain electrode are arranged on the interlayer insulating layer.
6. The display panel of claim 5, wherein an orthographic projection of the gate electrode on the substrate at least partially overlaps an orthographic projection of the second sub-portion on the substrate.
7. The display panel of claim 1, wherein the materials of the first sub-semiconductor layer and the second sub-semiconductor layer are both oxide semiconductor materials.
8. The display panel of claim 6, wherein the material of the first sub-semiconductor layer is a crystalline oxide semiconductor material or a rare earth doped oxide semiconductor material.
9. The display panel of claim 1, wherein a material of the first sub-semiconductor layer is an oxide semiconductor material and a material of the second sub-semiconductor layer is a non-oxide semiconductor material.
10. A method of manufacturing a display panel, comprising the steps of:
providing a substrate;
forming a semiconductor layer on the substrate, wherein forming the semiconductor layer comprises forming a first sub-semiconductor layer and forming a second sub-semiconductor layer, wherein the second sub-semiconductor layer at least comprises a first sub-part which is arranged in the same layer as the first sub-semiconductor layer, the first sub-part is connected with the first sub-semiconductor layer at a first end part of the first sub-semiconductor layer, and the resistivity of the material of the undoped second sub-semiconductor layer is smaller than that of the material of the undoped first sub-semiconductor layer;
forming a gate insulating layer on the semiconductor layer, and forming a gate electrode on the gate insulating layer;
a doping process is carried out on the semiconductor layer to form a source electrode region and a drain electrode region, the source electrode region and the drain electrode region are located at two opposite ends of the semiconductor layer, the source electrode region is located at a second end part of the first sub-semiconductor layer, which is far away from the first end part, and the drain electrode region is located at least at the first sub-part;
forming an interlayer insulating layer on the gate electrode;
and forming a source electrode and a drain electrode on the interlayer insulating layer, wherein the source electrode is directly connected with the source electrode region, and the drain electrode is directly connected with a drain electrode region part positioned at the first sub-part.
CN202310415576.3A 2023-04-12 2023-04-12 Display panel and manufacturing method thereof Pending CN117476686A (en)

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CN202310415576.3A CN117476686A (en) 2023-04-12 2023-04-12 Display panel and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310415576.3A CN117476686A (en) 2023-04-12 2023-04-12 Display panel and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN117476686A true CN117476686A (en) 2024-01-30

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