CN111540787A - Oxide thin film transistor and preparation method thereof - Google Patents
Oxide thin film transistor and preparation method thereof Download PDFInfo
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- CN111540787A CN111540787A CN202010349103.4A CN202010349103A CN111540787A CN 111540787 A CN111540787 A CN 111540787A CN 202010349103 A CN202010349103 A CN 202010349103A CN 111540787 A CN111540787 A CN 111540787A
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000010408 film Substances 0.000 claims abstract description 309
- 238000000034 method Methods 0.000 claims abstract description 89
- 239000010410 layer Substances 0.000 claims description 552
- 239000011229 interlayer Substances 0.000 claims description 63
- 238000005530 etching Methods 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 238000004544 sputter deposition Methods 0.000 claims description 12
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- 239000004065 semiconductor Substances 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 23
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
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- 229910001195 gallium oxide Inorganic materials 0.000 description 4
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- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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Abstract
The embodiment of the application provides an oxide thin film transistor and a preparation method thereof, which relate to the technical field of semiconductors, and the oxide thin film transistor comprises: a source contact, a drain contact, a source and a drain; a first oxide film layer is arranged between the source electrode contact part and the source electrode; a second oxide film layer is arranged between the drain contact part and the drain; the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion. The method and the device can improve the consistency of the conductor degree of the thin film transistor, and reduce the contact resistance between the active layer and the source electrode and the drain electrode.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an oxide thin film transistor and a preparation method thereof.
Background
The metal oxide semiconductor TFT technology is a current hot gate technology, and because the metal oxide semiconductor has higher electron mobility and the manufacturing process is relatively simple compared to low temperature polysilicon, the metal oxide semiconductor TFT technology can be applied to an LCD (Liquid crystal display) display device and an OLED (organic light-Emitting display) display device, and has a good application development prospect.
In the current manufacturing process of metal oxide semiconductor devices, the existing conductor method is to complete the conductor process of an active layer through plasma treatment in an etching process, in the conductor process, the etching thicknesses of a source contact part and a drain contact part are not consistent, so that the uniformity of the conductor degree is poor, and the contact impedance between the active layer and the source and the drain is relatively large, so that the transistor characteristics are influenced.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an oxide thin film transistor and a method for manufacturing the same, which can solve the problems of poor uniformity of the degree of conductivity of the thin film transistor and large contact resistance between an active layer and source and drain electrodes.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides an oxide thin film transistor, including: a source contact, a drain contact, a source and a drain; a first oxide film layer is arranged between the source electrode contact part and the source electrode; a second oxide film layer is arranged between the drain contact part and the drain; the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion.
Furthermore, the first oxide film layer is arranged on the upper surface of the source contact part close to the planarization layer; the second oxide film layer is arranged on the upper surface of the drain contact part close to the planarization layer.
Further, the oxide thin film transistor is of a top gate structure, and the distance between the first oxide film layer and the active layer in the horizontal direction and the distance between the second oxide film layer and the active layer in the horizontal direction are both first preset distances; the oxide thin film transistor is of a bottom gate structure, and the distance between the first oxide film layer and the protruding part of the source electrode contact part in the horizontal direction and the distance between the second oxide film layer and the protruding part of the drain electrode contact part in the horizontal direction are both second preset distances; the horizontal direction is a direction perpendicular to the stacking direction of the film layers of the oxide thin film transistor.
Further, the oxide thin film transistor further includes: an interlayer dielectric layer; a source contact hole and a drain contact hole are formed in the interlayer dielectric layer; the first oxide film layer is arranged on the side wall of the source contact hole; the second oxide film layer is arranged on the side wall of the drain contact hole.
Furthermore, the first oxide film layer is arranged on the lower surface of the source electrode close to the buffer layer; the second oxide film layer is arranged on the lower surface, close to the buffer layer, of the drain electrode.
In a second aspect, an embodiment of the present application further provides a method for manufacturing an oxide thin film transistor, where the method includes: forming a buffer layer on a substrate; forming an active layer, a gate insulating layer, a gate electrode layer, a source contact portion and a drain contact portion on the buffer layer; forming a first oxide film layer on the source contact portion and a second oxide film layer on the drain contact portion; wherein the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion; forming a source electrode on the first oxide film layer, and forming a drain electrode on the second oxide film layer; and forming a planarization layer, a pixel defining layer and a pixel electrode on the source electrode and the drain electrode to obtain the oxide thin film transistor.
Further, the step of forming a first oxide film layer on the source contact portion and a second oxide film layer on the drain contact portion includes: forming a first initial oxide film layer by adopting a sputtering process or a coating process; if the oxide thin film transistor with the top gate structure is prepared, the first initial oxide film layer covers the buffer layer, the grid layer, the source contact part and the drain contact part at the same time; if the oxide thin film transistor with the bottom gate structure is prepared, the first initial oxide film layer covers the insulated gate layer, the active layer, the source contact part and the drain contact part at the same time; and carrying out graphical etching treatment on the first initial oxide film layer by using a first mask plate, forming a first oxide film layer on the upper surface of the source electrode contact part, and forming a second oxide film layer on the upper surface of the drain electrode contact part.
Further, the step of forming a first oxide film layer on the source contact portion and a second oxide film layer on the drain contact portion includes: forming an interlayer dielectric layer by a graphical etching process; if the oxide thin film transistor with the top gate structure is prepared, the interlayer dielectric layer covers the buffer layer, the source electrode contact part, the drain electrode contact part and the grid layer at the same time; if the oxide thin film transistor with the bottom gate structure is prepared, the interlayer dielectric layer covers the insulating gate layer, the source electrode contact part, the drain electrode contact part and the active layer at the same time; forming a source contact hole corresponding to the source contact part on the interlayer dielectric layer, and forming a drain contact hole corresponding to the drain contact part on the interlayer dielectric layer; forming a second initial oxide film layer by adopting a sputtering process or a coating process, wherein the second initial oxide film layer covers the interlayer dielectric layer, the source electrode contact part, the drain electrode contact part, the source electrode contact hole and the drain electrode contact hole simultaneously; and carrying out graphical etching treatment on the second initial oxide film layer by using a second mask plate, forming a first oxide film layer covering the side wall of the source contact hole on the source contact part, and forming a second oxide film layer covering the side wall of the drain contact hole on the drain contact part.
Further, the step of forming a source electrode on the first oxide film layer and a drain electrode on the second oxide film layer includes: forming a metal layer through a graphical etching process, wherein the metal layer covers the interlayer dielectric layer, the first oxide film layer and the second oxide film layer simultaneously; and carrying out graphical etching treatment on the metal layer by using a third mask plate, forming a source electrode on the first oxide film layer, and forming a drain electrode on the second oxide film layer.
Further, after the step of forming the second initial oxide film layer on the interlayer dielectric layer by using the sputtering process or the coating process, the method further includes: forming a metal layer on the second initial oxide film layer through a graphical etching process; carrying out graphical etching treatment on the metal layer and the second initial oxide film layer by using a second mask plate, and forming a first oxide film layer and a source electrode on the source electrode contact part, wherein the first oxide film layer covers the source electrode contact hole and part of the interlayer dielectric layer; and forming a second oxide film layer and a drain electrode on the drain electrode contact part, wherein the second oxide film layer covers the drain electrode contact hole and part of the interlayer dielectric layer at the same time.
In the oxide thin film transistor provided by the embodiment of the present application, the first oxide film layer and the second oxide film layer are respectively disposed between the source contact portion and the source electrode of the transistor and between the drain contact portion and the drain electrode, and it is not necessary to perform etching processes such as the source contact portion and the drain contact portion on the first oxide film layer and the second oxide film layer, so that it is possible to alleviate the problem of the prior art that the degree of conductivity of the source contact portion and the drain contact portion is different due to over-etching, and the carrier concentration of the first oxide film layer is higher than that of the source contact portion, and the carrier concentration of the second oxide film layer is higher than that of the drain contact portion, that is, the conductivity of the first oxide film layer and the second oxide film layer is relatively strong, and the oxide thin film layer belongs to a high conductivity film layer, and by respectively disposing the high conductivity film layers between the source contact portion and the source electrode, and between the drain contact portion and the, contact resistance between the active layer and the source and drain electrodes can be reduced, thereby improving transistor performance.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram illustrating a partial structure of an oxide thin film transistor provided in an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a partial structure of another oxide thin film transistor provided in an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a partial structure of another oxide thin film transistor provided in an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a partial structure of another oxide thin film transistor provided in an embodiment of the present application;
fig. 5 is a schematic diagram illustrating a partial structure of another oxide thin film transistor provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of an oxide thin film transistor provided in an embodiment of the present application;
fig. 7 is a flowchart illustrating a method for fabricating an oxide thin film transistor according to an embodiment of the present disclosure;
FIG. 8 shows a schematic diagram of a first film layer formation process provided by an embodiment of the present application;
FIG. 9 shows a schematic diagram of a second film layer formation process provided by an embodiment of the present application;
FIG. 10 is a flow chart illustrating a method of fabricating a film layer provided by an embodiment of the present application;
FIG. 11 is a schematic diagram illustrating a third film layer formation process provided by an embodiment of the present application;
fig. 12 is a schematic diagram illustrating a fourth film layer forming process provided by an embodiment of the present application;
FIG. 13 is a schematic diagram illustrating a fifth film layer formation process provided by an embodiment of the present application;
FIG. 14 shows a schematic diagram of a sixth film layer formation process provided by an embodiment of the present application;
fig. 15 is a schematic view showing a seventh film forming process provided in an embodiment of the present application;
fig. 16 is a schematic diagram illustrating an eighth film layer formation process provided by an embodiment of the present application;
fig. 17 is a flow chart illustrating another method for preparing a film provided in the examples of the present application;
fig. 18 is a flow chart illustrating another method for preparing a film provided in the examples of the present application;
fig. 19 is a schematic view illustrating a ninth film layer forming process provided in an embodiment of the present application;
fig. 20 is a schematic diagram illustrating a tenth film layer forming process provided in an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "length", "width", "thickness", "upper", "lower", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
The oxide thin film transistor is mainly used in a Liquid Crystal Display (LCD) and an organic light emitting semiconductor (OLED), and generally includes a substrate, a buffer layer, an active layer, a source contact, a drain contact, a gate insulating layer, a gate electrode layer, a planarization layer, a pixel defining layer, and the like, and a commonly used substrate is silicon dioxide. In order to improve the performance of the oxide thin film transistor, for example: the embodiments of the present invention provide an oxide thin film transistor and a method for fabricating the same, which are described in detail below for the sake of understanding.
The first embodiment is as follows:
an embodiment of the present application provides an oxide thin film transistor, including: a source contact, a drain contact, a source and a drain; wherein, a first oxide film layer is arranged between the source electrode contact part and the source electrode; a second oxide film layer is arranged between the drain contact part and the drain; the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion. Besides, the transistor also comprises a conventional film structure, such as a substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer and other films.
In practical applications, the oxide thin film transistor may be a transistor with a top gate structure or a transistor with a bottom gate structure. Taking a top gate structure as an example, referring to a partial structure diagram of an oxide thin film transistor shown in fig. 1, the transistor includes a substrate 101, a buffer layer 103, an active layer 104, a source contact 105, a drain contact 102, a gate insulating layer 108, a gate layer 109, an interlayer dielectric layer 111, a source 107, a drain 110, a first oxide film 106, and a second oxide film 112; and the interlayer dielectric layer 111 is provided with a source contact hole 113 and a drain contact hole 114.
The position relation of each film layer in the oxide thin film transistor is as follows: the lowest layer is a substrate base plate 101, and a buffer layer 103 is arranged on the substrate base plate 101; the active layer 104 is disposed on the buffer layer 103; the source contact 105 and the drain contact 102 are respectively disposed at both sides of the active layer 104; a gate insulating layer 108 is disposed on the active layer 104; a gate layer 109 is provided on the gate insulating layer 108; a first oxide film layer 106 is disposed on the source contact 106, and a second oxide film layer 112 is disposed on the drain contact 102; an interlayer dielectric layer 111 covering the buffer layer 103, the gate layer 109, the source contact 105 and the drain contact 102; the source electrode 107 is electrically connected with the first oxide film layer 106 through a source contact hole 113 on the interlayer dielectric layer 111; the drain 110 is electrically connected to the second oxide film 112 through a drain contact hole 114 on the interlayer dielectric layer 111. .
In this embodiment, the first oxide film layer and the second oxide film layer are respectively disposed between the source contact portion and the source electrode of the oxide thin film transistor and between the drain contact portion and the drain electrode, and since there is no need to perform etching processes on the first oxide film layer and the second oxide film layer, the problem of different degrees of conductivity of the source contact portion and the drain contact portion due to different etching thicknesses in the prior art can be alleviated, and the carrier concentration of the first oxide film layer is higher than that of the source contact portion, and the carrier concentration of the second oxide film layer is higher than that of the drain contact portion, that is, the first oxide film layer and the second oxide film layer have relatively strong conductivity and belong to high conductivity film layers, and by respectively disposing the high conductivity film layers between the source contact portion and the source electrode and between the drain contact portion and the drain electrode, contact resistance between the active layer and the source electrode and between the active layer and the drain electrode can be reduced, thereby improving transistor performance.
The positions of the first oxide film layer and the second oxide film layer in the oxide thin film transistor can be arranged in various ways, and three possible implementation ways are listed as follows:
the first method is as follows: referring to a partial structural schematic diagram of the oxide thin film transistor shown in fig. 2, the oxide thin film transistor further includes a planarization layer 115 on the basis of fig. 1, wherein the planarization layer 115 covers the source 107, the drain 110 and the interlayer dielectric layer 111 at the same time. The first oxide film layer 106 is disposed on the upper surface of the source contact 105 near the planarization layer 115; the second oxide film 112 is disposed on the upper surface of the drain 102 close to the planarization layer 115, and the distance between the first oxide film 106 and the active layer 104 in the horizontal direction and the distance between the second oxide film 112 and the active layer 104 in the horizontal direction are both the first predetermined values. The horizontal direction is a direction perpendicular to a stacking direction of each film layer of the oxide thin film transistor. As a preferred embodiment, the first preset value is: 0.3-5 μm.
Referring to a partial structure diagram of the oxide thin film transistor with the bottom gate structure shown in fig. 3, the transistor includes a substrate 201, a buffer layer 202, an active layer 208, a source contact 205, a drain contact 213, a gate insulating layer 204, a gate layer 203, an interlayer dielectric layer 211, a source 207, a drain 210, a first oxide film layer 206, a second oxide film layer 212, and a planarization layer 209; and the interlayer dielectric layer 211 is provided with a source contact hole 214 and a drain contact hole 215.
The specific inter-layer relationships are as follows: the buffer layer 202 is disposed on the base substrate 201; the gate layer 203 is disposed on the buffer layer 202; a gate insulating layer 204 is disposed on the gate layer 203 and the buffer layer 202; the active layer 208 is disposed on the gate insulating layer 204; a source contact 205 and a drain contact 213 are respectively disposed at both sides of the active layer 208; a first oxide film layer 206 is disposed on the source contact 205, and a second oxide film layer 212 is disposed on the drain contact 213; the interlayer dielectric layer 211 covers the gate insulating layer 204, the active layer 208, the source contact 205, and the drain contact 213; the source electrode 207 is electrically connected with the first oxide film layer 206 through a source contact hole 214 on the interlayer dielectric layer 211; the drain electrode 210 is electrically connected with the second oxide film layer 212 through a drain contact hole 215 on the interlayer dielectric layer 211; the planarization layer 209 covers the source electrode 207, the drain electrode 210 and the interlayer dielectric layer 211 at the same time.
The first oxide film layer 206 is formed on the upper surface of the source contact 205 near the planarization layer 209; the second oxide film layer 212 is on the upper surface of the drain contact portion 213 close to the planarization layer 209, and the distance between the first oxide film layer 206 and the protrusion of the source contact portion 205 in the horizontal direction and the distance between the second oxide film layer 212 and the protrusion of the drain contact portion 213 in the horizontal direction are both a second predetermined value. The horizontal direction is a direction perpendicular to a stacking direction of each film layer of the oxide thin film transistor. As a preferred embodiment, the second preset value is: 0.3-5 μm.
It should be noted that the first preset value and the second preset value may be the same or different.
In order to reduce the damage to the active layer channel caused by the etching process of the first oxide film layer and the second oxide film layer and to alleviate the diffusion of oxygen holes to the active layer channel along the surface, the first oxide film layer and the second oxide film layer may also be disposed at other positions in the transistor, as in the following manner two and manner three:
the second method comprises the following steps: referring to fig. 4, a schematic diagram of a partial structure of an oxide thin film transistor, which still takes a transistor with a top gate structure as an example, includes: a substrate 301, a buffer layer 302, an active layer 303, a source contact 305, a drain contact 312, a gate insulating layer 304, a gate layer 308, an interlayer dielectric layer 309, a source 307, a drain 310, a first oxide film layer 306 and a second oxide film layer 311; a source contact hole 313 and a drain contact hole 314 are formed in the interlayer dielectric layer 309, the positional relationship of the layers is the same as that in fig. 1, and is not described herein again, except that the first oxide film layer 306 is disposed on the sidewall of the source contact hole 313; the second oxide film layer 311 is disposed on the sidewall of the drain contact hole 314. The formation positions of the first oxide film layer and the second oxide film layer in the transistor with the bottom gate structure may also be the same as the positions shown in fig. 4, and are not described herein again.
The third method comprises the following steps: referring to the partial structure diagram of the oxide thin film transistor shown in fig. 5, unlike the transistor in fig. 4, the first oxide film layer 306 is located at the source near the lower surface of the buffer layer 302; the second oxide film 311 is located on the lower surface of the drain electrode close to the buffer layer 302, and the forming positions of the first oxide film and the second oxide film in the transistor with the bottom gate structure may also be the same as those shown in fig. 5, which is not described herein again.
It should be noted that the first oxide film layer and the second oxide film layer may also be disposed at other positions in the transistor, for example, a portion of the film layers may be located on the lower surfaces of the source electrode and the drain electrode while covering the contact hole. The size of the film layers on the lower surfaces of the source electrode and the drain electrode depends on the pattern design of the mask plate. In the second mode or the third mode, the film layer is arranged, so that the active layer channel can be protected from being damaged in the etching process of the first oxide film layer and the second oxide film layer, and the diffusion of oxygen holes to the channel along the surface is relieved, thereby ensuring the performance of the transistor.
As a preferable embodiment, the carrier concentration of each of the first oxide film layer and the second oxide film layer is more than 1018cm "3; the thicknesses of the first oxide film layer and the second oxide film layer are both: 2nm-30 nm. The semiconductor material of the first oxide film layer and the second oxide film layer each include one of: IGZO indium gallium zinc oxide, ITZO indium tin zinc oxide, ITGO indium tin gallium oxide, ITZGO indium tin zinc gallium oxide, IZO indium zinc oxide, and ZnO zinc oxide. The oxide thin film transistor includes, but is not limited to, an IGZO indium gallium zinc oxide thin film transistor.
In order to meet the production requirement of the curved display device, a flexible substrate may be further disposed between the substrate and the buffer layer of the transistor, such as a schematic diagram of an oxide thin film transistor with a top gate structure shown in fig. 6, and the transistor further includes, on the basis of fig. 4, a flexible substrate 315, a planarization layer 316, a pixel defining layer 318, and a pixel electrode 317. The planarization layer 316 covers the source 307, the drain 310 and the interlayer dielectric layer 309 at the same time, and the pixel defining layer 318 is disposed on the planarization layer 316; a pixel electrode 317 electrically connected to the drain electrode 310 is disposed on the pixel defining layer 318 and the planarization layer 316.
It should be noted that the positions of the source contact portion and the drain contact portion, and the positions of the source and the drain may be interchanged, or the pixel electrode may be disposed at a corresponding position above the source in fig. 6, and the pixel electrode may be electrically connected to one of the source and the drain.
In the oxide thin film transistor provided by the embodiment of the application, the first oxide film layer and the second oxide film layer with higher carrier concentration are added on the source contact part and the drain contact part, so that the first oxide film layer and the second oxide film layer are respectively electrically connected with the source electrode and the drain electrode, the contact resistance between the active layer and the source electrode and the drain electrode can be reduced, a better similar ohmic contact effect is formed, and the transistor performance is improved. In addition, the first oxide film layer and the second oxide film layer with higher carrier concentration are added between the source contact part and the source and between the drain contact part and the drain, so that the problem of different conductor degrees of the source contact part and the drain contact part due to over etching in the prior art can be solved.
In addition, in the oxide thin film transistor provided by the embodiment of the application, since the increased carrier concentrations of the first oxide film layer and the second oxide film layer are higher than the carrier concentrations of the source contact portion and the drain contact portion, the source contact portion and the drain contact portion can be regarded as light conduction regions, the first oxide film layer and the second oxide film layer can be regarded as heavy conduction regions, and an electric field difference exists between the light conduction region and the heavy conduction region, so that an LDD-like structure can be formed, leakage current is reduced, and a hot electron degradation effect is prevented.
Example two:
based on the foregoing embodiments of the present application, there is also provided a method for manufacturing an oxide thin film transistor, referring to a flowchart of a method for manufacturing an oxide thin film transistor shown in fig. 7, where the method includes the following steps:
step S101 forms a buffer layer on a substrate.
Step S102, an active region, a gate insulating layer, a gate layer, a source contact portion, and a drain contact portion are formed on the buffer layer.
Step S103, forming a first oxide film layer on the source contact part and a second oxide film layer on the drain contact part; wherein the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion.
And step S104, forming a source electrode on the first oxide film layer, and forming a drain electrode on the second oxide film layer.
Step S105, a planarization layer, a pixel defining layer, and a pixel electrode are formed on the source and drain electrodes, resulting in an oxide thin film transistor.
The step S102 may include two process steps, one of which is based on a top gate structure, and the specific implementation process is as follows: forming an active layer on the buffer layer; sequentially forming a gate insulating layer and a gate electrode layer on the active layer; a source contact and a drain contact are formed on both sides of the active layer. The other is based on a bottom gate structure, and the specific implementation process is as follows: forming a gate electrode layer and a gate insulating layer covering the gate electrode layer on the buffer layer; forming an active layer on the gate insulating layer; a source contact and a drain contact are formed on both sides of the active layer.
In the above step S105: the planarization layer and the pixel defining layer may be formed by a patterned etching process; the planarization layer covers the source electrode, the drain electrode and the interlayer dielectric layer at the same time; and etching a pixel electrode electrically connected with the source electrode or the drain electrode on the pixel defining layer and the planarization layer. As a preferred embodiment, before the step of forming the buffer layer on the base substrate, the method may further include the steps of: a flexible substrate is formed on the base substrate.
The steps S101, S102 and S105 are all conventional thin film preparation process steps, and are not described herein again, and the process of the steps S103 and S104 will be described in detail below.
In step S103, there are various ways to form the first oxide film layer and the second oxide film layer, and different process steps may be adopted to implement the formation according to different positions of the film layers. To clearly illustrate the formation of the first oxide film layer and the second oxide film layer, reference may be made to two film layer formation diagrams shown in fig. 8-9 and the film layer preparation steps shown in fig. 10:
step S201, forming a first initial oxide film layer by adopting a sputtering process or a coating process; if the oxide thin film transistor with the top gate structure is prepared, the first initial oxide film layer covers the buffer layer, the grid layer, the source contact part and the drain contact part at the same time; if the oxide thin film transistor of the bottom gate structure is prepared, the first initial oxide film layer covers the insulated gate layer, the active layer, the source contact portion and the drain contact portion at the same time.
In the embodiment of the present application, taking the preparation of an oxide thin film transistor with a top gate structure as an example, as shown in fig. 8, a specific preparation process is as follows: forming a buffer layer 402 on a substrate base plate 401, and forming an active layer 404 on the buffer layer 402; a gate insulating layer 406 and a gate layer 407 are sequentially formed on the active layer 404; forming a source contact 405 and a drain contact 403 on both sides of the active layer 404; a first preliminary oxide film layer 408 is formed using a sputtering process or a coating process, and the first preliminary oxide film layer 408 covers the buffer layer 402, the gate layer 407, the source contact 405, and the drain contact 403 at the same time.
The first initial oxide film layer is made of the same oxide material as the active layer, but the proportion of O2 formed by sputtering is lower than that of O2 of the active layer, and the proportion of O2 is within the range of 0-15% so as to guarantee the carrier concentration of the first oxide film layer and the second oxide film layer. Other high mobility oxide materials may also be used for the first initial oxide film layer, such as: the material such as IGZO indium gallium zinc oxide, ITZO indium tin zinc oxide, ITGO indium tin gallium oxide, ITZGO indium tin zinc gallium oxide, IZO indium zinc oxide, ZnO zinc oxide and the like adopts a corresponding magnetron sputtering process, so that the carrier concentration of the first oxide film layer and the second oxide film layer is ensured.
Step S202, a first mask is used to perform a patterned etching process on the first initial oxide film layer, so as to form a first oxide film layer on the upper surface of the source contact portion and a second oxide film layer on the upper surface of the drain contact portion.
As shown in fig. 9, after the first preliminary oxide film layer 408 is patterned, a first oxide film layer 409 is formed on the upper surface of the source contact 405, and a second oxide film layer 410 is formed on the upper surface of the drain contact 403.
A first oxide film layer and a second oxide film layer are formed through a graphical etching process, the sizes of the first oxide film layer and the second oxide film layer are respectively larger than the contact sizes of the source electrode and the drain electrode, and a certain horizontal distance (5 mu m is larger than or equal to d is larger than or equal to 0.3 mu m) is ensured between the edges of the first oxide film layer and the second oxide film layer and an active layer channel, as shown in figures 1 and 2. For the transistor with the bottom gate structure, the edges of the first oxide film layer and the second oxide film layer and the source contact bulge and the drain contact bulge ensure a certain distance (d is more than or equal to 5 mu m and more than or equal to 0.3 mu m), as shown in figure 3, so that oxygen vacancy is prevented from diffusing to the channel of the active region along the surface of the contact. The coverage area of the first oxide film layer and the second oxide film layer on the upper surfaces of the source contact part and the drain contact part is determined by the pattern arrangement of the first mask plate. The positions of the first oxide film layer and the second oxide film layer formed through the above-described process steps are as shown in fig. 1 to 3 in the above embodiment.
It is considered that if oxygen holes in the first oxide film layer and the second oxide film layer diffuse into the active layer channel, the carrier concentration of the channel may increase to become a conductor, and the channel size may change, thereby affecting the TFT characteristics. The embodiments of the present application further provide another film layer forming process step, see the four film layer forming schematic diagrams shown in fig. 11-16 and the process step shown in fig. 17:
step S301, forming an interlayer dielectric layer through a graphical etching process; if the oxide thin film transistor with the top gate structure is prepared, the interlayer dielectric layer covers the buffer layer, the source electrode contact part, the drain electrode contact part and the grid layer at the same time; if the oxide thin film transistor with the bottom gate structure is prepared, the interlayer dielectric layer covers the insulating gate layer, the source contact part, the drain contact part and the active layer at the same time.
Also taking the preparation of the above-described oxide thin film transistor of the top gate structure as an example, as shown in fig. 11, after forming a buffer layer 502 on a base substrate 501, and forming an active layer 504, a gate insulating layer 506, a gate layer 507, a source contact 505, and a drain contact 503 on the buffer layer 502; an interlayer dielectric layer 508 is formed through a patterned etching process, and the interlayer dielectric layer 508 covers the buffer layer 502, the source contact 505, the drain contact 503, and the gate layer 507 at the same time.
In step S302, a source contact hole corresponding to the source contact portion is formed on the interlayer dielectric layer, and a drain contact hole corresponding to the drain contact portion is formed on the interlayer dielectric layer.
As shown in fig. 12, a source contact hole 510 corresponding to the source contact portion 505 is formed on the interlayer dielectric layer 508, and a drain contact hole 509 corresponding to the drain contact portion 503 is formed on the interlayer dielectric layer 508.
Step S303, a second initial oxide film layer is formed by a sputtering process or a coating process, and the second initial oxide film layer covers the interlayer dielectric layer, the source contact portion, the drain contact portion, the source contact hole, and the drain contact hole at the same time.
As shown in fig. 13, a second preliminary oxide film layer 511 is formed using a sputtering process or a coating process while covering the interlayer dielectric layer 508, the source contact portion 505, the drain contact portion 503, the source contact hole 510, and the drain contact hole 509.
Step S304, a second mask is used to perform a patterned etching process on the second initial oxide film layer, a first oxide film layer covering the sidewall of the source contact hole is formed on the source contact portion, and a second oxide film layer covering the sidewall of the drain contact hole is formed on the drain contact portion.
As shown in fig. 14, after the second preliminary oxide film layer 511 is subjected to a patterning etching process, a first oxide film layer 512 covering the sidewalls of the source contact hole 510 is formed on the source contact portion 505, and a second oxide film layer 513 covering the sidewalls of the drain contact hole 509 is formed on the drain contact portion 503.
After the first oxide film layer 512 and the second oxide film layer 513 are formed, the following steps of preparing a source electrode and a drain electrode may be further included:
step S305, a metal layer is formed through a graphical etching process, and the metal layer covers the interlayer dielectric layer, the first oxide film layer and the second oxide film layer at the same time.
As shown in fig. 15, the metal layer 514 formed by the patterned etching process covers the interlayer dielectric layer 508, the first oxide film layer 512 and the second oxide film layer 513 at the same time.
Step S306, a third mask is used to perform a patterned etching process on the metal layer, so as to form a source on the first oxide film layer and a drain on the second oxide film layer.
As shown in fig. 16, after the metal layer 514 is patterned and etched, a source electrode 515 is formed on the first oxide film layer 512, and a drain electrode 516 is formed on the second oxide film layer 513.
Through the above process steps, the positions of the first oxide film layer and the second oxide film layer are formed as shown in fig. 4 in the previous embodiment. In the above process steps, three mask plates are used in the process of forming the first oxide film layer, the second oxide film layer, the source electrode and the drain electrode, and three times of photolithography are performed, which is relatively complicated, and embodiments of the present application further provide a film layer forming process step, see the flowchart shown in fig. 18 and the film layer forming schematic diagrams shown in fig. 11 to 13 and fig. 19 to 20:
step S401, forming an interlayer dielectric layer through a graphical etching process; if the oxide thin film transistor with the top gate structure is prepared, the interlayer dielectric layer covers the buffer layer, the source electrode contact part, the drain electrode contact part and the grid layer at the same time; if the oxide thin film transistor with the bottom gate structure is prepared, the interlayer dielectric layer covers the insulating gate layer, the source contact part, the drain contact part and the active layer at the same time.
In step S402, a source contact hole corresponding to the source contact portion is formed on the interlayer dielectric layer, and a drain contact hole corresponding to the drain contact portion is formed on the interlayer dielectric layer.
Step S403, forming a second initial oxide film layer by adopting a sputtering process or a coating process, wherein the second initial oxide film layer covers the interlayer dielectric layer, the source contact part, the drain contact part, the source contact hole and the drain contact hole simultaneously;
taking the preparation of the oxide thin film transistor with the top gate structure as an example, the steps S401 to S403 are the same as the steps S301 to S303 in the previous embodiment, and are not repeated herein. The implementation mode further comprises the following steps:
in step S404, a metal layer is formed on the second initial oxide film layer by a patterning etching process, as shown in fig. 19, and a metal layer 514 is formed on the second initial oxide film layer 511.
Step S405, simultaneously carrying out graphical etching treatment on the metal layer and the second initial oxide film layer by using a second mask plate, forming a first oxide film layer and a source electrode on the source electrode contact part, wherein the first oxide film layer covers the source electrode contact hole and part of the interlayer dielectric layer; and forming a second oxide film layer and a drain electrode on the drain electrode contact part, wherein the second oxide film layer covers the drain electrode contact hole and part of the interlayer dielectric layer at the same time.
As shown in fig. 20, a metal layer 514 and the second initial oxide film layer 511 are simultaneously subjected to a patterned etching process to form a first oxide film layer 512 and a source electrode 515 on the source contact 505, wherein the first oxide film layer 512 simultaneously covers the source contact hole 510 and a part of the interlayer dielectric layer 508; a second oxide film layer 513 and a drain electrode 516 are formed on the drain contact part 503, and the second oxide film layer 513 covers both the drain contact hole 509 and a portion of the interlayer dielectric layer 508.
In the above embodiment, after the second initial oxide film layer is formed, the metal layer is further deposited, in this case, the metal layer and the second initial oxide film layer may be subjected to photolithography by using the same mask plate, so as to form the first oxide film layer covering the source contact hole, the second oxide film layer covering the drain contact hole, and the source and the drain. The method can reduce one mask plate, and reduce one photoetching process, thereby improving the preparation efficiency of the oxide thin film transistor. Through the above-described process steps, the first oxide film layer and the second oxide film layer are formed at positions as shown in fig. 5 to 6 in the above embodiment, and the first oxide film layer and the second oxide film layer are formed on the lower surfaces of the source electrode and the drain electrode.
In the method for manufacturing an oxide thin film transistor provided by the embodiment of the present application, on the basis of conventional film layer manufacturing, a manufacturing step of a first oxide film layer and a second oxide film layer is added, that is, a certain patterned photolithography process is performed to form the first oxide film layer and the second oxide film layer between a source contact portion and a source and between a drain contact portion and a drain of the transistor, and since etching processes such as the source contact portion and the drain contact portion are not required to be performed on the first oxide film layer and the second oxide film layer, the problem of inconsistent conduction degree of the source contact portion and the drain contact portion due to over etching in the prior art can be alleviated, and the carrier concentration of the first oxide film layer is higher than that of the source contact portion, and the carrier concentration of the second oxide film layer is higher than that of the drain contact portion, the first oxide film layer and the second oxide film layer have relatively strong conductive capability and belong to high-conductivity film layers, and the high-conductivity film layers are respectively arranged between the source contact part and the source electrode and between the drain contact part and the drain electrode, so that the contact resistance between the active layer and the source electrode and the contact resistance between the active layer and the drain electrode can be reduced, and the transistor performance is improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An oxide thin film transistor, comprising: a source contact, a drain contact, a source and a drain; a first oxide film layer is arranged between the source electrode contact part and the source electrode; a second oxide film layer is arranged between the drain contact part and the drain; the first oxide film layer has a carrier concentration higher than that of the source contact portion, and the second oxide film layer has a carrier concentration higher than that of the drain contact portion.
2. The oxide thin film transistor of claim 1, wherein the first oxide film layer is disposed on the source contact near an upper surface of a planarization layer; the second oxide film layer is arranged on the upper surface of the drain contact part close to the planarization layer.
3. The oxide thin film transistor according to claim 2, wherein the oxide thin film transistor has a top gate structure, and a distance between the first oxide film layer and the active layer in a horizontal direction and a distance between the second oxide film layer and the active layer in the horizontal direction are both a first predetermined distance;
the oxide thin film transistor is of a bottom gate structure, and the distance between the first oxide film layer and the protruding part of the source electrode contact part in the horizontal direction and the distance between the second oxide film layer and the protruding part of the drain electrode contact part in the horizontal direction are both second preset distances;
the horizontal direction is a direction perpendicular to the stacking direction of the film layers of the oxide thin film transistor.
4. The oxide thin film transistor according to claim 1, further comprising: an interlayer dielectric layer; a source contact hole and a drain contact hole are formed in the interlayer dielectric layer;
the first oxide film layer is arranged on the side wall of the source contact hole;
the second oxide film layer is arranged on the side wall of the drain contact hole.
5. The oxide thin film transistor of claim 1, wherein the first oxide film layer is disposed on a lower surface of the source electrode adjacent to the buffer layer; the second oxide film layer is arranged on the lower surface, close to the buffer layer, of the drain electrode.
6. A method for preparing an oxide thin film transistor, the method comprising:
forming a buffer layer on a substrate;
forming an active layer, a gate insulating layer, a gate electrode layer, a source contact portion and a drain contact portion on the buffer layer;
forming a first oxide film layer on the source contact portion and a second oxide film layer on the drain contact portion; wherein a carrier concentration of the first oxide film layer is higher than a carrier concentration of the source contact portion, and a carrier concentration of the second oxide film layer is higher than a carrier concentration of the drain contact portion;
forming a source electrode on the first oxide film layer, and forming a drain electrode on the second oxide film layer;
and forming a planarization layer, a pixel limiting layer and a pixel electrode on the source electrode and the drain electrode to obtain the oxide thin film transistor.
7. The method of claim 6, wherein forming a first oxide film layer on the source contact and a second oxide film layer on the drain contact comprises:
forming a first initial oxide film layer by adopting a sputtering process or a coating process; if an oxide thin film transistor of a top gate structure is prepared, the first initial oxide film layer covers the buffer layer, the gate layer, the source contact part and the drain contact part at the same time; if an oxide thin film transistor of a bottom gate structure is prepared, the first initial oxide film layer covers the insulated gate layer, the active layer, the source contact part and the drain contact part at the same time;
and carrying out graphical etching treatment on the first initial oxide film layer by using a first mask plate, forming a first oxide film layer on the upper surface of the source electrode contact part, and forming a second oxide film layer on the upper surface of the drain electrode contact part.
8. The method of claim 6, wherein forming a first oxide film layer on the source contact and a second oxide film layer on the drain contact comprises:
forming an interlayer dielectric layer by a graphical etching process; if the oxide thin film transistor with the top gate structure is prepared, the interlayer dielectric layer covers the buffer layer, the source electrode contact part, the drain electrode contact part and the grid layer at the same time; if the oxide thin film transistor with the bottom gate structure is prepared, the interlayer dielectric layer covers the insulating gate layer, the source electrode contact part, the drain electrode contact part and the active layer at the same time;
forming a source contact hole corresponding to the source contact part on the interlayer dielectric layer, and forming a drain contact hole corresponding to the drain contact part on the interlayer dielectric layer;
forming a second initial oxide film layer by adopting a sputtering process or a coating process, wherein the second initial oxide film layer covers the interlayer dielectric layer, the source contact part, the drain contact part, the source contact hole and the drain contact hole simultaneously;
and carrying out graphical etching treatment on the second initial oxide film layer by using a second mask plate, forming a first oxide film layer covering the side wall of the source contact hole on the source contact part, and forming a second oxide film layer covering the side wall of the drain contact hole on the drain contact part.
9. The method of claim 8, wherein forming a source electrode on the first oxide film layer and a drain electrode on the second oxide film layer comprises:
forming a metal layer through a graphical etching process, wherein the metal layer covers the interlayer dielectric layer, the first oxide film layer and the second oxide film layer simultaneously;
and carrying out graphical etching treatment on the metal layer by using a third mask plate, forming a source electrode on the first oxide film layer, and forming a drain electrode on the second oxide film layer.
10. The method of claim 8, further comprising, after the step of forming a second initial oxide film layer on the interlevel dielectric layer using a sputtering process or a coating process:
forming a metal layer on the second initial oxide film layer through a graphical etching process;
carrying out graphical etching treatment on the metal layer and the second initial oxide film layer by using a second mask plate, and forming a first oxide film layer and a source electrode on the source electrode contact part, wherein the first oxide film layer covers the source electrode contact hole and part of the interlayer dielectric layer; and forming a second oxide film layer and a drain electrode on the drain electrode contact part, wherein the second oxide film layer covers the drain electrode contact hole and part of the interlayer dielectric layer at the same time.
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