TW283218B - - Google Patents

Info

Publication number
TW283218B
TW283218B TW082111125A TW82111125A TW283218B TW 283218 B TW283218 B TW 283218B TW 082111125 A TW082111125 A TW 082111125A TW 82111125 A TW82111125 A TW 82111125A TW 283218 B TW283218 B TW 283218B
Authority
TW
Taiwan
Application number
TW082111125A
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW283218B publication Critical patent/TW283218B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
TW082111125A 1993-01-29 1993-12-29 TW283218B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1104193A 1993-01-29 1993-01-29

Publications (1)

Publication Number Publication Date
TW283218B true TW283218B (zh) 1996-08-11

Family

ID=21748611

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082111125A TW283218B (zh) 1993-01-29 1993-12-29

Country Status (7)

Country Link
US (1) US5611058A (zh)
EP (1) EP0609041A1 (zh)
JP (1) JP3189139B2 (zh)
KR (1) KR970001919B1 (zh)
CN (1) CN1102265C (zh)
CA (1) CA2109043A1 (zh)
TW (1) TW283218B (zh)

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EP0690382B1 (en) * 1994-07-01 2003-01-02 Sun Microsystems, Inc. Computer system with a multiplexed address bus and pipelined write operations
US5793996A (en) * 1995-05-03 1998-08-11 Apple Computer, Inc. Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US6226695B1 (en) 1995-09-29 2001-05-01 International Business Machines Corporation Information handling system including non-disruptive command and data movement between storage and one or more auxiliary processors
US5748914A (en) * 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5778438A (en) * 1995-12-06 1998-07-07 Intel Corporation Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5867675A (en) * 1996-08-06 1999-02-02 Compaq Computer Corp Apparatus and method for combining data streams with programmable wait states
US5905876A (en) * 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US6055373A (en) * 1997-04-28 2000-04-25 Ncr Corporation Computer system including a digital signal processor and conventional central processing unit having equal and uniform access to computer system resources
US6266379B1 (en) * 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6178477B1 (en) * 1997-10-09 2001-01-23 Vlsi Technology, Inc. Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6032178A (en) * 1998-01-12 2000-02-29 Siemens Aktiengesellschaft Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations
US6061764A (en) * 1998-01-26 2000-05-09 Intel Corporation Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions
US6347344B1 (en) 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
US6434649B1 (en) 1998-10-14 2002-08-13 Hitachi, Ltd. Data streamer
US6202112B1 (en) * 1998-12-03 2001-03-13 Intel Corporation Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge
US7555603B1 (en) 1998-12-16 2009-06-30 Intel Corporation Transaction manager and cache for processing agent
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6810455B2 (en) 2001-09-28 2004-10-26 Cradle Technologies, Inc. Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines
US6807593B1 (en) * 2001-11-01 2004-10-19 Lsi Logic Corporation Enhanced bus architecture for posted read operation between masters and slaves
US6839816B2 (en) * 2002-02-26 2005-01-04 International Business Machines Corporation Shared cache line update mechanism
US6907502B2 (en) * 2002-10-03 2005-06-14 International Business Machines Corporation Method for moving snoop pushes to the front of a request queue
TW594490B (en) * 2003-03-20 2004-06-21 Via Tech Inc Bus for control chipset and the arbitration method
US7099971B1 (en) * 2003-06-26 2006-08-29 Emc Corporation Arbitration system
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7502895B2 (en) * 2005-09-13 2009-03-10 Hewlett-Packard Development Company, L.P. Techniques for reducing castouts in a snoop filter
US8375171B2 (en) * 2010-04-08 2013-02-12 Unisys Corporation System and method for providing L2 cache conflict avoidance
WO2013130090A1 (en) * 2012-03-02 2013-09-06 Arm Limited Data processing apparatus having first and second protocol domains, and method for the data processing apparatus
US10282109B1 (en) 2016-09-15 2019-05-07 Altera Corporation Memory interface circuitry with distributed data reordering capabilities

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JPS5526736B2 (zh) * 1973-12-14 1980-07-15
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
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US4908749A (en) * 1985-11-15 1990-03-13 Data General Corporation System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal
JP2554050B2 (ja) * 1986-02-26 1996-11-13 株式会社日立製作所 デ−タ処理方法
JP2886856B2 (ja) * 1986-04-09 1999-04-26 株式会社日立製作所 二重化バス接続方式
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US5317715A (en) * 1987-12-15 1994-05-31 Advanced Micro Devices, Inc. Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics
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US5133074A (en) * 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
US5278974A (en) * 1989-12-04 1994-01-11 Digital Equipment Corporation Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths
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US5369748A (en) * 1991-08-23 1994-11-29 Nexgen Microsystems Bus arbitration in a dual-bus architecture where one bus has relatively high latency
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US5309567A (en) * 1992-01-24 1994-05-03 C-Cube Microsystems Structure and method for an asynchronous communication protocol between master and slave processors

Also Published As

Publication number Publication date
EP0609041A1 (en) 1994-08-03
CN1094526A (zh) 1994-11-02
JPH076124A (ja) 1995-01-10
US5611058A (en) 1997-03-11
CN1102265C (zh) 2003-02-26
KR970001919B1 (ko) 1997-02-19
JP3189139B2 (ja) 2001-07-16
CA2109043A1 (en) 1994-07-30
KR940018760A (ko) 1994-08-18

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