TW278221B - Fabrication method of self-aligned CMOS transistor - Google Patents

Abstract

A fabrication method of self-aligned CMOS transistor, that is applicable to fabricate PMOS transistor and NMOS transistor on one first-type substrate, comprises the steps of: forming one second-type well area on determined position of the above first-type substrate; forming pad oxide and silicon nitride layer in sequence on the above first-type substrate and the second-type well area; etching the above silicon nitride layer by photolithography to dope dopant to the above first-type substrate and the second-type well area so as to form drain and source region of the above PMOS and NMOS transistor, and contact region of the above first-type substrate and the second-type well area, and coating the above silicon nitride layer on channel area of the above PMOS and NMOS transistor, simultaneously with the silicon nitride layer coated on the above channel area as mask doping the above drain and source region to form gate oxide; performing oxidization to form field oxide layer; forming gate oxide on channel area of the above PMOS and NMOS transistor; and forming metal gate layer on the above gate oxide, simultaneouslyimplementing metal contact to the above drain, source and contact region.