KR970010018B1 - Semiconductor device and its manufacture - Google Patents

Abstract

Semiconductor device is manufactured by (a) Gate insulating film(105) is formed on a substrate(101), and a diffusion preventive material layer(106A) and a metal layer(107A) are formed in order on a gate insulating film(105). (b) Etching preventive material layer(108A) is formed on the upper part of metal layer(107A), and the mask pattern(110) of gate electrode is formed on the upper part of etching preventive material layer, (c) Etching preventive cap layer(108) is formed by etching selectively etching preventive material layer(108A) with mask pattern(110), and then mask pattern is removed, (d) Metal layer and diffusion preventive material layer are etched in order, selectively by using etching preventive pattern cap layer as etching preventive mask.

Description

Semiconductor device and manufacturing method thereof

1 is a cross-sectional view showing a semiconductor device according to the present invention.

2A through 2F are cross-sectional views sequentially illustrating intermediate structures according to a method of manufacturing a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its fabrication method, and more particularly to a MOS transistor structure and a fabrication method thereof.

In general, a polysilicon layer doped with a high concentration of impurities has been used as the MOS transistor gate electrode. However, the gate electrode formed of polysilicon becomes smaller in size as the device becomes more integrated, and thus has a very high resistance. Since the higher the resistance, the lower the signal transfer rate, the result is that polysilicon gates become undesirable in insisted semiconductor devices. Furthermore, in the PMOS transistors, surface channel PMOS transistors should be formed to suppress short channel phenomena, improve turn-off characteristics, and operate at low threshold voltages. In order to form the surface channel PMOS transistor, a gate electrode must be formed of p ⁺ polysilicon. However, since boron used as an impurity in p ⁺ polysilicon is easily diffused to the silicon substrate through the gate oxide film, the threshold voltage of the transistor is changed, thereby changing the characteristics of the device.

On the other hand, when looking at the electrode made of metal, since the metal layer generally has a low resistance value, it has the advantage that the signal transmission rate is increased, but because of the large diffusion coefficient to silicon, there is a fear of causing device defects and malfunction of the device There is.

Therefore, as a gate structure for overcoming such problems and applying to a highly integrated device, a gate electrode structure made of a diffusion barrier material layer / metal layer has been conventionally proposed.

However, it is necessary to pattern them in order to form a gate electrode made of a diffusion barrier material layer / metal layer. In general, a photoresist mask pattern is used when patterning a gate electrode. When a metal layer is to be etched using the photoresist mask pattern, the etch stop ratio of the photoresist mask pattern is very low, thereby damaging the metal layer formed under the gate electrode. There was a problem.

In addition, since the formation of the photoresist mask pattern is performed in the air, the metal layer is exposed to the air, and thus an oxide film is formed on the metal layer, thereby degrading the characteristics of the device.

Accordingly, it is an object of the present invention to provide a semiconductor device capable of improving the above-mentioned problem.

Another object of the present invention is to provide a method of manufacturing the semiconductor device.

In order to achieve the above object, a semiconductor device according to one type of the present invention is a semiconductor substrate: an electrode made of a diffusion preventing material layer and a metal layer sequentially formed on the semiconductor substrate via a predetermined insulating film: and on the electrode It is comprised including the etching prevention pattern cap layer formed in the.

The semiconductor device may further include source and drain regions that are spaced apart from each other to form a transistor channel in the semiconductor substrate, wherein the insulating film is a gate insulating film of a transistor, and the electrode is a transistor. It becomes a gate electrode of. The etch stop spatter and the etch stop pattern cap layer are formed of silicon nitride (Si ₃ N ₄ ) on the sidewall of the gate electrode, the diffusion barrier material layer is formed of titanium nitride (TiN), and the metal layer is copper (Cu).

In order to achieve the above another object, a method of manufacturing a semiconductor device according to one type of the present invention, forming a gate insulating film on a semiconductor substrate: a step of sequentially forming a diffusion preventing material layer and a metal layer on the gate insulating film : Forming a layer of an etch stop material on top of the metal layer: forming a mask pattern defining a gate electrode on top of the layer of etch stop material: selectively etching the layer of etch stop material using the mask pattern A process of forming an etch stop pattern cap layer may be performed by: removing the mask pattern; and using the etch stop pattern cap layer as an etch stop mask while sequentially and selectively etching the metal layer and the diffusion preventing material layer. Include.

In an embodiment of the method of manufacturing the semiconductor device, the step of forming the etch stop material layer is a step of applying silicon nitride (Si ₃ N ₄ ), the step of forming the diffusion barrier material layer is titanium nitride. The process of apply | coating and the process of forming the said metal layer is a process of apply | coating copper. And implanting ions to form a source and a drain of the LDD structure while using the patterned diffusion barrier material layer, the metal layer, and the etch stop pattern cap layer as an ion implantation prevention mask. Forming a spacer material layer: forming a spacer on sidewalls of the patterned diffusion barrier material layer, metal layer, and etch stop pattern cap layer by etching back the spacer material layer: and patterned diffusion barrier material layer, metal layer The method further includes a secondary ion implantation process of implanting ions to form a source and a drain while using the etch stop pattern cap layer and the spacer as an ion implantation prevention mask. Here, the process of forming the spacer material layer is a process of applying silicon nitride (Si ₃ N ₄ ).

In order to achieve the above another object, according to the manufacturing method of the semiconductor device according to another type of the present invention, the mask pattern is not removed after forming the etch stop pattern cap layer, the subsequent etching process of the metal layer and the diffusion preventing material layer In addition, together with the etch stop pattern cap layer, it acts as an etch stop mask. That is, the mask pattern is removed after the etching process of the metal layer and the diffusion barrier material layer.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a semiconductor device according to the present invention.

Referring to FIG. 1, a field oxide film 102 is selectively formed in the semiconductor substrate 101 to define an active region and an isolation region. Source and drain regions 103 and 104 are formed in the active region with a predetermined interval therebetween, and a transistor channel is formed therebetween. A gate electrode including a diffusion barrier material layer 106 and a metal layer 107 is formed on the transistor channel through the gate insulating layer 105, and an etch stop pattern cap layer 108 is formed on the gate electrode. Is formed. The metal layer 107 may be preferably formed of copper. Since copper (Gu) has a higher melting point than aluminum (A1) generally used as a metal electrode material, the temperature conditions of subsequent processes may be further relaxed. In addition, copper has a much lower resistance value than aluminum, and thus has an advantage of increasing signal transmission speed. On the other hand, since copper has a higher diffusion coefficient to silicon than aluminum, a diffusion preventing material layer capable of preventing diffusion of copper between the substrate made of silicon is required. The diffusion barrier material layer 106 for copper may use a material such as titanium nitride (TiN).

The etch stop pattern cap layer 108 formed on the gate electrode has the same pattern as the gate electrode, and serves as an etch stop mask pattern during an etching process for patterning the gate electrode. That is, the etch stop pattern cap layer is made of a material having a high etch differentiation with respect to the material constituting the gate electrode. In the gate electrode made of copper, a silicon nitride (Si ₃ N ₄ ) layer may be used as the etch stop pattern cap layer 108.

Spacers 109 are formed on sidewalls of the gate electrode, and the source and drain regions 103 and 104 have an LDD structure.

Although the structure of the transistor has been described above, the structure of the gate electrode is not only applied to the transistor, but an electrode of another element in the semiconductor device may have the same structure as the gate shown in FIG.

Next, a method of manufacturing a semiconductor device according to the present invention will be described in more detail with reference to FIGS. 2A through 2F.

First, referring to FIG. 2A, the field oxide film 102 is selectively formed on the semiconductor substrate 101 such as silicon through the LOCOS method to define the active region and the device isolation region.

Subsequently, the semiconductor substrate 101 is heat treated to form an oxide film as the gate insulating film 105. Then, titanium nitride (TiN) is applied as the diffusion barrier material layer 106A, and copper (Gu) is applied as the metal layer 107A, by sputtering or CVD in a vacuum. On top of the copper layer, silicon nitride (Si ₃ N ₄ ) is applied as the etch stop layer 108A. Here, the silicon nitride coating process is also carried out in a vacuum reactor. Thus, the copper layer is not exposed to the atmosphere during the process, thereby preventing the copper layer from being oxidized by the atmosphere.

Subsequently, as shown in FIG. 2B, a photoresist mask pattern 110 defining a gate electrode is formed on the etch stop material layer 108A made of silicon nitride, and is formed thereunder. The etch stop layer 108A is selectively etched to form an etch stop pattern cap layer 108. When formation of the etch stop pattern cap layer 108 is completed, the photoresist mask pattern 110 may be stripped.

Then, as shown in FIG. 2C, while using the etch stop pattern cap layer 108 as an etch stop mask, the copper layer and the titanium nitride layer formed thereunder using a reactive ion etching (RIE) method or the like. To be sequential and selective. Then, to form the source and drain regions of the LDD structure, ions are implanted using the patterned diffusion barrier material layer 106, the metal layer 107, and the etch stop pattern cap layer 108 as an ion implantation prevention mask. . Subsequently, as shown in FIG. 2d, a layer of spacer material 109A capable of protecting the gate electrode, such as silicon nitride, is applied on the entire surface of the resultant, and then etched back, as shown in FIG. 2e. The spacer 109 is formed on the sidewall of the gate electrode.

When the formation of the spacer 109 is completed, source / drain formation is performed using the patterned diffusion barrier material layer 106, the metal layer 107, the etch stop pattern cap layer 108, and the spacer 109 as an ion implantation prevention mask. After performing a secondary ion implantation process of implanting ions for the purpose, heat treatment is performed to activate the source / drain regions, thereby forming source and drain regions of the LDD structure.

On the other hand, unlike the manufacturing method described with reference to FIGS. 2A and 2F, the photoresist mask pattern 110 is not removed immediately after the formation of the etch stop pattern cap layer 108, and the metal layer and diffusion prevention In the etching process for patterning the material layer, it may be used together with the etch stop pattern cap layer 108 to be used as a mask pattern and then removed. In this case, since both the photoresist mask pattern and the etch stop pattern cap layer 108 serve as masks, the risk of damaging the gate electrode is reduced.

In the above-described manufacturing method, the method of forming the gate electrode is not limited to the transistor, but can also be used as a method of forming the electrode required in other kinds of elements of the semiconductor device.

As described above, in order to stabilize the gate electrode having a dual structure of TiN / Cu, which is advantageous for high-speed operation and high integration, the present invention provides an anti-etching pattern cap layer formed of a material such as silicon nitride on the gate electrode. As an advantage, preventing copper from being exposed to the atmosphere during the manufacturing process has the advantage of preventing the oxidation of copper and consequently increasing the reliability of the device.

As mentioned above, although this invention was demonstrated to an Example, this invention is not limited to the said Example, The deformation | transformation and improvement are possible within the range of the common knowledge which a person skilled in the art has.

Claims (12)

Semiconductor substrate; An electrode made of a diffusion preventing material layer and a metal layer sequentially formed on the semiconductor substrate through a predetermined insulating film; And an etch stop pattern cap layer formed on said electrode. The semiconductor device of claim 1, further comprising source and drain regions spaced apart from each other to form a transistor channel in the semiconductor substrate, wherein the insulating film is a gate insulating film of a transistor, and the electrode is a gate electrode of a transistor. A semiconductor device characterized by the above-mentioned. The semiconductor device of claim 2, further comprising an etch stop spacer formed on a sidewall of the gate electrode, wherein the source and drain regions have an LDD structure. The semiconductor device of claim 3, wherein the etch stop spacer is formed of silicon nitride (Si ₃ N ₄ ). The semiconductor device of claim 1, wherein the etch stop pattern cap layer is formed of silicon nitride (Si ₃ N ₄ ). The semiconductor device of claim 1, wherein the diffusion barrier material layer is made of titanium nitride (TiN), and the metal layer is made of copper (Cu). Forming a gate insulating film on the semiconductor substrate; Sequentially forming a diffusion barrier material layer and a metal layer on the gate insulating film; Forming an etch stop material layer on top of the metal layer; Forming a mask pattern defining a gate electrode on the etch stop layer; Selectively etching the etch stop layer using the mask pattern to form an etch stop pattern cap layer; Removing the mask pattern; And sequentially etching the metal layer and the diffusion barrier material layer sequentially and selectively while using the etch stop pattern cap layer as an etch stop mask. The method of claim 7, wherein the forming of the etch stop layer is applying a silicon nitride (Si ₃ N ₄ ). 8. The method of claim 7, wherein the forming of the diffusion barrier material layer is a process of applying titanium nitride, and the forming of the metal layer is a process of coating copper. The method of claim 7, further comprising: a primary ion implantation process of implanting ions to form a source and a drain of an LDD structure while using the patterned diffusion barrier material layer, the metal layer, and the etch stop pattern cap layer as an ion implantation prevention mask; Forming a spacer material layer on the entire surface of the resultant product; Forming a spacer on sidewalls of the patterned diffusion barrier material layer, the metal layer, and the etch stop pattern cap layer by etching the spacer material layer into an etch lily; And a secondary ion implantation process using the patterned diffusion barrier material layer, the metal layer, the etch stop pattern cap layer, and the spacer as an ion implantation prevention mask, and implanting ions to form a source and a drain. Method of manufacturing the device. The method of claim 10, wherein the forming of the spacer material layer is applying a silicon nitride (Si ₃ N ₄ ). Forming an insulating film on the semiconductor substrate; Sequentially forming a TiN layer and a copper (Cu) layer on the insulating film; Forming a Si ₃ N ₄ layer on top of the copper layer; Forming a mask pattern defining an electrode on the Si ₃ N ₄ layer; Selectively etching the Si ₃ N ₄ layer using the mask pattern; A step of, using the mask pattern and the patterned Si ₃ N ₄ layer by preventing an etch mask, sequentially, yet selectively etching the copper layer and the TiN layer; And removing the mask pattern.